MB85R1002A RAMXEED | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 23
Technical content
Copyright 2024 RAMXEED LIMITED Fujitsu Semiconductor Memory Solutions Limited has changed its name to RAMXEED Limited. RAMXEED Limited will continue to offer and support existing products while maintaining Fujitsu's part number unchanged. Memory FeRAM
1 M Bit (64 K 16)
DESCRIPTIONS The MB85R1002A is an FeRAM (Ferroelectric Random Access Memory) chip consisting of 65,536 words 16 bits of nonvolatile memory cells fabricated using ferroelectric process and silicon gate CMOS process technologies. The MB85R1002A is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85R1002A can be used for 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E 2PROM. The MB85R1002A uses a pseudo-SRAM interface. FEATURES
- Bit configuration : 65,536 words 16 bits
- LB and UB data byte control
- Read/write endurance : 1010 times / byte
- Data retention : 10 years ( 55 C), 55 years ( 35 C)
- Operating power supply voltage : 3.0 V to 3.6 V
- Low power operation : Operating power supply current 10 mA (Typ) Standby current 10 A (Typ)
- Operation ambient temperature range : 40 C to + 85 C
- Package : 48-pin plastic TSOP RoHS compliant DS501-00004-6v1E
2 DS501-00004-6v1E
PIN ASSIGNMENTS PIN DESCRIPTIONS Pin Number Pin Name Functional Description 1 to 8, 18 to 25 A0 to A15 Address Input pins 29 to 36, 38 to 45 I/O1 to I/O16 Data Input/Output pins
26 CE1 Chip Enable 1 Input pin
12 CE2 Chip Enable 2 Input pin
11 WE Write Enable Input pin
28 OE Output Enable Input pin
14, 15 LB, UB Data Byte Control Input pins 16, 37 VDD Supply Voltage pins Connect all two pins to the power supply. 13, 27, 46 VSS Ground pins Connect all three pins to ground. 9, 10, 17, 47, 48 NC No Connect pins Leave these pins open, or connect to VDD or VSS. A15 A14 A13 A12 A11 A10 NC NC WE CE2 VSS UB LB VDD NC NC NC VSS I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 VDD I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 OE VSS CE1 (TSOP 48) (TOP VIEW)
BLOCK DIAGRAM I/O8 I/O1 I/O16 I/O9 A15 CE2 WE OE CE1 LB UB intOE intWE I/O1 to I/O8 I/O9 to I/O16 Address Latch Row Decoder FeRAM Array 65,536 × 16 Column Decoder S/A
4 DS501-00004-6v1E
FUNCTIONAL TRUTH TABLE Note: L = V IL, H = VIH, X can be either H, L, or , Hi-Z = High Impedance : Latch address and latch data at falling edge, : Latch address and latch data at rising edge *1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read. *2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write. Mode CE 1 CE2 WE OE LB UB I/O1 to I/O8 I/O9 to I/O16 Supply Current Standby Precharge H X X X X X Hi-Z Hi-Z Standby (ISB) X L X X X X X X H H X X X X X X H H Read H H L L L Data Output Data Output Operation (IDD) L H Data Output Hi-Z H L Hi-Z Data Output L H L L L Data Output Data Output L H Data Output Hi-Z H L Hi-Z Data Output Read (Pseudo-SRAM, OE control*1) L H H L L Data Output Data Output L H Data Output Hi-Z H L Hi-Z Data Output Write H L H L L Data Input Data Input L H Data Input Hi-Z H L Hi-Z Data Input L L H L L Data Input Data Input L H Data Input Hi-Z H L Hi-Z Data Input Write (Pseudo-SRAM, WE control*2) L H H L L Data Input Data Input L H Data Input Hi-Z H L Hi-Z Data Input
ABSOLUTE MAXIMUM RATINGS * : All voltages are referenced to VSS 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS *1 : All voltages are referenced to VSS 0 V. *2 : Ambient temperature when only this device is working. Please consider it to be the almost same as the package surface temperature. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Parameter Symbol Rating Unit Min Max Power Supply Voltage* VDD 0.5 4.0 V Input Pin Voltage* VIN 0.5 V DD 0.5 ( 4.0) V Output Pin Voltage* VOUT 0.5 V DD 0.5 ( 4.0) V Operation ambient temperature TA 40 85 oC Storage Temperature TSTG 55 125 oC Parameter Symbol Value Unit Min Typ Max Power Supply Voltage*1 VDD 3.0 3.3 3.6 V Operation ambient temperature*2 TA 40 85 oC
6 DS501-00004-6v1E
ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) *1 : During the measurement of IDD, the Address, Data In were taken to only change once per active cycle. Iout : output current *2 : All pins other than setting pins should be input at the CMOS level voltages such as H VDD 0.2 V, L 0.2 V. Parameter Symbol Condition Value Unit Min Typ Max Input Leakage Current |I LI| V IN = 0 V to VDD 10 A Output Leakage Current |I LO| VOUT = 0 V to VDD, CE1 = VIH or OE = VIH 10 A Operating Power Supply Current*1 IDD CE1 = 0.2 V, CE2 = VDD 0.2 V, Iout = 0 mA 10 15 mA Standby Current*2 ISB CE1 VDD 0.2 V 10 50 A CE2 0.2 V OE VDD 0.2 V, WE VDD 0.2 V LB VDD 0.2 V, UB VDD 0.2 V High Level Input Voltage V IH VDD = 3.0 V to 3.6 V VDD 0.8 VDD 0.5 ( 4.0) V Low Level Input Voltage V IL VDD = 3.0 V to 3.6 V 0.5 0.6 V High Level Output Voltage V OH IOH = 1.0 mA VDD 0.8 V Low Level Output Voltage V OL IOL = 2.0 mA 0.4 V
- AC Characteristics AC Test Conditions Supply Voltage : 3.0 V to 3.6 V Operation Ambient Temperature : 40 oC to 85 oC Input Voltage Amplitude : 0.3 V to 2.7 V Input Rising Time : 5 ns Input Falling Time : 5 ns Input Evaluation Level : 2.0 V / 0.8 V Output Evaluation Level : 2.0 V / 0.8 V Output Load Capacitance : 50 pF (1) Read Cycle Parameter Symbol Value Unit Min Max Read Cycle time tRC 150 ns CE1 Active Time tCA1 120 ns CE2 Active Time tCA2 120 ns OE Active Time tRP 120 ns LB, UB Active Time tBP 120 ns Precharge Time tPC 20 ns Address Setup Time tAS 0 ns Address Hold Time tAH 50 ns OE Setup Time tES 0 ns LB, UB Setup Time tBS 5 ns Output Data Hold time tOH 0 ns Output Set Time tLZ 30 ns CE1 Access Time tCE1 100 ns CE2 Access Time tCE2 100 ns OE Access Time tOE 100 ns Output Floating Time tOHZ 20 ns
8 DS501-00004-6v1E
(2) Write Cycle 3. Pin Capacitance Parameter Symbol Value Unit Min Max Write Cycle Time tWC 150 ns CE1 Active Time tCA1 120 ns CE2 Active Time tCA2 120 ns LB, UB Active Time tBP 120 ns Precharge Time tPC 20 ns Address Setup Time tAS 0 ns Address Hold Time tAH 50 ns LB, UB Setup Time tBS 5 ns Write Pulse Width tWP 120 ns Data Setup Time tDS 0 ns Data Hold Time tDH 50 ns Write Setup Time tWS 0 ns Parameter Symbol Condition Value Unit Min Typ Max Input Capacitance CIN VDD VIN VOUT 0 V, f 1 MHz, TA 25 oC 10 pF Output Capacitance COUT 10 pF
TIMING DIAGRAMS 1. Read Cycle Timing (CE 1 Control) 2. Read Cycle Timing (CE2 Control) tAS tAH tES Valid tRP H or L CE1 CE2 tRC tPC A0 to A15 OE I/O1 to I/O16 tOHZ Hi-Z Valid tOH tLZ Invalid Invalid tCA1 tCE1 :H or L tBS tBP LB, UB tAS tAH Valid tRP H or L CE1 CE2 tRC tPC A0 to A15 OE I/O1 to I/O16 tOHZ Hi-Z Valid tOH tLZ Invalid Invalid tCA2 tCE2 :H or L tBS tBP LB, UB tES
10 DS501-00004-6v1E
- Read Cycle Timing (OE Control) 4. Write Cycle Timing (CE 1 Control) A0 to A15 OE I/O1 to I/O16 tAS tAH tRC tOE tOHZ Hi-Z Valid tOHtLZ Valid H or L tRP Invalid Invalid tPC CE1 CE2 :H or L tBS tBP LB, UB CE1 CE2 LB, UB tCA1 tWC tPC A0 to A15 WE Data In tWP tDH Hi-Z tAHtAS tDS Valid H or L Valid H or L tWS :H or L tBP tBS
- Write Cycle Timing (CE2 Control) 6. Write Cycle Timing (WE Control) CE1 CE2 tCA2 tWC tPC A0 to A15 WE Data In tWP tDH Hi-Z tAHtAS tDS Valid H or L Valid H or L tWS tBS :H or L LB, UB tBP A0 to A15 tWP tWC tDH Hi-Z tAHtAS tDS tBS Valid H or L Valid H or L tPC WE Data In CE1 CE2 :H or L LB, UB tBP
12 DS501-00004-6v1E
POWER ON/OFF SEQUENCE If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed. In case the power is turned on or off, use the power supply reset IC and fix the CE2 to low level, to prevent unexpected writing. Use either of CE1 or CE2, or both to disable control of the device. FeRAM CHARACTERISTICS *1 : Total number of reading and writing defines the minimum value of endurance, as an FeRAM memory operates with destructive readout mechanism. *2 : Minimum values define retention time of the first reading/writing data right after shipment, and these values are calculated by qualification results. NOTES ON USE We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed. Parameter Symbol Value Unit Min Typ Max CE1 level hold time for Power OFF t PD 85 ns CE1 level hold time for Power ON t PU 85 ns Power supply rising time tR 0.05 200 ms Item Min Max Unit Parameter Read/Write Endurance*1 1010 Times/byte Operation Ambient Temperature TA 85 C Data Retention*2 10 Years Operation Ambient Temperature TA 55 C 55 Operation Ambient Temperature TA 35 C CE1 > VCC × 0.8* CE1 : Don't Care CE1 > V CC × 0.8* tPUtRtPD VCC CE2 3.0 V 1.0 V VIH (Min) VIL (Max) 0 V CE1 CE1 VCC CE2 3.0 V 1.0 V VIH (Min) VIL (Max) 0 V * : CE1 (Max) < VDD 0.5 V CE2 0.2 V
ESD AND LATCH-UP
- Current method of Latch-Up Resistance Test Note : The voltage V IN is increased gradually and the current IIN of 300 mA at maximum shall flow. Confirm the latch up does not occur under IIN 300 mA. In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be increased to the level that meets the specific requirement. Test DUT Value ESD HBM (Human Body Model) JESD22-A114 compliant MB85R1002ANC-GE1 |2000 V| ESD MM (Machine Model) JESD22-A115 compliant |200 V| ESD CDM (Charged Device Model) JESD22-C101 compliant |1000 V| Latch-Up (I-test) JESD78 compliant Latch-Up (Vsupply overvoltage test) JESD78 compliant Latch-Up (Current Method) Proprietary method |300 mA| Latch-Up (C-V Method) Proprietary method A VDD VSS DUT V IIN VIN Test terminal Protection Resistor VDD (Max.Rating) Reference terminal
14 DS501-00004-6v1E
- C-V method of Latch-Up Resistance Test Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is considered as one cycle. Repeat this process 5 times. However, if the latch-up condition occurs before completing 5 times, this test must be stopped immediately. REFLOW CONDITIONS AND FLOOR LIFE [ JEDEC MSL ] : Moisture Sensitivity Level 3 (ISP/JEDEC J-STD-020E) CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS. VDD VSS DUT VIN SW 1 2 C 200pF V A Test terminal Protection Resistor VDD (Max.Rating) Reference terminal
ORDERING INFORMATION *: Please contact our sales office about minimum shipping quantity. Part Number Package Shipping form Minimum shipping quantity MB85R1002ANC-GE1 48-pin plastic TSOP Tray *
16 DS501-00004-6v1E
PACKAGE DIMENSIONS 48-pin plastic TSOP Lead pitch 0.50 mm Pa ck age width × pa ck age length 12.00 mm × 12.40 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm MAX 48-pin plastic TSOP MB85R1002ANC-GE1 #12.00 ±0.10 (.472 ±.004) 0.08(.003) 0.50(.020) 0.22 (.009 ) 2524 A0.145 (.006 ) M0.10(.004) Details of A part 0~8 (.024 ±.006) 0.60 ±0.15 INDEX (STAND OFF) +0.05 –0.03 +.002 –.001 +.002 –.002 +0.05 –0.04 (MOUNTING HEIGHT) 0.25(.010) Di mensions in mm (inches). No te: The values in parentheses are reference values. Note 1) # : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) * : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder.
MARKING(example) MB85R1002A JAPAN
1150 E00
[MB85R1002ANC-GE1] [TSOP 48] MB85R1002A
18 DS501-00004-6v1E
SHIPPING FORM 1. Tray
1.1 Tray Dimensions
TSOP48 Maximum storage capacity pcs/tray pcs/inner box pcs/outer box 128 1280 5120 (Dimensions in mm) Material : Conductive polyphenyleneether Heat proof temperature : 125 C MAX 135.9 7 × 14.9 = 104.315.8 15.8 15 × 19.0 = 285 322.6 315 7.62 1.27 1515 8-NO HOLES A A C3 B R4.75 0.76 255.3 34.3 25.4 25.4 2.54 7.62 1.27 1 12.2 13.564 0.9 1.271 1 815.8 14.9 7.62 1.27 1 11.8 14.2 15.564 0.9 1.27 1.27 1 1 1015 19 SEC.A-A SEC.B-B B
1.2 IC orientation
IC) 7UD\\ &KDPIHUHGFRUQHU
20 DS501-00004-6v1E
1.3 Product label indicators
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm x 100mm) Supplemental Label (20mm x 100mm)] C-3 Label Supplemental Label Perforated line (Part number) (Part number) (Control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Part number bar code) (Part number and quantity) (Control number bar code) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX (Part number)XXXXXXXXXXXXXX (Comment)XXXXXXXXXXXXXX (Control number )XXXXXXXXXX (LEAD FREE mark)
1.4 Dimensions for Containers
(1) Dimensions for inner box (2) Dimensions for outer box L W H 165 360 75 (Dimensions in mm) L W H 355 385 195 (Dimensions in mm) L W H L W H
22 DS501-00004-6v1E
MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn on the left side of that page. Page Section Change Results 17 MARKING New marking format is added.
Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan https://ramxeed.com/ All Rights Reserved. RAMXEED LIMITED, its subsidiaries and affiliates (collectively, "RAMXEED ") reserves the right to make changes to the infor- mation contained in this document without notice. Please contact your RAMXEED sales representatives before order of RAMXEED device. Information contained in this document, such as descriptions of function and application circuit examples is presented solely for reference to examples of operations and uses of RAMXEED device. RAMXEED disclaims any and all warranties of any kind, wheth- er express or implied, related to such information, including, without limitation, quality, accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the RAMXEED device based on such informa- tion, you must assume any responsibility or liability arising out of or in connection with such information or any use thereof. RAMX- EED assumes no responsibility or liability for any damages whatsoever arising out of or in connection with such information or any use thereof. Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or any other intellectual property rights of RAMXEED or any third party by license or otherwise, express or implied. RAMXEED assumes no responsibility or liability for any infringement of any intellectual property rights or other rights of third parties resulting from or in connection with the information contained herein or use thereof. The products described in this document are designed, developed and manufactured as contemplated for general use including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater and artificial satellite). RAMXEED shall not be liable for you and/or any third party for any claims or damages arising out of or in connection with above-mentioned uses of the products. Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and technical information described herein. All company names, brand names and trademarks herein are property of their respective owners.