MS85R4M1TA

MS85R4M1TA RAMXEED | Alldatasheet

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Copyright 2024 RAMXEED LIMITED DS501-00093-1v1-E Fujitsu Semiconductor Memory Solutions Limited has changed its name to RAMXEED Limited. RAMXEED Limited will continue to offer and support existing products while maintaining Fujitsu's part number unchanged. Memory FeRAM

4 M (512 K × 8) Bit

 DESCRIPTIONS The MS85R4M1TA is an FeRAM (Ferroelectric Random Access Memory) chip consisting of 524,288 words × 8 bits of nonvolatile memory cells fabricated using ferroelectric process and silicon gate CMOS process technologies. The MS85R4M1TA is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MS85R4M1TA can be used for 10 14 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. The MS85R4M1TA uses a pseudo-SRAM interface.  FEATURES

• Bit configuration : 524,288 words × 8 bits
• Read/write endurance : 1014 times ( + 85 °C), 1013 times ( + 105 °C),
• Data retention : 10 years ( + 105 °C), 40 years ( + 85 °C), over 200 years ( + 35 °C)
• Operating power supply voltage : 1.8 V to 3.6 V
• Low power operation : Operating power supply current 16 mA (Max) Standby current 150 μ A (Max) Sleep current 12 μ A (Max)
• Operation ambient temperature range : − 40 °C to + 105 °C
• Package : 44-pin plastic TSOP RoHS compliant

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 PIN ASSIGNMENTS PIN ASSIGNMENTS(Continued) /OE /ZZ VSS VSS I/O7 I/O6 VSS VDD I/O5 I/O4 (NC) VSS (NC) A10 A11 A12 A13 TSOP 44 (TOP VIEW) /CE (NC) (NC) I/O0 I/O1 VDD VSS I/O2 I/O3 (NC) (NC) /WE A18 A17 A16 A15 A14

 PIN DESCRIPTIONS Pin Number(TSOP) Pin Name Functional Description 39, 5 to 1, 44 to 42, 27 to 18 A0 to A18 Address Input pins Select 262,144 words in FeRAM memory array by 18 Address Input pins. When these address inputs are changed during /CE equals to “L” level, reading operation of data selected in the address after transition will start. 9 to 10, 13 to 14, 31 to 32, 35 to 36 I/O0 to I/O7 Data Input/Output pins These are 8 bits bidirectional pins for reading and writing. 6 /CE Chip Enable Input pin In case the /CE equals to “L” level and /ZZ equals to “H” level, device is activated and enables to start memory access. In writing operation, input data from I/O pins are latched at the rising edge of /CE and written to FeRAM memory array. 17 /WE Write Enable Input pin Writing operation starts at the falling edge of /WE. Input data from I/O pins are latched at the rising edge of /WE and written to FeRAM memory array. 41 /OE Output Enable Input pin When the /OE is “L” level, valid data are output to data bus. When the /OE is “H” level, all I/O pins become high impedance (High-Z) state. 40 /ZZ Sleep Mode Input pin When the /ZZ becomes to “L” level, device transits to the Sleep Mode. During reading and writing operation, /ZZ pin shall be hold “H” level. 11, 33 VDD Supply V oltage pins Connect all two pins to the power supply. 12, 29, 34, 37, 38 VSS Ground pins Connect all pins to ground. 7 to 8, 15 to 16, 28, 30 NC No connected pins Leave them open or connect to VDD or VSS. Note: Please refer to the timing diagram for functional description of each pin.

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 BLOCK DIAGRAM  FUNCTIONAL TRUTH TABLE Operation Mode /CE /WE /OE A0 to A2 A3 to A18 /ZZ Standby H × × × × H Read(/CE Control) ↓ H L H or L H or L H Address Access Read L H L H or L ↑ or ↓ H Write(/CE Control)*1 ↓ L × H or L H or L H Write(/WE Control)*1*2 L ↓ × H or L H or L H Address Access Write*1*3 L ↓ × H or L ↑ or ↓ H Page Read L H L ↑ or ↓ H or L H Page Address Write L ↓ H ↑ or ↓ H or L H Note: H= “H” level, L= “L” level, ↑= Rising edge, ↓ = Falling edge, ×= H, L, ↓ or ↑ *1: In writing cycle, input data is latched at early rising edge of /CE or /WE. *2: In writing sequence of /WE control, there exists time with data output of reading cycle at the falling edge of /CE. *3: In writing sequence of Address Access Write, there exists time with data output of reading cycle at the address transition. FRAM Array 524,288×8 Colum n Decoder / Sense Amp. / Write Amp. A0 to A18 /CE /WE /OE /ZZ Address Control c ircui ts Row Decoder I/O0 to I/O7

 State Transition Diagram Standby RD/WR Operation Sleep Power Up /ZZ=L /CE=L, /ZZ=H /CE=H,/ZZ=H /ZZ=H

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 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min Max Power Supply Voltage* VDD − 0.5 + 4.0 V Input Pin Voltage* VIN − 0.5 VDD + 0.5 ( ≤ 4.0) V Output Pin Voltage* VOUT − 0.5 VDD + 0.5 ( ≤ 4.0) V Operation Ambient Temperature TA − 40 + 105 °C Storage Temperature Tstg − 55 + 125 °C * : All voltages are referenced to VSS (ground 0 V). WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.  RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min Typ Max Power Supply Voltage*1 VDD 1.8 3.3 3.6 V Operation Ambient Temperature*2 TA − 40 ― + 105 °C *1: All voltages are referenced to VSS (ground 0 V). *2: Ambient temperature when only this device is working. Please consider it to be the almost same as the package surface temperature. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.

 ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) Parameter Sym -bol Condition Value Unit Min Typ Max(TA ≤85°C) Max(TA ≥ 85°C) Input Leakage Current |ILI| VIN = 0V to VDD ― ― 5 μA Output Leakage Current |ILO| VOUT = 0V to VDD /CE = VIH or /OE = VIH ― ― 5 μA Operating Power Supply Current*1 IDD /CE = 0.2 V, Iout = 0 mA ― 13.5 16 16 mA Standby Current ISB /ZZ ≥ VDD − 0.2V /CE, /WE, /OE ≥ VDD − 0.2V Others ≥ VDD − 0.2V or ≤ 0.2V ― 12 100 150 μA Sleep Current IZZ /ZZ = VSS /CE, /WE, /OE ≥ VDD − 0.2V Others ≥ VDD − 0.2V or ≤ 0.2V ― 3.5 10 12 μA High Level Input Voltage VIH VDD = 1.8V to 3.6V VDD × 0.8 ― VDD + 0.3 V Low Level Input Voltage VIL VDD = 1.8V to 3.6V − 0.3 ― VDD × 0.2 V High Level Output Voltage VOH1 VDD = 2.5V to 3.6V IOH = − 1.0mA VDD × 0.8 ― ― V VOH2 VDD = 1.8V to 2.5V IOH = − 100μA VDD − 0.2 ― ― Low Level Output Voltage V OL1 VDD = 2.5V to 3.6V IOL = 2.0mA ― ― 0.4 V VOL2 VDD = 1.8V to 2.5V IOL = 150μA ― ― 0.2 *1: During the measurement of IDD, all Address and I/O were taken to only change once per active cycle. Iout : output current

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1. AC Characteristics ・AC Test Conditions Power Supply Voltage : 1.8 V to 3.6 V Operation Ambient Temperature : − 40 °C to + 105 °C Input Voltage Amplitude : 0 V / VDD Input Rising Time : 3 ns Input Falling Time : 3 ns Input Evaluation Level : VDD/2 Output Evaluation Level : VDD/2 Output Load Capacitance : 30 pF (1) Read Cycle Parameter Symbol TA≤+85°C Unit Value (VDD=1.8V to 2.5V) Value (VDD=2.5V to 3.6V) Min Max Min Max Read Cycle time(/CE control) tRC 120 ― 120 ― ns Read Cycle time(Address access) tRCA 135 ― 120 ― ns /CE Access Time tCE ― 65 ― 65 ns Address Access Time tAA ― 135 ― 120 ns /CE Output Data Hold time tOH 0 ― 0 ― ns Address Access Output Data Hold time tOAH 20 ― 20 ― ns /CE Active Time tCA 65 ― 65 ― ns Pre-charge Time tPC 55 ― 55 ― ns Address Setup Time tAS 0 ― 0 ― ns Address Hold Time tAH 65 ― 65 ― ns /CE↑ to Address Transition time＊1 tCAH 0 ― 0 ― ns /OE Access Time tOE ― 35 ― 20 ns /CE Output Floating Time*1 tHZ ― 10 ― 10 ns /OE Output Floating Time tOHZ ― 10 ― 10 ns Address Transition Time*1 tAX ― 15 ― 15 ns *1: Same parameters with the Write cycle.

TA≥+85°C Unit Value (VDD=1.8V to 2.5V) Value (VDD=2.5V to 3.6V) Min Max Min Max Read Cycle time(/CE control) tRC 125 ― 125 ― ns Read Cycle time(Address access) tRCA 140 ― 125 ― ns /CE Access Time tCE ― 70 ― 70 ns Address Access Time tAA ― 140 ― 125 ns /CE Output Data Hold time tOH 0 ― 0 ― ns Address Access Output Data Hold time tOAH 20 ― 20 ― ns /CE Active Time tCA 70 ― 70 ― ns Pre-charge Time tPC 55 ― 55 ― ns Address Setup Time tAS 0 ― 0 ― ns Address Hold Time tAH 70 ― 70 ― ns /CE↑ to Address Transition time＊1 tCAH 0 ― 0 ― ns /OE Access Time tOE ― 35 ― 20 ns /CE Output Floating Time*1 tHZ ― 10 ― 10 ns /OE Output Floating Time tOHZ ― 10 ― 10 ns Address Transition Time*1 tAX ― 15 ― 15 ns *1: Same parameters with the Write cycle. (2) Write Cycle Parameter Symbol TA≤+85°C Unit Value (VDD=1.8V to 2.5V) Value (VDD=2.5V to 3.6V) Min Max Min Max Write Cycle Time tWC 120 ― 120 ― ns /CE Active Time tCA 65 ― 65 ― ns /CE↓ to /WE↑ Time tCW 65 ― 65 ― ns Pre-charge Time tPC 55 ― 55 ― ns Write Pulse Width tWP 20 ― 20 ― ns Address Setup Time tAS 0 ― 0 ― ns Address Hold Time tAH 65 ― 65 ― ns /WE↓ to /CE↑ Time tWLC 20 ― 20 ― ns Address Transition to /WE↑ Time tAWH 135 ― 120 ― ns /WE↑ to Address Transition Time tWHA 0 ― 0 ― ns Data Setup Time tDS 10 ― 10 ― ns Data Hold Time tDH 0 ― 0 ― ns /WE Output Floating Time tWZ ― 10 ― 10 ns /WE Output Access Time*1 tWX 10 ― 10 ― ns Write Setup Time*1 tWS 0 ― 0 ― ns Write Hold Time*1 tWH 0 ― 0 ― ns /CE Output Floating Time tHZ ― 10 ― 10 ns Address transition Time tAX ― 15 ― 15 ns

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TA≥+85°C Unit Value (VDD=1.8V to 2.5V) Value (VDD=2.5V to 3.6V) Min Max Min Max Write Cycle Time tWC 125 ― 125 ― ns /CE Active Time tCA 70 ― 70 ― ns /CE↓ to /WE↑ Time tCW 70 ― 70 ― ns Pre-charge Time tPC 55 ― 55 ― ns Write Pulse Width tWP 20 ― 20 ― ns Address Setup Time tAS 0 ― 0 ― ns Address Hold Time tAH 70 ― 70 ― ns /WE↓ to /CE↑ Time tWLC 20 ― 20 ― ns Address Transition to /WE↑ Time tAWH 140 ― 125 ― ns /WE↑ to Address Transition Time tWHA 0 ― 0 ― ns Data Setup Time tDS 10 ― 10 ― ns Data Hold Time tDH 0 ― 0 ― ns /WE Output Floating Time tWZ ― 10 ― 10 ns /WE Output Access Time*1 tWX 10 ― 10 ― ns Write Setup Time*1 tWS 0 ― 0 ― ns Write Hold Time*1 tWH 0 ― 0 ― ns /CE Output Floating Time tHZ ― 10 ― 10 ns Address transition Time tAX ― 15 ― 15 ns (3) Page Mode Read/Write Cycle Parameter Symbol Value (VDD=1.8V to 2.5V) Value (VDD=2.5V to 3.6V) Unit Min Max Min Max Page Mode Write Cycle Time tPWC 25 ― 25 ― ns Page Mode Write Pulse Width tWPP 15 ― 15 ― ns Page Address Setup Time (/WE=L) tASP 8 ― 8 ― ns Page Address Hold Time (/WE=L) tAHP 15 ― 15 ― ns Page Address Access Time tAAP ― 25 ― 25 ns Page Address Data Hold Time tOHP 3 ― 3 ― ns Page Mode Read Cycle Time tPRCA 25 ― 25 ― ns Page Mode Write Pre Charge Width tWPHP 7 ― 7 ― ns (4) Power ON/OFF Sequence and Sleep Mode Cycle Parameter Symbol Value Unit Min Max /CE level hold time for Power ON tPU 450 ― μs /CE level hold time for Power OFF tPD 85 ― ns Power supply rising time tVR 50 ― μs/V Power supply falling time tVF 100 ― μs/V /ZZ active time tZZL 1 ― μs Sleep mode enable time tZZEN ― 0 μs /CE level hold time for Sleep mode release tZZEX 450 ― μs

1. Pin Capacitance Parameter Symbol Condition Value Unit Min Typ Max Input Capacitance CIN VDD = 3.3 V, VIN = VOUT = 0V~VDD, f = 1 MHz, TA = + 25 °C ― ― 6 pF Input/Output Capacitance (I/O pin) CI/O ― ― 8 pF /ZZ Pin Input Capacitance CZZ ― ― 8 pF  AC Test Load Circuit Output 1.2kΩ 30pF VDD 0.95kΩ

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 TIMING DIAGRAMS 1. Read Cycle Timing 1 (/CE, /OE Control) 2. Read Cycle Timing 2 (Address Access) XXX：H or L tPC tAS tAH tCE tOE tCA tHZ tOHZ tOH A0～A18 I/O0～I/O7 /CE /OE tRC Valid Address Valid Output Data tCAH XXX：H or L tRCA tAA tRCA A3～A18 I/O0～I/O7 /CE = /OE = = L,/WE = H Valid Address 1 Valid Output Data 1 tOAH tAA tOAH Valid Address 2 Valid Output Data 2 Previous Valid Output Data tAX tAX

1. Read Cycle Timing 3 (Page Access) 4. Write Cycle Timing 1 (/WE Control) Output Data Output DataInput Data tAH XXX：H or L tPC tAS tCA A0～A18 I/O0～I/O7 /CE /WE tWC tWZ tHZ tWLC tCW tWP tDS tDH tWH *:In case /OE=L, be carefull not any bus conflicts occur. *:In case /OE=L, invalid data are output. XXX：H or L tPC tAS tCE tHZ tOHZ A3～A18 /OE /CE A0～A2 tRC Data０ Column１ Column２ Data１ Data２ Column０ tOE tOHP tAAP I/O0～I/O7 tAX tPRCA tPRCA

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1. Write Cycle Timing 2 (/CE Control) 6. Write Cycle Timing 3 (Address Access and /WE Control) Output Data Output DataInput Data Input Data *:In case /OE=L, be carefullnot any bus conflicts occur. *:In case /OE=L, invalid data are output. XXX：H or L A0～A18 I/O0～I/O7 /WE tWZ tAWH tWHA tDS tDH tWX tWC /CE = /OE = L tWC tPC tAS tCA A0～A18 /CE /WE tWC XXX：H or L tDH I/O0～I/O7 Input Data tDS

1. Write Cycle Timing 5 (Page Address Access) 8. Sleep Mode Timing tPC tZZL tZZEX /WE /CE /ZZ I/O0 ～ I/O7 tZZEN XXX：H or L tPC tAS tCA A2～A18 /WE /CE A0～Ａ2 tWC Column1 Column2Column０ tWP tDS tDH Input Data tDS tDH Input Data tDS tDH Input Data tCW tAHP tASP tWLC tPWC I/O0～I/O7 tWPHP tWPP

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 POWER ON/OFF SEQUENCE When applying relatively short term VDD pulse whose peak is more than 1.7V , it is required to set falling time, t VF more than 0.4ms/V . (In case VDD rises over 1.7V and falls just after that, if this term is short, device may lose its function.)  FeRAM CHARACTERISTICS Item Min Max Unit Parameter Read/Write Endurance*1 1013 *2 ― Times Operation Ambient Temperature TA = + 105 °C 1014 ― Operation Ambient Temperature TA = + 85 °C Data Retention*3 10 ― Years Operation Ambient Temperature TA = + 105 °C

40 Operation Ambient Temperature TA = + 85 °C

95 ― Operation Ambient Temperature TA = + 55 °C ≥ 200 ― Operation Ambient Temperature TA = + 35 °C *1: The values for Read/Write Endurance apply to the total number of read and write operations per row in FeRAM. This is because FeRAM needs writing operation after each reading operations. When switching rows, the number of Read/Write operations is counted for each selected row. However, if only addresses A0, A1 and A2 are switched, no row switching occurs. The memory consists of 64 internal outputs per row, and switching only A0, A1 and A2 selects 8 of these outputs. Each row in the memory array has 64 internal outputs, and 8 outputs are selected by A0, A1 and A2. Therefore, once a certain address is selected, switching only A0, A1 and A2 does not change the selected row, and the Read/Write count is totaled as one operation. For other address switches, each corresponding row is counted once. *2: Evaluating about minimum Read/Write Endurance at +105℃, over 1013 times. *3: The minimum value of Date Retention refers to data retention term from first read/write after the device shipped. The value is estimated from qualification results.  NOTE ON USE

• We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed. * : /CE (Max) < VDD+0.3V /CE Don’t Care tPD tPU tVF tVR /CE VDD VSS VIH(Min) VIL(Max) VDD(Min) 1.0V VDD VIH(Min) VIL(Max) VSS

 ESD AND LATCH-UP Test DUT Value ESD HBM (Human Body Model) JESD22-A114 compliant MS85R4M1TAFN-G-JAE2 ≥ |2000 V| ESD CDM (Charged Device Model) JESD22-C101 compliant ≥ |1000 V| Latch-Up (C-V Method) Proprietary method ≥ |200 V|  REFLOW CONDITIONS AND FLOOR LIFE [ JEDEC MSL ] : Moisture Sensitivity Level 3 (IPC/JEDEC J-STD-020E)  CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS.

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 ORDERING INFORMATION Part Number Package Shipping form Minimum shipping quantity MS85R4M1TAFN-G-JAE2 44-pin plastic TSOP Tray ―* *: Please contact our sales office about minimum shipping quantity.

 PACKAGE DIMENSIONS 44-pin plastic TSOP Lead pitch Package width × package length 10.16 × 18.41mm Lead shape Sealing method Mounting height MS85R4M1TAFN-G-JAE2 Dimensions in mm. 0.8mm Gullwing Plastic mold 1.2mm (max.) 44-pin plastic TSOP MS85R4M1TAFN-G-JAE2 Note 1): These dimensions do not include resin protrusion. Note 2): Pins width do not include tie bar cutting remainder. Pins width and pins thickness include plating thickness. [44] [23] LEAD No. [1] [22] INDEX 18.41±0.10 0.80TYP 0.25 to 0.40

1.20 MAX

0.05 MIN

0.10 MAX

10.16±0.10 10.16±0.10 11.76±0.20 0.10 to 0.21 0.50±0.１５ 0.25TYP 0～8°

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 MARKING(Examples) [MS85R4M1TAFN-G-JAE2] [44pin Plastic TSOP] MS85R4M1TA: Product name E2: (Lead free code)

2300 Y00:2300(Year and Week code)＋Y00（Trace code）

 PACKING MS85R4M1TAFN-G-JAE2

1.1 Tray dimensions

pcs/tray pcs/inner box pcs/outer box 126 1260 (10trays) 5040 (4 inner boxes, Max) TSOP 44

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1.2 IC orientation

1.3 Product label indicators

Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm x 100mm) Supplemental Label (20mm x 100mm)] (Part number) (Part number) (Control number bar code) XX/X X XXXX -XXX XXX XXXX -XXX XXX (L ot Number and qua ntity) (Package coun t) (Part number bar code) (Part number and qua n tity) (Control number bar code) QC PASS XXXXXXXXXXXXXX XXX X/XX/XX (Packed years/mo nth/d ay) ASSEMBLED IN xxxx (3N)1XXXXXXXXXXXXXX XXX (Quantity) (3N)2XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX (Part number)XXXXXXXXXXXXXX (Comme nt)XXXXXXXXXXXXXX (Control number )XXXXXXXXXX (LEAD FREE mark) C3-Label Perforated line Supplemental Label

1.4 Dimensions for container

(1) Dimensions for inner box L W H 162 360 90 (Dimensions in mm) (2) Dimensions for outer box L W H 410 375 225 (D imensions in mm) L W H L W H

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 MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn on the left side of that page. Page Section Change Results P.1,16 Read/write endurance 1014 times/64bits → 1014 times(+85℃)

Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan https://ramxeed.com/ All Rights Reserved. RAMXEED LIMITED, its subsidiaries and affiliates (collectively, "RAMXEED") reserves the right to make changes to the information contained in this document without notice. Please contact your RAMXEED sales representatives before order of RAMXEED device. Information contained in this document, such as descriptions of function and application circuit examples is presented solely for reference to examples of operations and uses of RAMXEED device. RAMXEED disclaims any and all warranties of any kind, whether express or implied, related to such information, including, without limitation, quality, accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the RAMXEED device based on such information, you must assume any responsibility or liability arising out of or in connection with such information or any use thereof. RAMXEED assumes no responsibility or liability for any damages whatsoever arising out of or in connection with such information or any use thereof. Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or any other intellectual property rights of RAMXEED or any third party by license or otherwise, express or implied. RAMXEED assumes no responsibility or liability for any infringement of any intellectual property rights or other rights of third parties resulting from or in connection with the information contained herein or use thereof. The products described in this document are designed, developed and manufactured as contemplated for general use including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater and artificial satellite). RAMXEED shall not be liable for you and/or any third party for any claims or damages arising out of or in connection with above-mentioned uses of the products. Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and technical information described herein. All company names, brand names and trademarks herein are property of their respective owners. MS85R4M1TA