MB85AS12MT RAMXEED | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 27
Technical content
Copyright 2024 RAMXEED LIMITED Fujitsu Semiconductor Memory Solutions Limited has changed its name to RAMXEED Limited. RAMXEED Limited will continue to offer and support existing products while maintaining Fujitsu's part number unchanged. Memory ReRAM 12M (1536 K 8) Bit SPI MB85AS12MT DESCRIPTION MB85AS12MT is a ReRAM (Resistive Random Access Memory) chip in a configuration of 1,572,864 words 8 bits, using the resistance-variable memory process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85AS12MT adopts the Serial Peripheral Interface (SPI). MB85AS12MT is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85AS12MT can be used for 5 105 rewrite operations. FEATURES
- Bit configuration : 12 Mbits (1,572,864 words 8 bits)
- Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
- Write buffer size : 256 bytes
- Operating frequency : 10 MHz (Max)
- Data endurance : 5 105 times / 4bytes* *4 bytes are selected by A1 to A0.
- Data retention : 10 years (+85 C)
- Operating power supply voltage : 1.6 V to 3.6 V
- Operating power supply current : Write current 1.5 mA (Typ) Read current 0.15 mA (Typ@5 MHz) Standby current 65 A (Typ) Sleep current 6 A (Typ)
- Operation ambient temperature range : -40 C to +85 C
- Package : 11-pin WLP RoHS compliant DS501-00071-1v1-E
2 DS501-00071-1v1-E
PIN ASSIGNMENT PIN FUNCTIONAL DESCRIPTIONS Pin Name Functional description CS Chip Select pin This is an input pin to make chips select. When CS is “H” level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before inputting op-code. SCK Serial Clock pin This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. SI/SO Serial Data Input/Output pin This is an input/output pin of serial data. It inputs op-code, address, and writing data.In case of read command, it outputs read data of ReRAM memory cell array or data of sta- tus register after inputing op-code/address. VDD Supply Voltage pin VSS Ground pin (BOTTOM VIEW) 11-pin WLP Type-A VSS VSS VSS VSS VSS VSS VSSVDD SI/SO SCK CS
BLOCK DIAGRAM SPI MODE MB85AS12MT corresponds to the SPI mode 0 (CPOL 0, CPHA 0) , and SPI mode 3 (CPOL 1, CPHA 1) . SCK SO SI Serial-Parallel Converter ReRAM Cell Array 1,572,864 x 8 Column Decoder/Sense Amp/ Write Amp ReRAM Status Register Data Register Parallel-Serial Converter Control Circuit Address Counter Row DecoderCS SCK SI CS SCK SI CS 76543210 76543210 MSB LSB MSB LSB SPI Mode 0 SPI Mode 3
4 DS501-00071-1v1-E
SERIAL PERIPHERAL INTERFACE (SPI) MB85AS12MT works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped with SPI port. SCK CS SI/SO MB85AS12MT System Configuration Microcontroller
STATUS REGISTER OP-CODE MB85AS12MT accepts 10 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command are not performed. Bit No. Bit Name Function
7 WPEN
This is bit composed of nonvolatile memories, writing with the WRSR command is possible. These bits are not used but they are read with the RDSR command. Initial value is “0”. 6 to 4 Not Used Bits These are bits composed of volatile memories, writing with the WRSR com- mand is possible. These bits are not used but they are read with the RDSR command. Initial value is “000”.
3 BP1 Block Protect
This is a bit composed of nonvolatile memory. This defines size of write protect block for the WRITE command (refer to “ BLOCK PROTECT”). Writing with the WRSR command and reading with the RDSR command are possible. 2 BP0
1 WEL
This indicates ReRAM Array and status register are writable. The WREN com- mand is for setting, and the WRDI command is for resetting. With the RDSR command, reading is possible but writing is not possible with the WRSR com- mand. WEL is reset after the following operations. After power ON. The rising edge of CS after WRDI command recognition. The end of writing process after WRSR command recognition. The end of writing process after WRITE command recognition.
0 WIP
This indicates ReRAM Array and status register are in writing process. During this writing process, any commands except RDSR will not be executed (refer to “ WRITING OPERATION OF NONVOLATILE MEMORY 2. WIP polling”). With the RDSR command, reading is possible but writing is not possible with the WRSR command. Name Description Op-code WREN Set Write Enable Latch 0000 0110B WRDI Reset Write Enable Latch 0000 0100B RDSR Read Status Register 0000 0101B WRSR Write Status Register 0000 0001B READ Read Memory Code 0000 0011B WRITE Write Memory Code 0000 0010B RDID Read Device ID 1001 1111B RDUID Read Device ID and Unique ID 1000 0011B SLEEP Enter Sleep Mode (Power Down Mode) 1011 1001B PWDN 1110 0010B
6 DS501-00071-1v1-E
COMMAND WREN The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before writing operation (WRSR command and WRITE command) . WRDI The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRSR command and WRITE command) are not performed when WEL is reset. SO SCK SI CS 00000110 High-Z 7 6 5 432 1 0 InvalidInvalid SO SCK SI CS 00000100 High-Z 7 6 5 432 1 0 InvalidInvalid
RDSR The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising of CS. WRSR The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register cannot be written. The SI value corresponding to bit 0 is ignored. WP signal level shall be fixed before performing WRSR command, and do not change the WP signal level until the end of command sequence. After rising edge of CS, MB85AS12MT starts writing operation to nonvolatile register and set WIP bit in status register to “1”. After this writing operation has finished, reset this WIP bit from “1” to “0”. Although the RDSR command is executable for WIP polling during this writing process, any other commands will not be per - formed. SO SCK SI CS 00000101 High-Z 7 6 5 432 1 0 Invalid MSB 7 6 5 432 1 0 Data Out LSB Invalid SO SCK SI CS 00000001 7 6 5 432 1 0 Data In MSB 7 6 5 432 1 0 High-Z LSB 76543 210 Instruction
8 DS501-00071-1v1-E
READ The READ command reads ReRAM memory cell array data. Arbitrary 24 bits address and op-code of READ are input to SI. The 3-bit upper address bit is invalid. And in case of designating address other than effective region (180000H to 1FFFFF H), the command itself is ignored. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address (17FFFFH), it rolls over to the starting address, and reading cycle keeps on infinitely. WRITE The WRITE command writes data to ReRAM memory cell array. WRITE op-code, arbitrary 24 bits of address and 8 bits of writing data are input to SI. The 3-bit upper address bit is invalid. And in case of designating address other than effective region (180000H to 1FFFFFH), the command itself is ignored. During the CS is low, input writing data are temporary saved in the data register. The maximum writing data size is 256 bytes during this CS = low period. If the input writing data are more than 8 bits, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over to the starting address, and writing cycle can be continued up to 256 bytes (which is the size of data register). Data exceed 256 bytes can not be written. After rising edge of CS , MB85AS12MT starts writing operation to nonvolatile memory and set WIP bit in status register to “1”. After this writing operation has finished, reset this WIP bit from “1” to “0”. Although the RDSR command is executable for WIP polling during this writing process, any other commands will not be performed. CS SCK SI Invalid MSB LSB MSB Data Out LSBHigh-Z Invalid 450123 2 6 2 7 6 7 8 9 10 11 12 13 14 15 38 39 28 29 30 31 32 33 34 35 36 37 00000011X 32X X 20 19 18 17 16 54 SO 76 3 54 210 CS SCK Data In SI MSB LSB MSB LSB High-Z 10 110123456789 14 15 26 31 3212 13 27 28 29 30 33 34 35 36 37 38 39 0000001 30 X X X 20 19 2 1 0 SO 18 17 16 5 4 3 2 1 07654
RDID The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte). In the RDID command, SO holds the output state of the last bit in 32-bit Device ID until CS is risen. SO SCK SI CS MSB 7 6 5 4 3 2 1 0 Data OutData Out High-Z LSB 11 109 8 33 32 31 39 38 37 36 35 34 Invalid 30 2829 31 10011111 20 1 364 5 7 8 bit 7 6 5 4 3 2 1 0 Hex Manufacturer ID 0 0 0 0 0 1 0 0 04 H Fujitsu Continuation code 0 1 1 1 1 1 1 1 7F H Proprietary use Density Hex Product ID (1st Byte) 1 0 1 1 1 1 0 0 BC H Density: 11100B 12 Mbit Proprietary use Hex Product ID (2nd Byte) 0 0 0 0 0 0 1 1 03 H
10 DS501-00071-1v1-E
RDUID The RDUID command reads (common) Device ID and (each chip-specific) Unique ID. After performing RDUID op-code to SI, 96-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output is in order of Manufacturer ID (8bit) / Continuation code (8bit) / Product ID (1st Byte) / Product ID (2nd Byte) as Device ID and Lot ID (40bit) / Wafer ID (8bit) / Chip ID (16bit) as Unique ID. In the RDUID command, SO holds the output state of the last bit in 96-bit Device ID and Unique ID until CS is risen. SO SCK SI CS MSB 7 6 5 4 3 2 1 0 Data OutData Out High-Z LSB 11 10 9 8 97 9695 103 102 101 10099 98 Invalid 94 9293 95 10000011 20 1 364 5 7 8 Bits Field Value Description Device ID [95:88] Manufacture ID 04h Fujitsu Device ID [87:80] Continuation code 7Fh Device ID [79:72] Product ID BCh 101b: Proprietary use 11100b: Density (12 Mbit) Device ID [71:64] Product ID 03h Proprietary use Unique ID [63:24] Lot ID 64 bit Unique IDUnique ID [23:16] Wafer ID Unique ID [15:0] Chip ID
SLEEP/PWDN The SLEEP/PWDN command shifts the LSI to a low power mode called “SLEEP mode” (“Power Down mode”). The transition to the SLEEP mode (Power Down mode) is carried out at the rising edge of CS after operation code in the SLEEP (PWDN) command. However, when at least one SCK clock is inputted before the rising edge of CS after operation code in the SLEEP (PWDN) command, this SLEEP (PWDN) command is canceled. After the SLEEP mode (Power Down mode) transition, SCK and SI/SO inputs are ignored. Returning to a normal operation from the SLEEP mode (Power Down mode) is carried out after t REC time from the falling edge of CS (see the figure below). It is possible to return CS to H level before t REC time. However, it is prohibited to bring down CS to L level again during tREC period. Enter Sleep Mode CS SCK SI Invalid Invalid High-Z Sleep Mode Entry 67012345 SO 11011100 CS CS tREC Exit Sleep Mode Sleep Mode Exit tCSWL From this time Command input enable
12 DS501-00071-1v1-E
WRITING OPERATION OF NONVOLATILE MEMORY Each input data is not written to the nonvolatile memory by unit of byte right after its data input. Multiple bytes up to maximum 256 bytes are temporarily saved to the data register. After the command input is finished and rising edge of CS, start writing operation from this data register to the nonvolatile memory. 1. Address counter control In case of memory access by WRITE and READ commands, after the end of op-code and address input, it is possible to keep on accessing (= reading or writing) with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles while CS is low level. However, for the WRITE command, continuous writing is restricted by the limit of buffer size in the data register. When it reaches the most significant address, it rolls over to the starting address, and this automatic address increment will be continued by the address counter control. Over write protection to the nonvolatile memory is enabled by BP0 and BP1 bits in status register. When the memory address exceed it from write protected block to unprotected block by address counter control, write to the unprotected block only. Similarly, when memory address exceed it from unprotected block to protected block, does not write to the protected block. bit number 654321 Start address Start address+1 Start address+2 Most significant address-5 Most significant address-4 Most significant address-3 Most significant address-2 Most significant address-1 Most significant address Address MSB LSB
- WIP polling After the last writing data was input, writing to the nonvolatile memory needs tWC waiting time from the rising edge of CS. This tWC time becomes larger than a minimum clock cycle. Production variation and operating condition are considered, and this maximum t WC value is defined. In the usual operation, this t WC time is shorter than the maximum value. Therefore, MB85AS12MT supports WIP polling to improve memory access by optimizing the waiting time. After starting the data writing to nonvolatile memory, MB85AS12MT sets “1” to a volatile register related to the WIP bit in status register. After finished the writing operation, reset this WIP bit from “1” to “0”. Although the usual commands are not executable during this writing process, only the RDSR command is acceptable. RDSR command outputs the value of status register to SO. It is possible to confirm if the internal writing operation to nonvolatile memory is finished or not, by checking the corresponding bit to WIP in output data from SO. RDSR command also outputs the BP1 and BP0 of status register to SO. In the polling after WRSR command, MB85AS12MT outputs the BP1 and BP0 data which is set before the writing to nonvolatile memory is completed. On the other hand for WEL and WIP, MB85AS12MT outputs (WEL,WIP)=2'b11 when the writing to nonvolatile memory is not completed. When it is competed, outputs (WEL,WIP)=2'b00. If continuously sending clocks to SCK during CS = low, it is also possible to keep on outputting from the most significant address to the least significant address (WIP bit) in status register in unit of 8 cycles since 17th clock. In case the WIP polling is applied, WIP and WEL bits in status register output to SO by RDSR command are updated regularly. Figure shows the example of RDSR command input with continuously sending clocks over 17 during CS = low, before the writing process of WRSR command is finished. CS SCK SI X XXX BP1 BP0 XX SO busy wip wel WRSR RDSR X X BP1XX BP0 WEL WIPX X BP1XX BP0 WEL WIP (Write process situation) (Internal volatile register for WIP) (Internal volatile register for WEL)
14 DS501-00071-1v1-E
BLOCK PROTECT Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register. WRITING PROTECT Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, as shown in the table. . BP1 BP0 Protected Block 0 0 None 0 1 120000 H to 17FFFFH (upper 1/4) 1 0 0C0000 H to 17FFFFH (upper 1/2) 1 1 000000 H to 17FFFFH (all) WEL Protected Blocks Unprotected Blocks Status Register
0 Protected Protected Protected
1 Protected Unprotected Unprotected
ABSOLUTE MAXIMUM RATINGS *:These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. RECOMMENDED OPERATING CONDITIONS *1: These parameters are based on the condition that VSS is 0 V. *2: Ambient temperature when only this device is working. Please consider it to be the almost same as the package surface temperature. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Parameter Symbol Rating Unit Min Max Power supply voltage* VDD 0.5 4.0 V Input voltage* VIN 0.5 V DD 0.5 ( 4.0) V Output voltage* VOUT 0.5 V DD 0.5 ( 4.0) V Operation ambient temperature T A 40 85 C Storage temperature Tstg 55 125 C Parameter Symbol Value Unit Min Typ Max Power supply voltage*1 VDD 1.6 3.6 V Operation ambient temperature*2 TA 40 85 C
16 DS501-00071-1v1-E
ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) Parameter Symbol Condition Value Unit Min Typ Max Input leakage current |I LI| CS , SCK 0 V to VDD 1 A Output leakage current |I LO| SI/SO 0 V to V DD 1 A Operating power supply current (Read) IDDR (60) SCK = 5 MHz, TA=0 C to 60 C, 1.6V VDD 2.0V 0.15 0.3 mA IDDR (85) SCK = 10 MHz, TA= 40 C to 85 C, 1.6V VDD 3.6V 0.7 Operating power supply current (Write) IDDW (60) SCK = tWC, TA=0 C to 60 C, 1.6V VDD 2.0V 1.5 mA IDDW (85) SCK = tWC, TA= 40 C to 85 C, 1.6V VDD 3.6V 2.5 Standby current ISB SCK SI CS VDD 65 500 A Sleep current IZZ CS VDD All inputs VSS or VDD VDD=3.6V, TA=85 C 6 8 A CS VDD All inputs VSS or VDD VDD=1.45V, TA=60 C 6 A Input high voltage V IH VDD 1.6 V to 3.6 V V DD 0.7 VDD 0.5 V Input low voltage VIL VDD 1.6 V to 3.6 V 0.5 VDD 0.3 V Output high voltage V OH IOH 1.5 mA @VDD 1.8 V IOH 1.2 mA @VDD < 1.8 V VDD 0.8 V Output low voltage V OL IOL 1.5 mA @VDD 1.8 V IOL 1.2 mA @VDD < 1.8 V VDD 0.2 V
- AC Characteristics AC Test Condition Power supply voltage : 1.6 V to 3.6 V Operation ambient temperature : 40 C to 85 C Input voltage magnitude : V DD 0.7 VIH VDD 0 VIL VDD 0.3 Input rising time : 5 ns Input falling time : 5 ns Input judge level : VDD/2 Output judge level : VDD/2 Parameter Symbol Value Unit Condition Min Typ Max SCK clock frequency f CK 0 10 MHz Clock high time tCH 40 ns Clock low time tCL 40 ns Chip select set up time tCSUH 30 ns CS rising to SCK rising tCSUL 30 CS falling to SCK rising Chip select hold time tCSHH 30 ns SCK rising to CS falling tCSHL 30 SCK rising to CS rising tCSH 30 SCK falling to CS rising Output disable time tOD 30 ns Output active time tOLZ 0 ns Output data valid time t ODV 35 ns Output hold time tOH 0 ns Deselect time tD 100 ns Data rising time tR 50 ns Data falling time tF 50 ns Data set up time tSU 20 ns Data hold time tH 20 ns Write cycle time tWC 5000 10000 s @100% data turn over Recovery time from SLEEP mode tREC 400 1000 s CS pulse width at SLEEP mode exit tCSWL 100 ns
18 DS501-00071-1v1-E
AC Load Equivalent Circuit 3. Pin Capacitance Parameter Symbol Condition Value Unit Min Max Output capacitance CIO VDD VIN VOUT 0 V, f 1 MHz, TA +25 C 6 pF Input capacitance CI 3 pF 30 pF Output VDD 1.2 kΩ 0.95 kΩ
TIMING DIAGRAM Serial Data Timing tCSUL CS SCK tCSHH tCSHL tCSH Mode0 High-Z tCH tCL tCSUH SI/SO tODV tOH tD tSU tH tOD tCSULCS SCK tCSHH tCSHL tCSH High-Z tCH tCSUH SI/SO tODVtSU tH 㼠㻻㻰 tDMode3 tCL tOLZ tOLZ tOH High-Z (Output)(Input) High-Z (Output)(Input)
20 DS501-00071-1v1-E
POWER ON/OFF SEQUENCE If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed. ReRAM CHARACTERISTICS *: 4 bytes are selected by A1 to A0. Parameter Symbol Value UnitMin Max CS level hold time at power OFF tpd 10 ms CS level hold time at power ON tpu 1 ms Power supply rising time tr 50 s/V Power supply falling time tf 100 s/V Parameter Value Unit RemarksMin Max Write Endurance 5 105 Times/4bytes* Operation Ambient Temperature T A 85 C Data Retention 10 Years Operation Ambient Temperature T A 85 C Data register size 256 byte VSS CS >VDD × 0.7V tpd tputrtf VIL (Max) 1.0 V VIH (Min) VDD (Min) VDD CS : don't care CS >VDD × 0.7VCS CS VSS VIL (Max) 1.0 V V IH (Min) VDD (Min) VDD * : CS (Max) < VDD 0.5 V
ESD AND LATCH-UP MB85AS12MT REFLOW CONDITIONS AND FLOOR LIFE [ JEDEC MSL ] : Moisture Sensitivity Level 3 (IPC/JEDEC J-STD-020E) CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS. Test DUT Value ESD HBM (Human Body Model) JESD22-A114 compliant MB85AS12MT |2000 V| ESD CDM (Charged Device Model) JESD22-C101 compliant |500 V| Latch-Up (I-test) JESD78 compliant |100 mA|
22 DS501-00071-1v1-E
ORDERING INFORMATION Part number Package Shipping form Minimum shipping quantity MB85AS12MTPW-GAERE1 11-pin WLP Type-A Embossed Carrier Tape 10,000
PACKAGE DIMENSION 11-pin WLP Bump pitch 0.5 mm Package width package length 2.067 mm 2.877 mm Bump shape Soldering ball Mounting height 0.385 mm MB85AS12MTPW-GAERE1
24 DS501-00071-1v1-E
MARKING (11-pin WLP) 11-pin WLP Type A AS12T : Product name E1 : Fixed code 2200 : Year and Week code C00 : C (Fixed code)+00 (Trace code) AS 1 T E1 2 200 C00
PACKING FIGURE 1. Emboss carrier tape and package direction of storage 2. Reel Package Index mark Direction of unreeling Unit: mm Direction of unreeling Emboss carrier tape
EMBOSS CARRIER TAPE DRAWING Unit: mm Dimensions of Emboss carrier tape W A0 B0 K0 T P0 P1 P2 D0 E1 F
Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan https://ramxeed.com/ All Rights Reserved. RAMXEED LIMITED, its subsidiaries and affiliates (collectively, "RAMXEED ") reserves the right to make changes to the infor- mation contained in this document without notice. Please contact your RAMXEED sales representatives before order of RAMXEED device. Information contained in this document, such as descriptions of function and application circuit examples is presented solely for reference to examples of operations and uses of RAMXEED device. RAMXEED disclaims any and all warranties of any kind, wheth- er express or implied, related to such information, including, without limitation, quality, accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the RAMXEED device based on such informa- tion, you must assume any responsibility or liability arising out of or in connection with such information or any use thereof. RAMX- EED assumes no responsibility or liability for any damages whatsoever arising out of or in connection with such information or any use thereof. Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or any other intellectual property rights of RAMXEED or any third party by license or otherwise, express or implied. RAMXEED assumes no responsibility or liability for any infringement of any intellectual property rights or other rights of third parties resulting from or in connection with the information contained herein or use thereof. The products described in this document are designed, developed and manufactured as contemplated for general use including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater and artificial satellite). RAMXEED shall not be liable for you and/or any third party for any claims or damages arising out of or in connection with above-mentioned uses of the products. Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and technical information described herein. All company names, brand names and trademarks herein are property of their respective owners.