MACH215-12

MACH215-12 LATTICE | Alldatasheet

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Publication# 16751 Rev. E Amendment /0 Issue Date: May 1995 MACH215-12/15/20 High-Density EE CMOS Programmable Logic FINAL COM’L: -12/15/20 IND: -14/18/24 DISTINCTIVE CHARACTERISTICS ■ 44 Pins ■ 32 Output Macrocells ■ 32 Input Macrocells ■ Product terms for: — Individual flip-flop clock — Individual asynchronous reset, preset — Individual output enable ■ 12 ns t PD Commercial 14.5 ns tPD Industrial ■ 67 MHz fCNT ■ 38 Inputs with pull-up resistors ■ 32 Outputs ■ 64 Flip-flops ■ For asynchronous and synchronous

applications

■ 4 “PAL22RA8” blocks with buried macrocells ■ Pin-compatible with MACH110, MACH111, MACH210, and MACH211 GENERAL DESCRIPTION The MACH215 is a member of the high-performance EE CMOS MACH device family. This device has approximately three times the capability of the popular PAL20RA10 without loss of speed. This device is designed for use in asynchronous as well as synchro- nous applications. The MACH215 consists of four PAL blocks intercon- nected by a programmable switch matrix. The four PAL blocks are essentially “PAL22RA8” structures complete with product-term arrays and programmable macro- cells, individual register control product terms, and input registers. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH215 has two kinds of macrocell: output and input. The MACH215 output macrocell provides regis- tered, latched, or combinatorial outputs with program- mable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. Each macrocell has its own dedicated clock, asynchronous reset, and asynchronous preset control. The polarity of the clock signal is programmable. All output macrocells can be connected to an I/O cell. The MACH215 has dedicated input macrocells which provide input registers or latches for synchronizing input signals and reducing setup time requirements. Lattice Semiconductor

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I/O0–I/O7 Input Macrocells I0–I1, I3–I4 I/O16–I/O23 CLK 0/I2I/O24–I/O31 16751E-1 8 8 8 I/O Cells I/O8–I/O15 8 88 I/O Cells 8 88 8 I/O Cells 88 8 Output Macrocells Input Macrocells 44x64 AND Logic Array and Logic Allocator 44x64 AND Logic Array and Logic Allocator 44x64 AND Logic Array and Logic Allocator CLK 1/I5 OE OE OE CLK CLK CLK CLK OE

18 28 27 26 25 24 23 22 21 19 20 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage Note: Pin-compatible with MACH110, MACH111, MACH210, and MACH211. 16751E-2

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ORDERING INFORMATION

Programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: OPERATING CONDITIONS C = Commercial (0 °C to +70°C) FAMILY TYPE MACH = Macro Array CMOS High-Speed SPEED -12 = 12 ns t PD -15 = 15 ns tPD -20 = 20 ns tPD MACH215-12 MACH215-15 MACH215-20 MACH -12 J C Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. Valid Combinations OPTIONAL PROCESSING Blank = Standard Processing 215 DEVICE NUMBER 215 = 32 Asynchronous Output Macrocells, 44 Pins PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) JC

5MACH215-14/18/24 (Ind) Programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: OPERATING CONDITIONS I = Industrial (–40 °C to +85°C) FAMILY TYPE MACH = Macro Array CMOS High-Speed SPEED -14 = 14.5 ns t PD -18 = 18 ns tPD -24 = 24 ns tPD MACH215-14 MACH215-18 MACH215-24 MACH -14 J I Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. Valid Combinations OPTIONAL PROCESSING Blank = Standard Processing 215 DEVICE NUMBER 215 = 32 Asynchronous Output Macrocells, 44 Pins PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) JI

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within the device can operate independently. when fitting a design into the device. generating macrocell control signals. Figure 1 for cluster and macrocell numbers. Table 1. Logic Allocation configured as registered or latched inputs. Table 2. Programmable polarity and the T-type flip-flop Table 2. Register/Latch Operation *Polarity of CLK/LE can be programmed.

macrocell configurations are shown in Figure 4. a signal acts as both clock and input to the same device. Table 3. Asynchronous Reset/Preset Operation two global clock/latch-enable pins. used, and the feedback from the I/O pin is used directly. the output buffer or the output macrocell.

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Figure 1. MACH215 PAL Block

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Figure 4. Output Macrocell Configurations

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DC Input Voltage –0.5 V to V DC Output or I/O Pin Voltage –0.5 V to V Latchup Current Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (T A) Operating Supply Voltage (VCC ) with Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 24 mA, VCC = Min 0.5 V VIN = VIH or VIL (Note 1) VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 2) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 2) IIH Input HIGH Current V IN = 5.25 V, VCC = Max (Note 3) 10 µA IIL Input LOW Current V IN = 0 V, VCC = Max (Note 3) –100 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 3) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –100 µA Current LOW V IN = VIH or VIL (Note 3) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) –30 –160 mA ICC Supply Current (Typical) V CC = 5 V, TA = 25°C, f = 25 MHz 95 mA (Note 5) Notes: 1. Total IOL for one PAL block should not exceed 128 mA. 2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH ). 4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.

13MACH215-12/15/20 (Com’l) CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 3 12 3 15 3 20 ns D-type 5 6 8 ns T-type 6 7 9 ns tHA Register Data Hold Time Using Product Term Clock 5 6 8 ns tCOA Product Term Clock to Output (Note 3) 4 14 4 18 4 22 ns tWLA LOW 8 9 12 ns tWHA HIGH 8 9 12 ns D-type 52.6 41.7 33.3 MHz T-type 50 40 32.2 MHz D-type 58.8 45.5 35.7 MHz T-type 55.6 43.5 34.5 MHz 62.5 55.6 41.7 MHz D-type 7 10 13 ns T-type 8 11 14 ns t HS Register Data Hold Time Using Global Clock 0 0 0 ns tCOS Global Clock to Output (Note 3) 2 8 2 10 2 12 ns tWLS LOW 6 6 8 ns tWHS HIGH 6 6 8 ns D-type 66.7 50 40 MHz T-type 62.5 47.6 38.5 MHz fMAXS D-type 83.3 66.6 50 MHz T-type 76.9 62.5 47.6 MHz 83.3 83.3 62.5 MHz tSLA 568 n s tHLA Latch Data Hold Time Using Product Term Clock 5 6 8 ns tGOA Product Term Gate to Output (Note 3) 16 19 22 ns tGWA Product Term Gate Width LOW (for LOW transparent) 8 9 12 ns or HIGH (for HIGH transparent) t SLS Setup Time from Input, I/O, or Feedback to Global Gate 7 10 13 ns tHLS Latch Data Hold Time Using Global Gate 0 0 0 ns tGOS Gate to Output (Note 3) 10 11 12 ns tGWS Global Gate Width LOW (for LOW transparent) 6 6 8 ns or HIGH (for HIGH transparent) Maximum Frequency Using Product Term Clock (Note 1) External Feedback 1/(t SA + tCOA ) Internal Feedback (fCNTA ) No Feedback 1/(tWLA + tWHA ) Global Clock Width -12 Maximum Frequency Using Global Clock (Note 1) Setup Time from Input, I/O, or Feedback to Product Term Clock External Feedback 1/(tSS + tCOS ) Internal Feedback (fCNTS ) No Feedback 1/(tWLS + tWHS ) -15 -20 tSS tSA Setup Time from Input, I/O, or Feedback to Global Clock Setup Time from Input, I/O, or Feedback to Product Term Gate fMAXA Product Term, Clock Width

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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 14 17 22 ns t SIR Input Register Setup Time 2 2 2 ns tHIR Input Register Hold Time 2 2.5 3 ns tICO Input Register Clock to Combinatorial Output 15 18 23 ns tICS Input Register Clock to Output Register Setup D-type 12 15 20 ns T-type 13 16 21 ns tWICL LOW 6 6 8 ns tWICH HIGH 6 6 8 ns fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH ) 83.3 83.3 62.5 MHz tSIL Input Latch Setup Time 2 2 2 ns tHIL Input Latch Hold Time 2 2.5 3 ns tIGO Input Latch Gate to Combinatorial Output 17 20 25 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 19 22 27 ns Setup Time from Input, I/O, or Feedback Through t SLLA Transparent Input Latch to Product Term Output 7 8 10 ns Latch Gate t IGSA Input Latch Gate to Output Latch Setup Using 7 8 10 ns Product Term Output Latch Gate t SLLS Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Global Output Latch Gate 9 12 15 ns tIGSS Input Latch Gate to Output Latch Setup Using Global 13 16 21 ns Output Latch Gate t WIGL Input Latch Gate Width LOW 6 6 8 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 16 19 24 ns t AR Asynchronous Reset to Registered or Latched Output 16 20 25 ns tARW Asynchronous Reset Width (Note 1) 12 15 20 ns tARR Asynchronous Reset Recovery Time (Note 1) 8 10 15 ns tAP Asynchronous Preset to Registered or Latched Output 16 20 25 ns tAPW Asynchronous Preset Width (Note 1) 12 15 20 ns tAPR Asynchronous Preset Recovery Time (Note 1) 8 10 15 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 2 12 2 15 2 20 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 2 12 2 15 2 20 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. Switching waveforms illustrate true clocks only. Switching waveforms can be used to illustrate both synchronous and asynchronous clock timing. For example, tSS is the tS parameter for synchronous clocks and tSA is the tS parameter for asynchronous clocks. 3. Parameters measured with 16 outputs switching. -12 -15 -20 Input Register Clock Width

15MACH215-14/18/24 (Ind) ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Input Voltage –0.5 V to V CC DC Output or I/O Pin Voltage –0.5 V to V CC Latchup Current Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. INDUSTRIAL OPERATING RANGES Ambient Temperature (TA) Supply Voltage (VCC) with Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 24 mA, VCC = Min 0.5 V VIN = VIH or VIL (Note 1) VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 2) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 2) IIH Input HIGH Leakage Current V IN = 5.25 V, VCC = Max (Note 3) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 3) –100 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 3) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –100 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 4) –30 –160 mA ICC Supply Current (Typical) V CC = 5 V, TA = 25°C, f = 25 MHz (Note 5) 95 mA Notes: 1. Total IOL for one PAL block should not exceed 128 mA. 2. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.

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CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output 14.5 18 24 ns (Note 3) D-type 6 7.5 10 ns T-type 7.5 8.5 11 ns tHA Register Data Hold Time Using Product Term Clock 6 7.5 10 ns tCOA Product Term Clock to Output (Note 3) 17 22 26.5 ns tWLA LOW 10 11 15 ns tWHA HIGH 10 11 15 ns D-type 42 33 26.5 MHz T-type 40 32 25.5 MHz D-type 47 36 28.5 MHz T-type 44 34.5 27.5 MHz 50 44.5 33 MHz D-type 8.5 12 16 ns T-type 10 13.5 17 ns tHS Register Data Hold Time Using Global Clock 0 0 0 ns tCOS Global Clock to Output (Note 3) 10 12 14.5 ns tWLS LOW 7.5 7.5 10 ns tWHS HIGH 7.5 7.5 10 ns D-type 53 40 32 MHz T-type 50 38 30.5 MHz fMAXS D-type 66.5 53 40 MHz T-type 61.5 50 38 MHz 66.5 66.5 50 MHz tSLA 6 7.5 10 ns tHLA Latch Data Hold Time Using Product Term Clock 6 7.5 10 ns tGOA Product Term Gate to Output (Note 3) 19.5 23 26.5 ns tGWA Product Term Gate Width LOW (for LOW transparent) 10 11 14.5 ns or HIGH (for HIGH transparent) tSLS Setup Time from Input, I/O, or Feedback to Global Gate 8.5 12 16 ns tHLS Latch Data Hold Time Using Global Gate 0 0 0 ns tGOS Gate to Output (Note 3) 12 13.5 14.5 ns tGWS Global Gate Width LOW (for LOW transparent) 7.5 7.5 10 ns or HIGH (for HIGH transparent) Maximum Frequency Using Product Term Clock (Note 1) External Feedback 1/(tSA + tCOA) Internal Feedback (fCNTA) No Feedback 1/(tWLA + tWHA) Global Clock Width -14 Maximum Frequency Using Global Clock (Note 1) Setup Time from Input, I/O, or Feedback to Product Term Clock External Feedback 1/(tSS + tCOS) Internal Feedback (fCNTS) No Feedback 1/(tWLS + tWHS) -18 -24 tSS tSA Setup Time from Input, I/O, or Feedback to Global Clock Setup Time from Input, I/O, or Feedback to Product Term Gate fMAXS Product Term, Clock Width

17MACH215-14/18/24 (Ind) SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tPDL Input, I/O, or Feedback to Output Through 17 20.5 26.5 ns Transparent Input or Output Latch tSIR Input Register Setup Time 2.4 2.4 2.4 ns tHIR Input Register Hold Time 3 3.5 4 ns tICO Input Register Clock to Combinatorial Output 18 22 28 ns tICS Input Register Clock to Output Register Setup D-type 14.5 18 24 ns T-type 16 19.5 25.5 ns tWICL LOW 7.5 7.5 10 ns tWICH HIGH 7.5 7.5 10 ns fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 66.5 66.5 50 MHz tSIL Input Latch Setup Time 2.5 2.5 2.5 ns tHIL Input Latch Hold Time 3 3.5 4 ns tIGO Input Latch Gate to Combinatorial Output 20.5 24 30 ns tIGOL Input Latch Gate to Output Through Transparent 23 26.5 32.5 ns Output Latch Setup Time from Input, I/O, or Feedback Through tSLLA Transparent Input Latch to Product Term Output 8.5 10 12 ns Latch Gate tIGSA Input Latch Gate to Output Latch Setup Using 8.5 10 12 ns Product Term Output Latch Gate tSLLS Setup Time from Input, I/O, or Feedback Through 11 14.5 18 ns Transparent Input Latch to Global Output Latch Gate tIGSS Input Latch Gate to Output Latch Setup Using Global 16 19.5 25.5 ns Output Latch Gate tWIGL Input Latch Gate Width LOW 7.5 7.5 10 ns tPDLL Input, I/O, or Feedback to Output Through Transparent 19.5 23 29 ns Input and Output Latches tAR Asynchronous Reset to Registered or Latched Output 19.5 24 30 ns tARW Asynchronous Reset Width (Note 1) 14.5 18 24 ns tARR Asynchronous Reset Recovery Time (Note 1) 10 12 18 ns tAP Asynchronous Preset to Registered or Latched Output 19.5 24 30 ns tAPW Asynchronous Preset Width (Note 1) 14.5 18 24 ns tAPR Asynchronous Preset Recovery Time (Note 1) 10 12 18 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 14.5 18 24 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 14.5 18 24 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. Switching waveforms illustrate true clocks only. Switching waveforms can be used to illustrate both synchronous and asynchronous clock timing. For example, tSS is the tS parameter for synchronous clocks and tSA is the tS parameter for asynchronous clocks. 3. Parameters measured with 16 outputs switching. -14 -18 -24 Input Register Clock Width

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TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS VCC = 5.0 V, TA = 25°C Input –40 –60 –80 –2 –1 123 Output, HIGH II (mA) VI (V) –20 IOH (mA) VOH (V) –50 –75 –100 –3 –2 –1 123 –25 –125 –150 –100 16751E-10Output, LOW .4 .6 1.0.8 –20 –40 –60 –80 I OL (mA) VOL (V) 16751E-11 16751E-12

TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C MACH215 150 125 100 0 1 02 03 04 0 5 06 07 08 09 0 ICC (mA) Frequency (MHz) The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. 16751E-13

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TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Parameter Description PLCC Units θ jc Thermal impedance, junction to case 15 °C/W θja Thermal impedance, junction to ambient 40 °C/W θjma Thermal impedance, junction to 200 lfpm air 36 °C/W 400 lfpm air 33 °C/W 600 lfpm air 31 °C/W 800 lfpm air 29 °C/W Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. Typ ambient with air flow

Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. tPD Input, I/O, or Feedback Combinatorial Output VT VT Combinatorial Output VT Input, I/O, or Feed- back Registered Output Registered Output tS tCO VT tH VTClock tWH Clock Clock Width tWL VT Combinatorial Output Registered Input (MACH 2 and 4) tSIR tICO VT tHIR VT Input Register Clock Registered Input Latched Output (MACH 2, 3, and 4) Gate Gate Width (MACH 2, 3, and 4) tGWS VT VT VT VT tICS Input Register to Output Register Setup (MACH 2 and 4) Output Register Clock Input Register Clock Registered Input tPDL Input, I/O, or Feedback Latched Out Gate VT tHLtSL tGO VT VT 16751E-14 16751E-15 16751E-16 16751E-17 16751E-18 16751E-19 16751E-20

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Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. Latched Input (MACH 2 and 4) Latched Input and Output (MACH 2, 3, and 4) Latched In Output Latch Gate Latched Out tSLL Combinatorial Output Gate tHILtSIL tIGO Latched In tPDLL tIGOL tIGS Input Latch Gate VT VT VT VT VT VT 16751E-21 16751E-22

Input Register Clock Width (MACH 2 and 4) VT tWICL VT VT tARW VT tAR Asynchronous Reset Input, I/O, or Feedback Registered Output Clock tARR Asynchronous Preset Registered Output Clock VT VTOutputs Output Disable/Enable tER tEA VOH - 0.5V VOL + 0.5V Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. Input, I/O, or Feedback VT VT Input, I/O, or Feedback tAPW VT tAP tAPR Input Latch Gate Input Latch Gate Width (MACH 2 and 4) tWIGL VT 16751E-23 16751E-24 16751E-25 16751E-26 16751E-27

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KEY TO SWITCHING WAVEFORMS KS000010-PAL Must be Steady May Change from H to L May Change from L to H Does Not Apply Don’t Care, Any Change Permitted Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is High- Impedance “Off” State WAVEFORM INPUTS OUTPUTS SWITCHING TEST CIRCUIT Measured Specification S 1 C L R 1 R 2 Output Value tPD , tCO Closed 1.5 V tEA Z → H: Open 35 pF 1.5 V Z → L: Closed 300 Ω 390 Ω tER H → Z: Open 5 pF H → Z: VOH – 0.5 V L → Z: Closed L → Z: VOL + 0.5 V Commercial 16751E-28 C L Output R 1 R 2 Test Point 5 V *Switching several outputs simultaneously should be avoided for accurate measurement.

The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexi- bility inherent in programmable logic devices offers a choice of clocked flip-flop designs, f MAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the in- put setup time for the external signals (t S + tCO ). The re- ciprocal, fMAX , is the maximum frequency with external feedback or in conjunction with an equivalent speed de- vice. This f MAX is designated “fMAX external.” The second type of design is a single-chip state ma- chine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop out- puts. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the inter- nal feedback and logic to the flip-flop inputs. This f MAX is designated “fMAX internal”. A simple internal counter is a good example of this type of design; therefore, this pa- rameter is sometimes called “f CNT.” The third type of design is a simple data path applica- tion. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (t S + tH ). However, a lower limit for the period of each fMAX type is the mini- mum clock period (tWH + tWL ). Usually, this minimum clock period determines the period for the third fMAX , des- ignated “fMAX no feedback.” For devices with input registers, one additional fMAX pa- rameter is specified: fMAXIR . Because this involves no feedback, it is calculated the same way as fMAX no feed- back. The minimum period will be limited either by the sum of the setup and hold times (t SIR + tHIR) or the sum of the clock widths (tWICL + tWICH ). The clock widths are nor- mally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH ). Note that if both input and output reg- isters are use in the same path, the overall frequency will be limited by t ICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is meas- ured directly. tHIRtSIR LOGIC REGISTER tt CLK (SECOND CHIP) SC O tS fMAX External; 1/(tS + tCO ) LOGIC REGISTER CLK fMAX Internal (fCNT ) LOGIC REGISTER t CLK S fMAX No Feedback; 1/(tS + tH ) or 1/(tWH + tWL ) 16751E-29 LOGICREGISTER CLK fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH )

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The MACH families are manufactured using our advanced Electrically Erasable process. This technol- ogy uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics Parameter Symbol Parameter Description Min Units Test Conditions

10 Years Max Storage

20 Years Max Operating

N Max Reprogramming Cycles 100 Cycles Normal Programming Conditions tDR Min Pattern Data Retention Time

INPUT/OUTPUT EQUIVALENT SCHEMATICS Input I/O Preload Circuitry ESD Protection Feedback Input VCC VCC 1 kΩ 100 kΩ VCC VCC 100 kΩ 1 kΩ 16751E-30

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The MACH devices have been designed with the capa- bility to reset during system power-up. Following power- up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing dia- gram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways V CC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The V CC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Descriptions Max Unit t PR Power-Up Reset Time 10 µs tS Input or Feedback Setup Time tWL Clock Width LOW See Switching Characteristics tPR tWL tS 4 V VCC Power Registered Output Clock 16751E-31 Power-Up Reset Waveform

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PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches) TOP VIEW SEATING PLANE .685 .695 .650 .656 Pin 1 I.D. .685 .695 .650 .656 .026 .032 .050 REF .042 .056 .062 .083 .013 .021 .590 .630 .500 REF .009 .015 .165 .180 .090 .120 16-038-SQ PL 044 DA78 6-28-94 ae SIDE VIEW *For reference only. BSC is an ANSI standard for Basic Space Centering.