Logic IC

MACH211SP-7VC

Lattice Semiconductor

High-Performance EE CMOS Programmable Logic

Manufacturer: Lattice Semiconductor

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Publication# 14051 Rev: K Amendment/0 Issue Date: November 1998 MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic

FEATURES

N High-performance electrically-erasable CMOS PLD families N 32 to 128 macrocells N 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages N SpeedLocking™ – guaranteed ﬁxed timing up to 16 product terms N Commercial 5/5.5/6/7.5/10/12/15-ns t PD and Industrial 7.5/10/12/14/18-ns t PD N Conﬁgurable macrocells — Programmable polarity — Registered or combinatorial outputs — Internal and I/O feedback paths — D-type or T-type ﬂip-ﬂops — Output Enables — Choice of clocks for each ﬂip-ﬂop — Input registers for MACH 2 family N JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available N Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns N Safe for mixed supply voltage system designs N Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs N Programmable power-down mode results in power savings of up to 75% N Supported by Vantis DesignDirect™ software for rapid logic development — Supports HDL design methodologies with results optimized for Vantis — Flexibility to adapt to user requirements — Software partnerships that ensure customer success N Lattice/Vantis and third-party hardware programming support — Lattice/VantisPRO™ (formerly known as MACHPRO ) software for in-system programmability support on PCs and Automated Test Equipment — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General

2 MACH 1 & 2 Families

Values in parentheses ( ) are for the SP version.

users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.

C = Commercial, I = Industrial
-5 speed grade for MACH111 (SP) = 5.0 ns t
-5 speed grade for MACH131(SP) = 5.5 ns t

Table 1. MACH 1 and 2 Family Device Features Table 2. MACH 1 and 2 Family Speed Grades

The MACH110, MACH120, MACH130, MACH210, MACHLV210, MACH215, MACH220 and MACH230 are not listed above and

your local Lattice/Vantis sales ofﬁce or visit our Web site at www.vantis.com for more information. devices. This system is supported under Windows ’95, ’98 and NT as well as Sun Solaris and HPUX. compliant VHDL and SDF simulation netlists for design veriﬁcation. Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided. Table 3. MACH 1 and 2 Family Package and I/O Options

4 MACH 1 & 2 Families

in a single device instead of using multiple devices. communicate with each other with guaranteed ﬁxed timing (SpeedLocking). Figure 1. Overall Architecture of MACH 1 & 2 Devices

There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.

preset product term. This allows the ﬂip-ﬂops within a single PAL block to be initialized as a bank. There are also output enable product terms that provide tri-state control for the I/O cells. provided in both true and complement forms for efﬁcient logic implementation. the appropriate number of product terms to generate the function. wasted, product terms left over. at the ends of the block have fewer product terms available (Tables 5, 6, 7, 8). Table 4. PAL Block Inputs

6 MACH 1 & 2 Families

Table 5. Logic Allocation for MACH111(SP) Table 6. Logic Allocation for MACH131(SP) Figure 2. Product Term Clusters and the Logic Allocator

doubles the number of macrocells available without increasing the pin count. a T-type or a D-type ﬂip-ﬂop. Register and latch functionality is deﬁned in Table 9. by the software when it ﬁts the design into the device. Table 7. Logic Allocation for MACH211(SP) and MACH231(SP) Table 8. Logic Allocation for MACH221(SP) Table 9. Register/Latch Operation

8 MACH 1 & 2 Families

and to the I/O cell. The feedback is always available regardless of the conﬁguration of the I/O cell. inputs if not needed as outputs. The basic output macrocell conﬁgurations are shown in Figure 4. conﬁgurations are shown in Figure 6. Figure 3. Output Macrocell

Latch option available on MACH 2 devices only.

Figure 4. Output Macrocell Conﬁgurations

10 MACH 1 & 2 Families

Figure 5. Buried Macrocell (MACH 2 only) Figure 6. Buried Macrocell Conﬁgurations (MACH 2 only)

The ﬂip-ﬂops in either macrocell type can be clocked by one of several clock pins (Table 10). acts as both clock and input to the same device. product terms provided are common to a bank of I/O cells. Table 10. Macrocell Clocks Table 11. Asynchronous Reset/Preset Operation

01 X 1

10 X 0

11 X 0

12 MACH 1 & 2 Families

give designers easy access to the performance required in today’s designs. Figure 7. I/O Cell

5 PT 10 PT 15 PT

Patented Architecture
Path Independent
Logic/Routing Independent
Guaranteed Fixed Timing
Up to 16 Product Terms per Output
Variable
Path Dependent
Logic/Routing Dependent Delays
Unpredictable
4-5 Product Terms before Delays Non-MACHMACH 1 & 2 SpeedLocking

Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices

MACH 1 & 2 Families 13 JTAG IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of signiﬁcant beneﬁts including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-ﬁeld modiﬁcations. All MACHxxxSP devices provide in-system programming (ISP) capability through their JTAG ports. This capability has been implemented in a manner that insures that the JTAG port remains compliant to the IEEE 1149.1 standard. By using JTAG as the communication interface through which ISP is achieved, customers beneﬁt from a standard, well-deﬁned interface. MACHxxxSP devices can be programmed across the commercial temperature and voltage range. These devices tristate the outputs during programming. Lattice/Vantis provides its free PC-based Lattice/VantisPRO software to facilitate in-system programming. Lattice/VantisPRO software takes the JEDEC ﬁle output produced by Vantis’ design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. Lattice/ VantisPRO software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, Lattice/VantisPRO software can output ﬁles in formats understood by common automated test equipment. This equipment can then be used to program MACHxxxSP devices during the testing of a circuit board. For more information about in-system programming, refer to the separate document entitled MACH ISP Manual. BUS-FRIENDLY INPUTS AND I/Os The MACH 1 & 2 inputs and I/Os include two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. For the circuit diagram, please refer to the Input/Output Equivalent Schematics (page 393) in the General Information Section of the Vantis 1999 Data Book. PCI COMPLIANT The MACH 1 & 2 families in -5/-6/-7/-10/-12 speed grades are fully compliant with the PCI Local Bus Speciﬁcation published by the PCI Special Interest Group. The MACH 1 & 2 families’ predictable timing ensures compliance with the PCI AC speciﬁcations independent of the design. POWER-DOWN MODE The MACH 1 & 2 families feature a programmable low-power mode in which individual signal paths can be programmed for low power. These low-power speed paths will be slower than the non-low-power paths. This feature allows speed critical paths to run at maximum frequency while the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. If all of the signals in a PAL block are in low-power mode, then the total power is reduced even further. SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS All MACHxxxSP and most of the MACH 1 & 2 devices are safe for mixed supply voltage system designs. These 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they can accept inputs from other 3.3-V devices. The MACH 1 & 2 families provide easy-to- use mixed-voltage design compatibility. For more information, refer to the Technical Note entitled Mixed Supply Design with MACH 1 & 2 SP Devices. POWER-UP RESET All ﬂip-ﬂops power-up to a logic LOW for predictable system initialization. The actual values of the outputs of the MACH devices will depend on the conﬁguration of the macrocell. To guarantee

14 MACH 1 & 2 Families

initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset delay time has elapsed. SECURITY BIT A security bit is provided on the MACH devices as a deterrent to unauthorized copying of the array conﬁguration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and veriﬁcation are also defeated by the security bit. The bit can only be reset by erasing the entire device.

MACH 1 & 2 Families 15 MACH111(SP) AND MACH131(SP) PAL BLOCK 0 4 8 12 16 20 24 28 40 32 4336 0 4 8 12 16 20 24 28 40 32 4336 I/O Cell I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Switch Matrix Output Enable Output Enable Asynchronous Reset Asynchronous Preset Output Enable Output Enable CLK I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell for MACH111SP for MACH111, MACH131, MACH131SP 47 51 47 51 Logic Allocator C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 C 10 C 11 C 12 C 13 C 14 C 15 M 3 M 6 M 5 M 4 M 2 M 1 M 0 M 9 M 8 M 7 M 10 M 11 M 12 M 13 M 14 M 15 14051K-013

16 MACH 1 & 2 Families

MACH211(SP) PAL BLOCK 0 4 8 12 16 20 24 28 40 32 4336 0 4 8 12 16 20 24 28 40 32 4336 I/O Cell I/O I/O I/O I/O I/O I/O I/O I/O Switch Matrix Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell 47 51 47 51 CLK for MACH211SP for MACH211 Logic Allocator C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 C 10 C 11 C 12 C 13 C 14 C 15 M 3 M 6 M 5 M 4 M 2 M 1 M 0 M 9 M 8 M 7 M 10 M 11 M 12 M 13 M 14 M 15 14051K-015

MACH 1 & 2 Families 17 MACH221(SP) PAL BLOCK Asynchronous Preset 0 4 8 12 16 20 24 28 40 32 4336 0 4 8 12 16 20 24 28 40 32 4336 Switch Matrix Output Enable Output Enable Asynchronous Reset CLK 47 51 47 51 I/OI/O CellOutput Macro Cell Buried Macro Cell I/OI/O Cell Output Macro Cell Buried Macro Cell I/OI/O Cell Output Macro Cell Buried Macro Cell I/OI/O Cell Output Macro Cell Buried Macro Cell I/OI/O Cell Output Macro Cell Buried Macro Cell Buried Macro Cell I/OI/O Cell Output Macro Cell Logic Allocator C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 C 10 C 11 M 3 M 6 M 5 M 4 M 2 M 1 M 0 M 9 M 8 M 7 M 10 M 11 14051K-016

18 MACH 1 & 2 Families

MACH231(SP) PAL BLOCK 0 4 8 12 16 20 24 28 40 32 4336 0 4 8 12 16 20 24 28 40 32 4336 Switch Matrix 47 59 I/O Cell I/O I/O I/O I/O I/O I/O I/O I/O Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell I/O Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Output Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell Buried Macro Cell CLK Logic Allocator C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 C 10 C 11 C 12 C 13 C 14 C 15 M 3 M 6 M 5 M 4 M 2 M 1 M 0 M 9 M 8 M 7 M 10 M 11 M 12 M 13 M 14 M 15 51 55 63 55 59 63 14051K-017

MACH 1 & 2 Families 19 BLOCK DIAGRAM (MACH111, MACH111SP) 52 x 70 AND Logic Array and Logic Allocator I/O0 – I/O15 I/O Cells Macrocells Switch Matrix OE 52 x 70 AND Logic Array and Logic Allocator I/O16 – I/O31 I0 I/O Cells Macrocells OE 1616 Block A Block B 14051K-008MACH111 CLK0 /I1 CLK1 /I2 CLK2/I4 CLK3 /I5 MACH111 CLK0 /I0 CLK1 /I1 MACH111SP

4 MACH111

2 MACH111SP

2 MACH111 Only

20 MACH 1 & 2 Families

BLOCK DIAGRAM (MACH131, MACH131SP) I/O Cells Macrocells I/O48 – I/O63 52 x 70 AND Logic Array and Logic Allocator OE I/O Cells Macrocells I/O16 – I/O31 52 x 70 AND Logic Array and Logic Allocator OE Switch Matrix I/O Cells Macrocells I/O0 – I/O15 I2, I5 52 x 70 AND Logic Array and Logic Allocator CLK0/I0, CLK1/I1 CLK2/I3, CLK3/I4 OE I/O Cells Macrocells I/O32 – I/O47 52 x 70 AND Logic Array and Logic Allocator OE Block A Block B Block D Block C 14051K-009 16 16 16 16

MACH 1 & 2 Families 21 BLOCK DIAGRAM (MACH211, MACH211SP) Switch Matrix I/O Cells Macrocells I/O0–I/O7 Macrocells 52 x 68 AND Logic Array and OE I/O Cells Macrocells I/O8–I/O15 Macrocells 52 x 68 AND Logic Amrray and OE I/O Cells Macrocells I/O24–I/O31 Macrocells 52 x 68 AND Logic Array and Logic Allocator OE I/O Cells Macrocells I/O16–I/O23 Macrocells 52 x 68 AND Logic Array and Logic Allocator OE Block A Block B Block D Block C 2 2 2 2 14051K-010 MACH211 only MACH211 CLK0 /I1 CLK1 /I2 CLK2/I4 CLK3 /I5 MACH211 CLK0 /I0 CLK1 /I1 MACH211SP

4 MACH211

2 MACH211SP

2 MACH211 only

22 MACH 1 & 2 Families

BLOCK DIAGRAM (MACH221, MACH221SP) CLK 0/I0, CLK1/I1 CLK 2/I4, CLK3/I5 I2–I3, I6–I7 I/O Cells Macrocells Macrocells 52 x 52 AND Logic Array and Logic Allocator I/O18 – I/O23 O I/O42 – I/O47 I/O Cells Macrocells Macrocells 52 x 52 AND Logic Array and Logic Allocator I/O0 – I/O5 Macrocells Macrocells 666 I/O Cells Switch Matrix 52 x 52 AND Logic Array and Logic Allocator O O I/O36 – I/O41 I/O Cells Macrocells Macrocells 52 x 52 AND Logic Array and Logic Allocator I/O6 – I/O11 Macrocells Macrocells 666 I/O Cells 52 x 52 AND Logic Array and Logic Allocator O O I/O30 – I/O35 I/O Cells Macrocells Macrocells 52 x 52 AND Logic Array and Logic Allocator I/O12 – I/O17 Macrocells Macrocells 666 I/O Cells 52 x 52 AND Logic Array and Logic Allocator O O I/O24 – I/O29 Macrocells Macrocells 666 I/O Cells 52 x 52 AND Logic Array and Logic Allocator O 2 2 2 222 2 Block H Block G Block F Block E Block DBlock CBlock BBlock A 14051K-011

MACH 1 & 2 Families 23 BLOCK DIAGRAM (MACH231, MACH231SP) CLK 0/I0, CLK1/I1 CLK 2/I3, CLK3/I4 I2, I5 I/O Cells Macrocells Macrocells 64 x 68 AND Logic Array and Logic Allocator I/O24 – I/O31 (Block D) OE I/O56 – /O63 (Block I/O Cells Macrocells Macrocells 64 x 68 AND Logic Array and Logic Allocator I/O0 – I/O7 (Block A) Macrocells Macrocells 888 I/O Cells Switch Matrix 64 x 68 AND Logic Array and Logic Allocator OE OE I/O48 – I/O55 (Block G) I/O Cells Macrocells Macrocells 64 x 68 AND Logic Array and Logic Allocator I/O8 – I/O15 (Block B) Macrocells Macrocells 888 I/O Cells 64 x 68 AND Logic Array and Logic Allocator OE OE I/O40 – I/O47 (Block F) I/O Cells Macrocells Macrocells 64 x 68 AND Logic Array and Logic Allocator I/O16 – I/O23 (Block C) Macrocells Macrocells 888 I/O Cells 64 x 68 AND Logic Array and Logic Allocator OE OE I/O32 – I/O39 (Block E) Macrocells Macrocells 888 I/O Cells 64 x 68 AND Logic Array and Logic Allocator OE 2 2 2 2 2222 14051K-012

24 MACH 1 & 2 Families

DC Output or I/O Pin Voltage . . -0.5 V to VCC +0.5 V Latchup Current (T Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Rat- ings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges deﬁne those limits between which the func- tionality of the device is guaranteed. Industrial (I) Devices Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges deﬁne those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS OVER OPERATING RANGES Notes: 1. This applies to MACH111SP, MACH131SP, and die code “B” or later for MACH211(SP) and MACH231(SP). This does not apply to MACH111, MACH131, MACH221(SP), and die code “A” for MACH211(SP) and MACH231(SP). 2. Total I OL for one PAL block should not exceed 64 mA. 3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included. 4. I/O pin leakage is the worst case of I IL and IOZL (or IIH and IOZH). 5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 6. For commercial temperature range only. Parameter Symbol Parameter Description Test Description Min Typ Max Unit VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V IOH = –300 µA, VCC = Max, VIN = VIH or VIL (Note 1) 3.5 V VOL Output LOW Voltage IOL = 16 mA, VCC = Min, VIN = VIH or VIL (Note 2) 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 3) 2.0 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 3) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, V VCC = Max (Note 4) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 4) –10 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 4) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max, VIN = VIH or VIL (Note 4) –10 µA ISC Output Short-Circuit Current VOUT = 0.5 V VCC = Max (Note 5) –30 –130 (Note 6), –160 mA

MACH 1 & 2 Families 25 MACH111 AND MACH111SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES1 Notes: 1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiﬁed where this parameter may be affected. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. Parameter Symbol Parameter Description UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max tPD Input, I/O, or Feedback to Combinatorial Output 5 7.5 10 12 14 15 18 ns tS Setup Time from Input, I/O, or Feedback to Clock D-type 3.5 5.5 6.5 7 8.5 10 12 ns T-type 4 6.5 7.5 8 10 11 13.5 ns tH Register Data Hold Time 0000000 n s tCO Clock to Output 3.5 5 6 8 10 10 12 ns tWL Clock Width L O W 2 . 5 35666 7 . 5 n s tWH HIGH 2.5 35666 7 . 5 n s fMAX Maximum Frequency External Feedback 1/(tS + tCO) D-type 143 95 80 66.7 54 50 42 MHz T-type 133 87 74 62.5 50 47.6 39 MHz Internal Feedback (fCNT) D-type 182 133 100 76.9 69 66.6 53 MHz T-type 167 125 91 71.4 57 55.5 44 MHz No Feedback 1/(t WL + tWH) 200 167 100 83.3 83.3 83.3 66.7 MHz tAR Asynchronous Reset to Registered Output 7.5 9.5 11 16 19.5 20 24 ns tARW Asynchronous Reset Width (Note 2) 4.5 5 7.5 12 14.5 15 18 ns tARR Asynchronous Reset Recovery Time (Note 2) 4.5 5 7.5 8 10 10 12 ns tAP Asynchronous Preset to Registered Output 7.5 9.5 11 16 19.5 20 24 ns tAPW Asynchronous Preset Width (Note 2) 4.5 5 7.5 12 14.5 15 18 ns tAPR Asynchronous Preset Recovery Time (Note 2) 4.5 5 7.5 8 10 10 12 ns tEA Input, I/O, or Feedback to Output Enable 7.5 9.5 10 12 14.5 15 18 ns tER Input, I/O, or Feedback to Output Disable 7.5 9.5 10 12 14.5 15 18 ns tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 3) 7777777 n s tLPCO tCO Increase for Powered-down Macrocell (Note 3) 3333333 n s tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 10 10 ns

26 MACH 1 & 2 Families

SWITCHING CHARACTERISTICS OVER OPERATING RANGES1 Notes: 1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiﬁed where this parameter may be affected. 3. If a signal is powered down, this parameter must be added to its respective high-speed parameter. Parameter Symbol Parameter Description UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max tPD Input, I/O, or Feedback to Combinatorial Output 5.5 7.5 10 12 14 15 18 ns tS Setup Time from Input, I/O, or Feedback D-type 3.0 5.5 6.5 7 8.5 10 12 ns T-type 3.5 6.5 7.5 8 10 11 13.5 ns tH Hold Time 0000000 n s tCO Clock to Output 4568 1 0 1 0 1 2 n s tWL Clock Width L O W 2 . 5 34666 7 . 5 n s tWH HIGH 2.5 34666 7 . 5 n s fMAX Maximum Frequency External Feedback 1/(tS + tCO) D-type 143 95 80 66.7 54 50 42 MHz T-type 133 87 74 62.5 50 47.6 39 MHz Internal Feedback (fCNT) D-type 182 133 100 76.9 69 66.6 53 MHz T-type 167 125 91 71.4 57 55.5 44 MHz No Feedback 1/(tWL + tWH) 200 167 125 83.3 83.3 83.3 66.7 MHz tAR Asynchronous Reset to Registered Output 8.5 9.5 11 16 19.5 20 24 ns tARW Asynchronous Reset Width (Note 2) 4.5 5 7.5 12 14.5 15 18 ns tARR Asynchronous Reset Recovery Time (Note 2) 4.5 5 7.5 8 10 10 12 ns tAP Asynchronous Preset to Registered Output 8.5 9.5 11 16 19.5 20 24 ns tAPW Asynchronous Preset Width (Note 2) 4.5 5 7.5 12 14.5 15 18 ns tAPR Asynchronous Preset Recovery Time (Note 2) 4.5 5 7.5 8 10 10 12 ns tEA Input, I/O, or Feedback to Output Enable 7.5 9.5 10 12 14.5 15 18 ns tER Input, I/O, or Feedback to Output Disable 7.5 9.5 10 12 14.5 15 18 ns tLP tPD Increase for Powered-Down Macrocell (Note 3) 10 10 10 10 10 10 10 ns tLPS tS Increase for Powered-Down Macrocell (Note 3) 7777777 n s tLPCO tCO Increase for Powered-Down Macrocell (Note 3) 3333333 n s tLPEA tEA Increase for Powered-Down Macrocell (Note 3) 10 10 10 10 10 10 10 ns

MACH 1 & 2 Families 27 MACH211 AND MACH211SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1 Parameter Symbol Parameter Description UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max tPD Input, I/O, or Feedback to Combinatorial Output 6 7.5 10 12 14 15 18 ns tS Setup Time from Input, I/O, or Feedback to Clock D-type 5 5.5 6.5 7 8.5 10 12 ns T-type 5.5 6.5 7.5 8 10 11 13.5 ns tH Register Data Hold Time 0 0 0 0000 n s tCO Clock to Output 4 4.5 6 8 10 10 12 ns tWL Clock Width LOW 2.5 3 5 6 6 6 7.5 ns tWH HIGH 2.5 3 5 6 6 6 7.5 ns fMAX Maximum Frequency External Feedback 1/(tS + tCO) D-type 111 100 80 66.7 54 50 42 MHz T-type 105 91 74 62.5 50 47.6 39 MHz Internal Feedback (fCNT) D-type 166 133 100 83.3 69 66.6 55.6 MHz T-type 150 125 91 76.9 62.5 62.5 51.3 MHz No Feedback 1/(t WL + tWH) 200 167 100 83.3 83.3 83.3 66.7 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 5 5.5 6.5 7 8.5 10 12 ns tHL Latch Data Hold Time 0 0 0 0000 n s tGO Gate to Output 7 7.5 (note 4) (note 5) 10 11 11 (note 6) 13.5 ns tGWL Gate Width LOW 2.5 3 5 6 6 6 7.5 ns tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 9 9.5 12 14 17 17 (note 6) 20.5 ns tSIR Input Register Setup Time 1.5 2 2 2 2 2 2.5 ns tHIR Input Register Hold Time 1.5 2 2 2 2.5 2.5 3.5 ns tICO Input Register Clock to Combinatorial Output 10 11 13 15 18 18 (note 6) ns tICS Input Register Clock to Output Register Setup D-type 8 9 10 12 14.5 15 18 ns T-type 9 10 11 13 16 16 19.5 ns tWICL Input Register Clock Width LOW 2.5 3 5 6 6 6 7.5 ns tWICH HIGH 2.5 3 5 6 6 6 7.5 ns fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 200 167 100 83.3 83.3 83.3 66.7 MHz tSIL Input Latch Setup Time 1.5 2 2 2 2 2 2.5 ns tHIL Input Latch Hold Time 1.5 2 2 2 2.5 2.5 3.5 ns tIGO Input Latch Gate to Combinatorial Output 12 12 14 17 20 20 24 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 13 14 16 19 22 22 26.5 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 7 7.5 8.5 9 11 12 14.5 ns tIGS Input Latch Gate to Output Latch Setup 9 10 11 13 16 16 19.5 ns tWIGL Input Latch Gate Width LOW 2.5 3 5 6 6 6 7.5 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 12 12.5 14 16 19 19 23 ns

28 MACH 1 & 2 Families

Notes: 1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiﬁed where this parameter may be affected. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. 4. MACH211 t GO = 7 ns. MACH211SP tGO = 7.5 ns. 5. MACH211, commercial t GO = 7 ns. 6. The faster -18 t GO, tPDL, tICO, apply to MACH211 only, not MACH211SP. tAR Asynchronous Reset to Registered or Latched Output 9 9.5 15 16 19.5 20 24 ns tARW Asynchronous Reset Width (Note 2) 4 5 10 12 14.5 15 18 ns tARR Asynchronous Reset Recovery Time (Note 2) 4 5 10 10 10 10 12 ns tAP Asynchronous Preset to Registered or Latched Output 9 9.5 15 16 19.5 20 24 ns tAPW Asynchronous Preset Width (Note 2) 4 5 10 12 14.5 15 18 ns tAPR Asynchronous Preset Recovery Time (Note 2) 4 5 10 10 10 10 12 ns tEA Input, I/O, or Feedback to Output Enable 9 9.5 10 12 14 15 18 ns tER Input, I/O, or Feedback to Output Disable 9 9.5 10 12 14 15 18 ns tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 10 10 ns tLPCO tCO Increase for Powered-down Macrocell (Note 3) 0 0 0 0 0 0 0 ns tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 10 10 ns MACH211 AND MACH211SP (CONTINUED) SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1 Parameter Symbol Parameter Description UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max

MACH 1 & 2 Families 29 MACH221 and MACH221SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1 Parameter Symbol Parameter Description UnitMin Max Min Max Min Max Min Max Min Max Min Max tPD Input, I/O, or Feedback to Combinatorial Output 7.5 10 12 14 15 18 ns ts Setup Time from Input, I/O, or Feedback to Clock D-type 5.5 6.5 7 8.5 10 12 ns T-type 6.5 7.5 8 10 11 13.5 ns tH Register Data Hold Time 000000 n s tCO Clock to Output 5 6 8 10 10 12 ns tWL Clock Width L O W 35666 7 . 5 n s tWH HIGH 35666 7 . 5 n s fMAX Maximum Frequency External Feedback 1/(tS + tCO) D-type 95 80 66.7 54 50 42 MHz T-type 87 74 62.5 50 47.6 39 MHz Internal Feedback (fCNT) D-type 133 100 83.3 69 66.6 55.6 MHz T-type 125 91 76.9 62.5 62.5 51.3 MHz No Feedback 1/(t WL + tWH) 167 100 83.3 83.3 83.3 66.7 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 5.5 6.5 7 8.5 10 12 ns tHL Latch Data Hold Time 000000 n s tGO Gate to Output 7 7 (note 2) 10 11 11 13.5 ns tGWL Gate Width LOW 35666 7 . 5 n s tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 9.5 12 14 17 17 20.5 ns tSIR Input Register Setup Time 22222 2 . 5 n s tHIR Input Register Hold Time 2 2 2 2.5 2.5 3.5 ns tICO Input Register Clock to Combinatorial Output 11 13 15 18 18 22 ns tICS Input Register Clock to Output Register Setup D-type 9 10 12 14.5 15 18 ns T-type 10 11 13 16 16 19.5 ns tWICL Input Register LOW 35666 7 . 5 n s tWICH Clock Width HIGH 35666 7 . 5 n s fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 167 100 83.3 83.3 83.3 66.7 MHz tSIL Input Latch Setup Time 22222 2 . 5 n s tHIL Input Latch Hold Time 2 2 2 2.5 2.5 3.5 ns tIGO Input Latch Gate to Combinatorial Output 12 14 17 20 20 24 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 14 16 19 22 22 26.5 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 7.5 8.5 9 11 12 14.5 ns tIGS Input Latch Gate to Output Latch Setup 10 11 13 16 16 19.5 ns tWIGL Input Latch Gate Width LOW 35666 7 . 5 n s tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 11.5 14 16 19 19 23 ns tAR Asynchronous Reset to Registered or Latched Output 9.5 15 16 19.5 20 24 ns tARW Asynchronous Reset Width (Note 3) 5 10 12 14.5 15 18 ns tARR Asynchronous Reset Recovery Time (Note 3) 5 8 10 10 10 12 ns tAP Asynchronous Preset to Registered or Latched Output 9.5 15 16 19.5 20 24 ns

30 MACH 1 & 2 Families

Notes: 1. See “Switching Test Circuits” in the General Information section of the Vantis 1999 Data Book. 2. MACH221 t GO = 7 ns. MACH221SP tGO = 8 ns. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiﬁed where this parameter may be affected. 4. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. tAPW Asynchronous Preset Width (Note 3) 5 10 12 14.5 15 18 ns tAPR Asynchronous Preset Recovery Time (Note 3) 5 8 10 10 10 12 ns tEA Input, I/O, or Feedback to Output Enable 9.5 12 12 14 15 18 ns tER Input, I/O, or Feedback to Output Disable 9.5 12 12 14 15 18 ns tLP tPD Increase for Powered-down Macrocell (Note 4) 10 10 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 4) 10 10 10 10 10 10 ns tLPCO tCO Increase for Powered-down Macrocell (Note 4) 000000 n s tLPEA tEA Increase for Powered-down Macrocell (Note 4) 10 10 10 10 10 10 ns MACH221 and MACH221SP (CONTINUED) SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1 Parameter Symbol Parameter Description UnitMin Max Min Max Min Max Min Max Min Max Min Max

MACH 1 & 2 Families 31 MACH231 AND MACH231SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1 Parameter Symbol Parameter Description UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max tPD Input, I/O, or Feedback to Combinatorial Output 6 7.5 10 12 14 15 18 ns tS Setup Time from Input, I/O, or Feedback to Clock D-type 5 5.5 6.5 7 8.5 10 12 ns T-type 6 6.5 7.5 8 10 11 13.5 ns tH Register Data Hold Time 0000000 n s tCO Clock to Output 4 5 6.5 8 10 10 12 ns tWL Clock Width L O W 2 . 5 34666 7 . 5 n s tWH HIGH 2.5 34666 7 . 5 n s fMAX Maximum Frequency External Feedback 1/(tS + tCO) D-type 111 95 77 66.7 54 50 42 MHz T-type 100 87 72 62.5 50 47.6 39 MHz Internal Feedback (fCNT) D-type 166 133 100 83.3 69 66.6 55.6 MHz T-type 150 125 91 76.9 62.5 62.5 51.3 MHz No Feedback 1/(tWL + tWH) 200 167 125 83.3 83.3 83.3 66.7 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 5 5.5 6.5 7 8.5 10 12 ns tHL Latch Data Hold Time 0000000 n s tGO Gate to Output 5 6 7.5 8.5 11 11 13.5 ns tGWL Gate Width LOW 234666 7 . 5 n s tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 9 9.5 14 14.5 17 17 20.5 ns tSIR Input Register Setup Time 1.5 22222 2 . 5 n s tICO Input Register Clock to Combinatorial Output 10 11 15.5 16 18 18 22 ns tICS Input Register Clock to output Register Setup D-type 8 9 11 12 14.5 15 18 ns T-type 9 10 12 13 16 16 19.5 ns tWICL Input Register Clock Width L O W 2 . 5 34666 7 . 5 n s tWICH HIGH 2.5 34666 7 . 5 n s fMAXIR Maximum Input Register Frequency 200 167 125 83.3 83.3 83.3 66.7 MHz tHIL Input Latch Hold Time 1.5 2 2.5 3 3 3 3.5 ns tIGO Input Latch Gate to Combinatorial Output 11 12 17 17 20 20 24 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 13 14 18 19.5 22 22 26.5 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 7 7.5 10 10.5 11 12 14.5 ns tIGS Input Latch Gate to Output Latch Setup 9 10 11 13.5 16 16 19.5 ns

32 MACH 1 & 2 Families

Notes: 1. See “Switching Test Circuit” in the General Information section of the Vantis 1999 Data Book. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiﬁed where this parameter may be affected. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. CAPACITANCE 1 Note: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modiﬁed where these parameters may be affected. tWIGL Input Latch Gate Width LOW 234666 7 . 5 n s tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 11 12.5 16 17 19 19 23 ns tAR Asynchronous Reset to Registered or Latched Output 9 9.5 13 16 19.5 20 24 ns tARW Asynchronous Reset Width (Note 2) 4 5 10 12 14.5 15 18 ns tARR Asynchronous Reset Recovery Time (Note 2) 4 5 7 . 5 8 1 01 01 2n s tAP Asynchronous Preset to Registered or Latched Output 9 9.5 13 16 19.5 20 24 ns tAPW Asynchronous Preset Width (Note 2) 4 5 10 12 14.5 15 18 ns tAPR Asynchronous Preset Recovery Time (Note 2) 4 5 7.5 8 10 10 12 ns tEA Input, I/O, or Feedback to Output Enable 9 9.5 10 12 15 15 18 ns tER Input, I/O, or Feedback to Output Disable 9 9.5 10 12 15 15 18 ns tLP tPD Increase for Powered-down Macrocell (Note 3) 9 10 10 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 3) 6777777 n s tLPCO tCO Increase for Powered-down Macrocell (Note 3) 0000000 n s tLPEA tEA Increase for Powered-down Macrocell (Note 3) 9 10 10 10 10 10 10 ns Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance V IN = 2.0V V CC = 5.0V, TA = 25°C f = 1 MHz 6p F COUT Output Capacitance V OUT = 2.0V 8 pF MACH231 AND MACH231SP (CONTINUED) SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1 Parameter Symbol Parameter Description UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max

MACH 1 & 2 Families 33 ICC vs. FREQUENCY These curves represent the typical power consumption for a particular device at system frequency. The selected “typical” pattern is a 16-bit up-down counter. This pattern ﬁlls the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. TA = 25°C, VCC =5V 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 High Speed Low Power Frequency (MHz) ICC (mA) 100 125 150 0 1 02 03 04 05 06 07 08 09 0 High Speed Low Power Frequency (MHz) ICC (mA) 100 125 150 175 200 225 250 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Low Power Frequency (MHz) ICC (mA) 100 125 150 High Speed MACH111(SP) MACH131(SP) MACH211(SP) 0 1 02 03 04 05 06 07 08 09 0 High Speed Low Power Frequency (MHz) ICC (mA) 100 125 150 175 200 225 250 MACH 221(SP) 275 Low Power Frequency (MHz) 100 150 200 250 300 350 400 High Speed MACH231 Low Power Frequency (MHz) 100 150 200 250 300 350 High Speed MACH231SP400 0 1 02 03 04 05 06 07 08 00 1 02 03 04 05 06 07 08 0 ICC (mA) ICC (mA)

34 MACH 1 & 2 Families

Table 12. ICC

MACH 1 & 2 Families 35 44- PIN PLCC CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND MACH111SP-5/7/10/12/15) Top View 44-Pin PLCC PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Note: 1. Pin designators in parentheses ( ) apply to the MACH111SP 1 44 43 425 4 3 264 1 40 23 24 25 2619 20 21 2218 27 28 I/O5 I/O6 I/O7 (TDI) I0 (CLK 0/I0) CLK0/I1 GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11 I/O27 I/O26 I/O25 I/O24 CLK3/I5 (TDO) GND CLK2/I4 (CLK 1/I1) I3 (TMS) I/O23 I/O22 I/O21 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 Block BBlock A 14051K-018

36 MACH 1 & 2 Families

44-PIN TQFP CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND MACH111SP-5/7/10/12/15) Top View 44-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Note: 1. Pin designators in parentheses ( ) apply to the MACH111SP I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 CLK3/I5 (TDO) GND CLK2/I4 (CLK 1/I1) I3 (TMS) I/O23 I/O22 I/O21 I/O5 I/O6 I/O7 (TDI) I0 (CLK 0/I0) CLK0/I1 GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11 Block BBlock A 14051K-019

MACH 1 & 2 Families 37 84-PIN PLCC CONNECTION DIAGRAM (MACH131-5/7/10/12/15) Top View 84-Pin PLCC PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage 123 818283846789 45 80 76777879 75 43424140 4746454437363534 393833 48 52515049 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I0 VCC GND CLK1/I1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O8 GND I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I4 VCC CLK2/I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 GND I/O40 GND VCC I/O0 I/O62 I/O63 VCC I/O3 I/O4 I/O5 I/O6 I/O1 I/O2 I/O61 I/O57 I/O58 I/O59 I/O60 I/O56 I/O7 GND GND VCC I/O34 I/O33 I/O32 VCC I/O29 I/O28 I/O27 I/O26 I/O31 I/O30 I/O35 I/O39 I/O38 I/O37 I/O36 GND I/O25 I/O24 Block A Block D Block B Block C 14051K-020

38 MACH 1 & 2 Families

100-PIN PQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15) Top View 100-Pin PQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 GND GND I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND TDI I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 IO/CLK0 GND GND VCC VCC I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 N/C TCK GND GND 10031 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 TMS GND GND GND TDO N/C I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND GND VCC VCC I3/CLK2 I/O47 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND VCC GND VCC VCC VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 Block DBlock A Block CBlock B 14051K-021

MACH 1 & 2 Families 39 100-PIN TQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15) Top View 100-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out TDI I/5 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 V CC GND GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC TCK GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 NC V CC GND GND V CC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND 100 GND GND NC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 V CC GND GND V CC NC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND TDO NC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND V CC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 TMS Block DBlock A Block CBlock B 14051K-022

40 MACH 1 & 2 Families

44-PIN PLCC CONNECTION DIAGRAM (MACH211-7/10/12/15 AND MACH211SP-6/7/10/12/15) Top View 44-Pin PLCC PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Note: 1. Pin designators in parentheses ( ) apply to the MACH211SP 1 44 43 425 4 3 264 1 40 23 24 25 2619 20 21 2218 27 28 I/O5 I/O6 I/O7 (TDI) I0 (CLK 0/I0) CLK0/I1 GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11 I/O27 I/O26 I/O25 I/O24 CLK3/I5 (TDO) GND CLK2/I4 (CLK 1/I1) I3 (TMS) I/O23 I/O22 I/O21 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 Block DBlock A Block B Block C 14051K-023

MACH 1 & 2 Families 41 44-PIN TQFP CONNECTION DIAGRAM (MACH211-7/10/12/15 AND MACH211SP-6/7/10/12/15) Top View 44-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Note: 1. Pin designators in parentheses ( ) apply to the MACH211SP I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 CLK3/I5 (TDO) GND CLK2/I4 (CLK 1/I1) I3 (TMS) I/O23 I/O22 I/O21 I/O5 I/O6 I/O7 (TDI) I0 (CLK 0/I0) CLK0/I1 GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11 Block B Block C Block DBlock A 14051K-024

42 MACH 1 & 2 Families

68-PIN PLCC CONNECTION DIAGRAM (MACH221-7/10/12/15) Top View 68-Pin PLCC PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage Block GBlock F Block EBlock D Block C Block A Block B Block H 1 68 67 66 65 64 63 62 6176543298 35 36 37 38 39 40 41 42 4329 30 31 32 33 3427 28 I/O7 I/O8 I/O9 I/O10 I/O11 CLK0/I0 CLK1/I1 VCC GND I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 GND I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 GND I/O30 I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 GND VCC CLK3/I5 CLK2/I4 I/O35 I/O34 I/O33 I/O32 I/O31 I/O6 GND I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 GND 14051K-025

MACH 1 & 2 Families 43 100-PIN PQFP CONNECTION DIAGRAM (MACH221SP-7/10/12/15) Top View 100-Pin PQFP PIN DESIGNATIONS I/CLK = Input or Clock GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out N/C I/O5 N/C I/O4 I/O3 I/O2 I/O1 I/O0 GND GND I/O47 I/O46 I/O45 I/O44 I/O43 N/C I/O42 N/C GND GND TDI N/C I/O6 N/C I/O7 I/O8 I/O9 I/O10 I/O11 IO/CLK0 GND GND VCC VCC I1/CLK1 I/O12 I/O13 I/O14 I/O15 I/O16 N/C I/O17 N/C TCK GND GND 10031 I/O34 I/O33 I/O32 I/O31 N/C I/O30 N/C TMS GND GND GND TDO N/C I/O41 N/C I/O40 I/O39 I/O38 I/O37 I/O36 I5/CLK3 GND GND VCC VCC I4/CLK2 I/O35 GND N/C I/O18 N/C I/O19 I/O20 I/O21 I/O22 I/O23 GND VCC GND VCC VCC VCC I/O24 I/O25 I/O26 I/O27 I/O28 N/C I/O29 N/C Block A Block H Block D Block E Block C Block B Block GBlock F 14051K-026

44 MACH 1 & 2 Families

84-PIN PLCC CONNECTION DIAGRAM (MACH231-6/7/10/12/15) Top View 84-Pin PLCC PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage Block G Block C 123 818283846789 45 80 76777879 75 43424140 4746454437363534 393833 48 52515049 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK 0/I0 VCC GND CLK 1/I1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O8 GND I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK 3/I4 VCC CLK 2/I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 GND I/O40 GND VCC I/O0 I/O62 I/O63 VCC I/O3 I/O4 I/O5 I/O6 I/O1 I/O2 I/O61 I/O57 I/O58 I/O59 I/O60 I/O56 I/O7 GND GND VCC I/O34 I/O33 I/O32 VCC I/O29 I/O28 I/O27 I/O26 I/O31 I/O30 I/O35 I/O39 I/O38 I/O37 I/O36 GND I/O25 I/O24 Block B Block A Block H Block D Block E Block F 14051K-027

MACH 1 & 2 Families 45 100-PIN PQFP CONNECTION DIAGRAM (MACH231SP-10/12/15) Top View 100-Pin PQFP PIN DESIGNATIONS I/CLK = Input or Clock GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Block E Block B I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 GND GND I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND TDI I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 IO/CLK0 GND GND VCC VCC I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 N/C TCK GND GND 10031 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 TMS GND GND GND TDO N/C I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND GND VCC VCC I3/CLK2 I/O47 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND VCC GND VCC VCC VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 Block A Block H Block D Block C Block F Block G 14051K-028

46 MACH 1 & 2 Families

100-PIN TQFP CONNECTION DIAGRAM (MACH231SP-10/12/15) Top View 100-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Block BBlock C TDI I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 V CC GND GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC TCK GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 NC V CC GND GND V CC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND 100 GND GND NC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 V CC GND GND V CC NC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND TDO NC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND V CC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 TMS Block A Block H Block D Block E Block F Block G 14051K-029

MACH 1 & 2 Families 47

ORDERING INFORMATION

Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combination of: Valid Combinations The Valid Combinations list conﬁgurations planned to be supported in volume for this device. Consult the local Lattice/ Vantis sales ofﬁce to conﬁrm availability of speciﬁc valid combinations and to check on newly released combinations. Note: 1. All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e. MACH131SP-5YC-7YI SP FAMILY TYPE MACH = Macro Array CMOS High-Density MACH 131 Y C MACROCELL DENSITY 111 = 32 Macrocells, 32 I/Os 131 = 64 Macrocells, 64 I/Os 211 = 64 Macrocells, 32 I/Os 221 = 96 Macrocells, 48 I/Os 231 = 128 Macrocells, 64 I/Os PRODUCT DESIGNATION SP = JTAG-compatible, In-system Programmable OPERATING CONDITIONS C = Commercial (0 °C to +70°C) I = Industrial (-40 °C to +85°C) PACKAGE TYPE J = Plastic Leaded Chip Carrier (PLCC) V = Thin Quad Flat Pack (TQFP) Y = Plastic Quad Flat Pack (PQFP) SPEED -5 = 5.0 or 5.5 ns t PD -6 = 6.0 ns t PD -7 = 7.5 ns t PD -10 = 10 ns t PD -12 = 12 ns t PD -14 = 14 ns t PD -15 = 15 ns t PD -18 = 18 ns t PD PROGRAMMING DESIGNATOR Blank = Initial Algorithm /1 = First Revision Valid Combinations – Commercial MACH111SP -5, -7, -10, -12, -15 JC, VC MACH131SP -5, -7, -10, -12, -15 VC, YC MACH211 -7, -10, -12, -15 JC, VC MACH211SP -6, -7, -10, -12, -15 JC, VC MACH221 -7, -10, -12, -15 JC MACH221SP -7, -10, -12, -15 YC MACH231 -6, -7 JC -10, -12, -15 JC/1 MACH231SP -10, -12, -15 VC, YC Valid Combinations – Industrial MACH211 -10, -12, -14, -18 JI MACH211SP -10, -12, -14, -18 JI MACH221 -10, -12, -14, -18 JI MACH221SP -10, -12, -14, -18 YI MACH231 -12, -14, -18 JI/1 MACH231SP -12, -14, -18 YI

48 MACH 1 & 2 Families

Product Information

MACH211SP-7VC specifications and overview.

Summary

High-Performance EE CMOS Programmable Logic

Description

High-Performance EE CMOS Programmable Logic

Source title MACH211SP-7VC Datasheet(PDF) - Lattice Semiconductor

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