MACH120-12

MACH120-12 LATTICE | Alldatasheet

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Publication# 14129 Rev: J Amendment/0 Issue Date: November 1997 MACH 1 & 2 Families MACH 1 & 2 FAMILIES COM’L: -12/15 IND: -18 MACH120-12/15 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS u

68 Pins in PLCC

u

48 Macrocells

u 12 ns t PD Commercial, 18 ns t PD Industrial u

77 MHz f

u

48 I/Os; 4 dedicated inputs; 4 dedicated inputs/clocks

u

48 Outputs

u

48 Flip-flops; 4 clock choices

u 4 “PALCE26V12” blocks u SpeedLocking™ for guaranteed fixed timing u Pin-compatible with the MACH221 GENERAL DESCRIPTION The MACH120 is a member of the high-performance EE CMOS MACH 1 family. This device has approximately five times the logic macrocell capability of the popular PALCE22V10 without loss of speed. The MACH120 consists of four PAL blocks interconnected by a programmable switch matrix. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH120 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. Lattice Semiconductor

MACH 1 & 2 Families BLOCK DIAGRAM 14129J-1 I/O Cells Macrocells I/O0–I/O11 52 x 54 AND Logic Array and Logic Allocator OE I/O Cells Macrocells I/O12–I/O23 52 x 54 AND Logic Array and Logic Allocator OE 26 26 I2–I3 I6–I7 I/O Cells Macrocells I/O36–I/O47 52 x 54 AND Logic Array and Logic Allocator OE I/O Cells Macrocells I/O24–I/O35 52 x 54 AND Logic Array and Logic Allocator OE Switch Matrix CLK 0/I0, CLK 1/I1, CLK 2/I4, CLK3/I5 Block D Block C Block A Block B

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Note: Pin-compatible with the MACH220 and MACH221. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage 1 68 67 66 65 64 63 62 617 6 5 4 3 29 8 35 36 37 38 39 40 41 42 43 29 30 31 32 33 34 27 28 I/O7 I/O8 I/O9 I/O10 I/O11 CLK 0/I0 CLK 1/I1 VCC GND I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 GND I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 GND I/O30 I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 GND VCC CLK 3/I5 CLK 2/I4 I/O35 I/O34 I/O33 I/O32 I/O31 I/O6 GND I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 GND Block A Block D Block B Block C 14129J-2

MACH120-12/15 (Com’l) 5 MACH 1 & 2 Families

ORDERING INFORMATION

Vantis programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. FAMILY TYPE MACH = Macro Array CMOS High-Speed MACH 120 –12 J C DEVICE NUMBER 120 = 48 Macrocells, 68 Pins SPEED –12 = 12 ns tPD –15 = 15 ns tPD OPERATING CONDITIONS C = Commercial (0°C to +70°C) PACKAGE TYPE J = 68-Pin Plastic Leaded Chip Carrier (PL 068) Valid Combinations MACH120-12 JC MACH120-15

6 MACH120-18 (Ind)

Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. FAMILY TYPE MACH = Macro Array CMOS High-Speed MACH 120 –18 J I DEVICE NUMBER 120 = 48 Macrocells, 68 Pins SPEED –18 = 18 ns tPD OPERATING CONDITIONS I = Industrial (–40°C to +85°C) PACKAGE TYPE J = 68-Pin Plastic Leaded Chip Carrier (PL 068) Valid Combinations MACH120-18 JI

the PAL block look effectively like an independent “PALCE26V12”. the output enable product terms. flip-flop initialization. All flip-flops within the PAL block are initialized together. product terms are used for the first six I/O cells; the other two control the last six macrocells. software automatically configures the logic allocator when fitting the design into the device. block. Refer to Figure 1 for cluster and macrocell numbers. Table 1. Logic Allocation

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The MACH120 macrocells can be configured as either registered or combinatorial, with programmable polarity. The macrocell provides internal feedback whether configured as registered or combinatorial. The flip-flops can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of four global clock pins, which are also available as logic inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The I/O Cell The I/O cell in the MACH120 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to six I/O cells. Within each PAL block, two product terms are available for selection by the first six three-state outputs; two other product terms are available for selection by the last six three-state outputs. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. SpeedLocking for Guaranteed Fixed Timing The unique MACH 1 architecture is designed for high performance—a metric that is met in both raw speed, but even more importantly, guaranteed fixed speed . Using the design of the central switch matrix, the MACH 120 product offers the SpeedLocking feature, which allows a stable fixed pin-to-pin delay, independent of logic paths, routing resources and design refits for up to 16 product terms per output. Other non-Vantis CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine for continuous, high performance required in today's demanding designs

Figure 1. MACH120 PAL Block

10 MACH120-12/15 (Com’l)

CC + 0.5 V DC Output or I/O CC + 0.5 V Latchup Current Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Rat- ings for extended periods may affect device reliability. Pro- gramming conditions may differ. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of I IL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measur ed with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = -3.2 mA, VCC = Min VIN = VIH or VIL 2.4 V VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 V V IL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V I IH Input HIGH Current V IN = 5.25 V, VCC = Max (Note 2) 10 mA IIL Input LOW Current V IN = 0 V, VCC = Max (Note 2) -10 mA IOZH Off-State Output Leakage Current HIGH V OUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 mA IOZL Off-State Output Leakage Current LOW V OUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) -10 mA ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) -30 -130 mA ICC Supply Current (Typical) VCC = 5 V, TA=25°C, f = 25 MHz (Note 4) 85 mA

MACH120-12/15 (Com’l) 11 MACH 1 & 2 FamiliesCAPACITANCE (Note 1) SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit, for test conditions. Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance V IN = 2.0 V VCC = 5.0 V, TA = 25°C f = 1 MHz 6 pF COUT Output Capacitance V OUT = 2.0 V 8 pF Parameter Symbol Parameter Description -12 -15 Unit Min Max Min Max tPD Input, I/O, or Feedback to Combinatorial Output 12 15 ns tS Setup Time from Input, I/O, or Feedback to Clock D-type 7 10 ns T-type 8 11 ns tH Hold Time 0 0 ns tCO Clock to Output 8 10 ns tWL CLock Width LOW 6 6 ns tWH HIGH 6 6 ns fMAX Maximum Frequency (Note 1) External Feedback D-type 66.7 50 MHz T-type 62.5 47.6 MHz Internal Feedback (f CNT) D-type 76.9 66.6 MHz T-type 71.4 55.5 MHz No Feedback 83.3 83.3 MHz tAR Asynchronous Reset to Registered Output 16 20 ns tARW Asynchronous Reset Width (Note 1) 12 15 ns tARR Asynchronous Reset Recovery Time (Note 1) 8 10 ns tAP Asynchronous Preset to Registered Output 16 20 ns tAPW Asynchronous Preset Width (Note 1) 12 15 ns tAPR Asynchronous Preset Recovery Time (Note 1) 8 10 ns tEA Input, I/O, or Feedback to Output Enable 12 15 ns tER Input, I/O, or Feedback to Output Disable 12 15 ns

12 MACH120-18 (Ind)

CC + 0.5 V DC Output or I/O CC + 0.5 V Latchup Current Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Rat- ings for extended periods may affect device reliability. Pro- gramming conditions may differ. INDUSTRIAL OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA ) Supply Voltage (VCC ) Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over INDUSTRIAL operating ranges Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of I IL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measur ed with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Parameter Symbol P arameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = -3.2 mA, VCC = Min VIN = VIH or VIL 2.4 V VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 V V IL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V I IH Input HIGH Current V IN = 5.25 V, VCC = Max (Note 2) 10 mA IIL Input LOW Current V IN = 0 V, VCC = Max (Note 2) -10 mA IOZH Off-State Output Leakage Current HIGH V OUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 mA IOZL Off-State Output Leakage Current LOW V OUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) -10 mA ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) -30 -130 mA ICC Supply Current (Typical) V CC = 5 V, TA = 25°C, f = 25 MHz (Note 4) 85 mA

MACH120-18 (Ind) 13 MACH 1 & 2 FamiliesCAPACITANCE (Note 1) SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 24 outputs switching. Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V VCC = 5.0 V, TA = 25°C f = 1 MHz 6 pF COUT Output Capacitance V OUT = 2.0 V 8 pF Parameter Symbol Parameter Description -18 Unit Min Max tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 18 ns tS Setup Time from Input, I/O, or Feedback D-type 12 ns T-type 13.5 ns tH Hold Time 0 ns tCO Clock to Output (Note 3) 12 ns tWL Clock Width LOW 7.5 ns t WH HIGH 7.5 ns fMAX Maximum Frequency (Note External Feedback 1/(t S + tCO) D-type 40 MHz T-type 38 MHz Internal Feedback (fCNT) D-type 53 MHz T-type 44 MHz No Feedback 1/(t WL + tWH) 66.5 MHz tAR Asynchronous Reset to Registered Output 24 ns tARW Asynchronous Reset Width (Note 1) 18 ns tARR Asynchronous Reset Recovery Time (Note 1) 12 ns tAP Asynchronous Preset to Registered Output 24 ns tAPW Asynchronous Preset Width (Note 1) 18 ns tAPR Asynchronous Preset Recovery Time (Note 1) 12 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 18 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 18 ns

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TYPICAL CURRENT vs. VOLTAGE (I-V) CHARACTERISTICS VCC = 5.0 V, TA = 25°C IOL (mA) –20 –40 –60 –80 VOL (V) Output, LOW 14129 IOH (mA) –25 –50 –75 –100 –3 –2 –1 1 2 3 4 5 VOH (V) Output, HIGH –125 –150 14129J-5 II (mA) –20 –40 –60 –80 –2 –1 1 2 3 4 5 VI (V) Input –100 14129J-6

MACH 1 & 2 FamiliesTYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C The selected “typical” pattern is a 12-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. 150 125 100 0 10 20 30 40 50 60 70 I CC (mA) Frequency (MHz) 14129J-7

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TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Plastic qjc Considerations The data listed for plastic qjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the qjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, qjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. The thermal measurements are taken with components on a six-layer printed circuit board. SWITCHING WAVEFORMS Notes: 1. V T = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. Parameter Symbol Parameter Description Typ Unit PLCC q jc Thermal impedance, junction to case 13 °C/W qja Thermal impedance, junction to ambient 37 °C/W qjma Thermal impedance, junction to ambient with air flow 200 lfpm air 33 °C/W 400 lfpm air 30 °C/W 600 lfpm air 28 °C/W 800 lfpm air 25 °C/W 14129J-8 Combinatorial Output tPD Input, I/O, or Feedback Combinatorial Output VT VT 14129J-9 Registered Output VT Input, I/O, or Feedback Registered Output tS tCO VT tH VTClock 14129J-10 Clock Width tWH Clock tWL

MACH 1 & 2 FamiliesSWITCHING WAVEFORMS Notes: 1. V T = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. VT VT tARW VT tAR Input, I/O, or Feedback Registered Output Clock tARR 14129J-11 Asynchronous Reset Input, I/O, or Feedback VT VT tAPW VT tAP tAPR Registered Output Clock 14129J-12 Asynchronous Preset 14129J-13 Output Disable/Enable VT VTOutputs tER tEA VOH – 0.5 V VOL + 0.5 V Input, I/O, or Feedback

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KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUIT *Switching several outputs simultaneously should be avoided for accurate measurement. Specification S 1 C L Commercial Measured Output Value R1 R 2 tPD, tCO Closed 35 pF

300 W 390 W

1.5 V tEA Z fi H: Open Z fi L: Closed tER H fi Z: Open L fi Z: Closed 5 pF H fi Z: VOH – 0.5 V L fi Z: VOL + 0.5 V Must be Steady May Change from H to L May Change from L to H Does Not Apply Don’t Care, Any Change Permitted Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is High- Impedance “Off” State WAVEFORM INPUTS OUTPUTS KS000010-PAL 14129J-14 C L Output R 1 R 2 Test Point 5 V

MACH 1 & 2 FamiliesFMAX PARAMETERS The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Be- cause the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the exter- nal signals (t S + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated “fMAX external.” The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these condi- tions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This f MAX is designated “fMAX internal”. A simple in- ternal counter is a good example of this type of design; therefore, this parameter is sometimes called “fCNT.” The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the pe- riod is limited by the sum of the data setup time and the data hold time (t S + tH). However, a lower limit for the period of each f MAX type is the minimum clock period (t WH + tWL). Usually, this minimum clock period determines the period for the third f MAX, designated “fMAX no feed- back.” For devices with input registers, one additional f MAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as f MAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that f MAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by t ICS. All frequencies except f MAX internal are calculated from other measured AC parameters. f MAX internal is measured directly. LOGIC REGISTER CLK LOGIC REGISTER CLK tCOtS tS tS fMAX Internal (fCNT ) fMAX External 1/(ts + tCO ) LOGIC REGISTER CLK fMAX No Feedback; 1/(ts + tH ) or 1/(tWH + tWL ) (SECOND CHIP) REGISTER LOGIC CLK fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH ) tSIR tHIR

20 MACH120-12/15

The MACH families are manufactured using Vantis’ advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics INPUT/OUTPUT EQUIVALENT SCHEMATICS Parameter Symbol Parameter Description Units Test Conditions tDR Min Pattern Data Retention Time

10 Years Max Storage Temperature

20 Years Max Operating Temperature

N Max Reprogramming Cycles 100 Cycles Normal Programming Conditions VCC ESD Protection 1 kW Input VCC 100 kW Preload Circuitry Feedback Input I/O VCCVCC 100 kW 1 kW 14129J-15

MACH 1 & 2 FamiliesPOWER-UP RESET The MACH devices have been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in sim- plifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways V CC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Power-Up Reset Waveform Parameter Symbol P arameter Descriptions Max Unit tPR Power-Up Reset Time 10 ms tS Input or Feedback Setup Time See Switching Characteristicst WL Clock Width LOW 14129J-16 tPR tWL tS 4 V VCC Power Registered Output Clock