M5LV-128/104-7HI

MACH5 LATTICE | Alldatasheet

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Publication# 20446 Rev: I Amendment/ Issue Date: September 2000 MACH

5 CPLD Family

Fifth Generation MACH Architecture

FEATURES

N High logic densities and I/Os for increased logic integration — 128 to 512 macrocell densities — 68 to 256 I/Os N Wide selection of density and I/O combinations to support most application needs — 6 macrocell density options — 7 I/O options — Up to 4 I/O options per macrocell density — Up to 5 density & I/O options for each package N Performance features to fit system needs — 5.5 ns t PD Commercial, 7.5 ns t PD Industrial — 182 MHz f CNT — Four programmable power/speed settings per block N Flexible architecture facilitates logic design — Multiple levels of switch matrices allow for performance-based routing — 100% routability and pin-out retention — Synchronous and asynchronous clocking, including dual-edge clocking — Asynchronous product- or sum-term set or reset — 16 to 64 output enables — Functions of up to 32 product terms N Advanced capabilities for easy system integration — 3.3-V & 5-V JEDEC-compliant operations — IEEE 1149.1 compliant for boundary scan testing — 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port — PCI compliant (-5/-6/-7/-10/-12 speed grades) — Safe for mixed supply voltage system design — Bus-Friendly™ Inputs & I/Os — Individual output slew rate control — Hot socketing — Programmable security bit N Advanced E CMOS process provides high performance, cost effective solutions N Supported by ispDesignEXPERT™ software for rapid logic development — Supports HDL design methodologies with results optimized for MACH 5 devices — Flexibility to adapt to user requirements — Software partnerships that ensure customer success N Lattice and Third-party hardware programming support — LatticePRO™ software for in-system programmability support on PCs and Automated Test Equipment — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General

2 MACH 5 Family

1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.

5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation. Table 1. MACH 5 Device Features

1. C = Commercial grade, I = Industrial grade
2. /1 version recommended for new designs

options to meet a wide range of design needs (Table 3).

1. The I/O options indicated with a “*” are obsolete, please contact factory for more information.

Table 2. MACH 5 Speed Grades Table 3. MACH 5 Package and I/O Options

4 MACH 5 Family

programmable through an IEEE 1149.1 Test Access Port (TAP) interface. available which can also be used as logic inputs. resembles an independent PAL device, it has superior control and logic generation capabilities. block interconnect lines and local feedback lines to the PAL block inputs.

16 MCs

4 Blocks

Figure 1. MACH 5 Block Diagram

of-products function with either 3 of 4 product terms. gate for separate logic generation and/or polarity control. 32 product terms) with only one pass through the logic array. Table 4. Product Term Steering Options for PT Clusters and Macrocells Figure 2. PAL Block Structure

6 MACH 5 Family

as T-type, J-K, or S-R operation through the use of the XOR gate associated with each macrocell. used as “buried” macrocells to drive device logic via the matrix. available as well as advanced clocking features such as complementary and biphase clocking. Figure 3. Macrocell Diagram

8 MACH 5 Family

output enables per PAL block (Figure 6). Figure 6. Output Enable Generator and I/O Cell

gone through the output buffer, it is using external feedback. BUF, is defined as the time it takes to go through the output buffer to the I/O pad. BUF to this internal parameter, the external parameter is derived. for a more detailed discussion about the timing parameters. Figure 7. MACH 5 Timing Model

10 MACH 5 Family

MULTIPLE I/O AND DENSITY OPTIONS The MACH 5 family offers six macrocell densities in a number of I/O options. This allows designers to choose a device close to their logic density and I/O requirements, thus minimizing costs. For the same package type, every density has the same pin-out. With proper design considerations, a design can be moved to a higher or lower density part as required. IEEE 1149.1 - COMPLIANT BOUNDARY SCAN TESTABILITY Most MACH 5 devices have boundary scan registers and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more complete board-level testing. IEEE 1149.1 - COMPLIANT IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All MACH 5 devices provide in-system programming (ISP) capability through their IEEE 1149.1- compliant Boundary Scan Test Access Port. By using the IEEE 1149.1-compliant Boundary Scan Test Access Port as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface. MACH 5 devices can be programmed across the commercial temperature and voltage range. The PC-based LatticePRO software facilitates in-system programming of MACH 5 devices. LatticePRO software takes the JEDEC file output produced by design implementation software, along with information about the Boundary Scan chain, and creates a set of vectors that are used to drive the Boundary Scan chain. LatticePRO software can use these vectors to drive a Boundary Scan chain via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats understood by common automated test equipment. This equipment can then be used to program MACH 5 devices during the testing of a circuit board. PCI COMPLIANT MACH 5 devices in the -5/-6/-7/-10/-12 speed grades are compliant with the PCI Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above V CC because of their 5-V input tolerant feature. MACH 5 devices provide the speed, drive, density, output enables and I/Os for the most complex PCI designs.

Both the 3.3-V and 5-V VCC MACH 5 devices are safe for mixed supply voltage system designs.

1. Excludes original M5-128, M5-192, and M5-256 while M5-128/1, M3-192/1 and M5-256/1 are supported. Please refer to

Application Note titled “Hot Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices”. Characteristics on the Lattice Data Book CD-ROM or Lattice web site. to run at maximum frequency while the rest of the signal paths operate in a lower-power mode. speed. The slew rate is adjusted independent of power. Table 5. Power Levels

12 MACH 5 Family

initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset delay time has elapsed. SECURITY BIT A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device.

0 4 8 1 21 62 02 42 83 2 6 3 36 40 44 48 52 56 60 20446G-015

14 MACH 5 Family

BLOCK DIAGRAM — M5(LV)-128/XXX Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT

2 PT OE

Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect S E G M E N T I N T E R C O N N E C T CLK0 CLK1 CLK2 CLK3 SEGMENT 0 SEGMENT 1 I0, 1 I2, 3 20446G-007

BLOCK DIAGRAM — M5-192/XXX Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect S E G M E N T I N T E R C O N N E C T CLK0 CLK1 CLK2 CLK3 SEGMENT 0 SEGMENT 2 SEGMENT 1 I0 I2, I3 20446G-008

16 MACH 5 Family

BLOCK DIAGRAM — M5(LV)-256/XXX Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect S E G M E N T I N T E R C O N N E C T CLK0 CLK1 CLK2 CLK3 SEGMENT 0 SEGMENT 3 SEGMENT 2SEGMENT 1 I0 I3 I1 I2 20446G-009

BLOCK DIAGRAM — M5(LV)-320/XXX Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect S E G M E N T CLK0 CLK1 CLK2 CLK3 SEGMENT 0 SEGMENT 4 SEGMENT 2SEGMENT 1 I1 I2 I3 Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect I N T E R C O N N E C T SEGMENT 3 20446G-010

18 MACH 5 Family

BLOCK DIAGRAM — M5(LV)-384/XXX Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect S E G M E N T CLK0 CLK1 CLK2 CLK3 SEGMENT 0 SEGMENT 5 SEGMENT 2SEGMENT 1 I1 I2 Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect I N T E R C O N N E C T SEGMENT 3 Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block InterconnectI3 SEGMENT 4 20446G-011

BLOCK DIAGRAM — M5(LV)-512/XXX Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect S E G M E N T CLK0 CLK1 CLK2 CLK3 SEGMENT 0 SEGMENT 7 SEGMENT 2SEGMENT 1 20446G-012 Continued

20 MACH 5 Family

BLOCK DIAGRAM — M5(LV)-512/XXX Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect Macrocells 64 x 73 AND Logic Array and Logic Allocator Control Generator 64 PT Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block Interconnect I N T E R C O N N E C T SEGMENT 6 SEGMENT 5 SEGMENT 4SEGMENT 3 20446G-013 Continued

Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Supply Voltage (VCC) Industrial (I) Devices Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges define those limits between which the functionality of the device is guaranteed. Note: 1. 150° for M5-128, M5-192 and M5-256 devices. 130° for M5-128/1, M5-192/1, M5-256/1, M5-320, M5-384 and M5-512 devices. 2. Total I OL between ground pins should not exceed 64 mA. 3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included. 4. I/O pin leakage is the worst case of I IL and IOZL or IIH and IOZH. 5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. 5-V DC CHARACTERISITICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Description Min Typ Max Unit VOH Output HIGH Voltage M5-384, M5-512 Devices) IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V IOH = 0 mA, VCC = Max, VIN = VIH or VIL 3.3 V Output HIGH Voltage (For M5-128, M5-192, M5-256 Devices) IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V IOH = -2.5 mA, VCC = 5.25 V, VIN = VIH or VIL 3.6 V VOL Output LOW Voltage (Note 2) IOL = +16 mA, VCC = Min, VIN = VIH or VIL 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 3) 2.0 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 3) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25, VCC = Max (Note 4) 10 µA IIL Input LOW Leakage Current VIN = 0, VCC = Max (Note 4) -10 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25, VCC = Max, VIN = VIH or VIL (Note 4) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0, VCC = Max, VIN = VIH or VIL (Note 4) -10 µA ISC Output Short-Circuit Current VOUT = 0.5 VCC = Max, VIN = VIH or VIL (Note 5) -30 -180 mA

22 MACH 5 Family

Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Supply Voltage (VCC) Industrial (I) Devices Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges define those limits between which the functionality of the device is guaranteed. Notes: 1. Total I OL between ground pins should not exceed 64 mA. 2. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included. 3. I/O pin leakage is the worst case of I IL and IOZL or IIH and IOZH. 4. Not more than one output should be shorted at one time. Duration of the short-circuit should not exceed one second. 3.3-V DC CHARACTERISITICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Description Min Max Unit VOH Output HIGH Voltage VCC = Min I OH = -100 µA VCC -0.2 V VIN = VIH or VIL IOH = 3.2 mA 2.4 V VOL Output LOW Voltage VCC = Min VIN = VIH or VIL IOL = 100 µA 0.2 V IOL = 16 mA (Note 1) 0.5 V VIH Input HIGH Voltage V OUT ≥ VOH Min or VOUT ≤ VOL Max (Note 2) 2.0 5.5 V VIL Input LOW Voltage V OUT ≥ VOH Min or VOUT ≤ VOL Max (Note 2) -0.3 0.8 V IIH Input HIGH Leakage Current V IN = 3.6, VCC = Max (Note 3) 10 µA IIL Input LOW Leakage Current V IN = 0, VCC = Max (Note 3) -10 µA IOZH Off-State Output Leakage Current HIGH V OUT = 3.6, VCC = Max, VIN = VIH or VIL (Note 3) 10 µA IOZL Off-State Output Leakage Current LOW V OUT = 0, VCC = Max, VIN = VIH or VIL (Note 3) -10 µA ISC Output Short-Circuit Current V OUT = 0.5 VCC = Max, VIN = VIH or VIL (Note 4) -15 -160 mA

M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Combinatorial Delay: tPDi Internal combinatorial propagation Registered Delays: t Latched Delays: t tPDL Propagation delay through transparent Input Register Delays: tSIRS Input register setup time using a tSIRA Input register setup time using an tHIRS Input register hold time using a tHIRA Input register hold time using an Input Latch Delays: Output Delays: t

24 MACH 5 Family

Power Delays: tPL1 Power level 1 delay (Note 2) 4.0 (5.0) 4.0 4.0 (5.0) 4.0 (5.0) 4.0 (5.0) 4.0 (5.0) 4.0 (5.0) ns tPL2 Power level 2 delay (Note 2) 6.0 (9.0) 6.0 6.0 (9.0) 6.0 (9.0) 6.0 (9.0) 6.0 (9.0) 6.0 (9.0) ns tPL3 Power level 3 delay (Note 2) 9.0 (17.5) 9.0 9.0 (17.5) 9.0 (17.5) 9.0 (17.5) 9.0 (17.5) 9.0 (17.5) ns Additional Cluster Delay: Interconnect Delays: t Reset and Preset Delays: tSRi Asynchronous reset or preset to internal tSR Asynchronous reset or preset to register Clock Enable Delays: t Width: t tGWA Gate width low (for low transparent) or M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max

Notes: 1. See “MACH Switching Test Circuits” documentation on the Lattice Data Book CD-ROM or Lattice web site. 2. Numbers in parentheses are for M5-128, M5-192, M5-256. 3. If a signal is used as both a clock and a logic array input, then the maximum input frequency applies (f MAX/2). Frequency: fMAX External feedback, PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS) 133 125 100 83.3 71.4 55.6 45.5 MHz Internal feedback, PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS +tCOSi) 182 167 125 100 83.3 62.5 50.0 MHz No feedback PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS + tHS) 200 167 167 125 100 83.3 83.3 MHz fMAXA External feedback, PAL block level. Min Internal feedback, PAL block level. Min No feedback, PAL block level. Min of 1/(tWLA + tWHA) or 1/(tSA + tHA) 167 125 125 100 83.3 71.4 62.5 MHz fMAXI Maximum input register frequency 1/(tSIRS+tHIRS) or 1/(2 x tWICW) 167 125 125 100 83.3 71.4 62.5 MHz M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max

26 MACH 5 Family

1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where

these parameters may be affected. These curves represent the typical power consumption for a particular device at system frequency. Figure 8. ICC Curves at High/Low Power Modes

Figure 9. ICC Curves at High/Low Power Modes

28 MACH 5 Family

100-PIN PQFP CONNECTION DIAGRAM Top View GND GND TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 V CC VCC GND GND I1/CLK1 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 TCK GND GND M5-128 M5LV-128* M5-128 M5LV-128* M5-192* M5-256* M5LV-256 M5-256* M5LV-256 M5-256* M5LV-256 M5-256* M5LV-256 M5-192* M5-192* M5-192* M5-128 M5LV-128* *Package obsolete, contact factory. M5-128 M5LV-128* 0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12 0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12 0A14 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A14 3A12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 2B2 2B3 2B4 2B7 2B8 2B11 2B12 2B13 2A12 2A12 2B13 2B12 2B11 2B8 2B7 2B4 2B3 2B2 2C2 2C3 2C4 2C7 2C8 2C11 2C12 2C13 2D12 0D14 0C13 0C12 0C11 0C8 0C7 0C4 0C3 0C2 1C2 1C3 1C4 1C7 1C8 1C11 1C12 1C13 1D14 GND GND TDO I/O51 I/O50 I/O49 I/O48 I/O47 I/O46 I/O45 I/O44 I/O43 I3/CLK3 GND GND V CC VCC I2/CLK2 I/O42 I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I/O35 I/O34 TMS GND GND I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 V CC GND GND V CC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 0D2 0D3 0D4 0D7 0D8 0D11 0D12 0D13 0A13 0A12 0A11 0A8 0A7 0A4 0A3 0A2 I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 V CC GND GND V CC I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 I/O53 I/O52 100 20446G-016 100-Pin PQFP (68 I/O) 3D 1 5CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations Macrocell (0-15) PAL Block (A-D) Segment (0-3)

100-PIN TQFP CONNECTION DIAGRAM – 68 I/O Top View 100-Pin TQFP (68 I/O) 100 TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 V CC GND GND I1/CLK1 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 TCK GND GND I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 NC V CC GND GND V CC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 GND GND GND GND NC I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 V CC GND GND V CC NC I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 I/O53 I/O52 GND 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 0A13 0A12 0A11 0A8 0A7 0A4 0A3 0A2 0D2 0D3 0D4 0D7 0D8 0D11 0D12 0D13 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 GND TDO I/O51 I/O50 I/O49 I/O48 I/O47 I/O46 I/O45 I/O44 I/O43 I3/CLK3 GND V CC I2/CLK2 I/O42 I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I/O35 I/O34 TMS 3A12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 M5-128 M5LV-128 M5-128 M5LV-128 M5-128 M5LV-128 M5-192 M5-256 M5LV-256* M5-256 M5LV-256* M5-256 M5LV-256* M5-256 M5LV-256* M5-192 M5-192 M5-192 M5-128 M5LV-128 2B2 2B3 2B4 2B7 2B8 2B11 2B12 2B13 2A12 2A12 2B13 2B12 2B11 2B8 2B7 2B4 2B3 2B2 2C2 2C3 2C4 2C7 2C8 2C11 2C12 2C13 2D12 0D14 0C13 0C12 0C11 0C8 0C7 0C4 0C3 0C2 1C2 1C3 1C4 1C7 1C8 1C11 1C12 1C13 1D14 0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12 0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12 0A14 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A14 *Package obsolete, contact factory. 20446G-017 3D 1 5CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations Macrocell (0-15) PAL Block (A-D) Segment (0-3)

30 MACH 5 Family

100-PIN TQFP CONNECTION DIAGRAM – 74 I/O Top View 100-Pin TQFP (74 I/O) 100 TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 V CC GND GND I1/CLK1 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 TCK GND I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 1/O27 V CC GND GND V CC I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 1/O36 GND GND I/O73 I/O72 I/O71 I/O70 I/O69 I/O68 I/O67 I/O66 I/O65 I/O64 V CC GND GND V CC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 I/O55 GND 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 0D11 0D12 3D12 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 1D11 1D12 2D12 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 0A13 0A12 0A11 0A10 0A9 0A8 0A7 0A4 0A3 0A2 0D1 0D2 0D3 0D4 0D7 0D8 0D11 0D12 0D13 1A13 1A12 1A11 1A10 1A8 1A7 1A4 1A3 1A2 1A1 1D2 1D3 1D4 1D7 1D8 1D10 1D11 1D12 1D13 GND TDO I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I/O47 I/O46 I3/CLK3 GND V CC I2/CLK2 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I/O39 I/O38 I/O37 TMS 3A12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 M5LV-256 M5LV-128M5LV-128 M5LV-128M5LV-128 M5LV-256 M5LV-256 M5LV-256 2B2 2B3 2B4 2B7 2B8 2B11 2B12 2B13 2A12 0D14 0C13 0C12 0C11 0C8 0C7 0C4 0C3 0C2 1C2 1C3 1C4 1C7 1C8 1C11 1C12 1C13 1D14 0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12 0A14 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A14 20446G-018 3D 1 5CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations Macrocell (0-15) PAL Block (A-D) Segment (0-3)

144-PIN PQFP CONNECTION DIAGRAM Top View 144-Pin PQFP TDI I/O0 I/O1 I/O2 I/O3 I/O4 GND I/O5 I/O6 I/O7 I/O8 GND I/O9 I/O10 I/O11 I/O12 I0/CLK0 V CC GND I1/CLK1 I/O13 I/O14 I/O15 I/O16 GND I/O17 I/O18 I/O19 I/O20 GND I/O21 I/O22 I/O23 I/O24 I/O25 TCK 0A8 0A9 0A10 0A11 0A12 0B13 0B12 0B11 0B8 0B5 0B4 0B3 0B2 1B2 1B3 1B4 1B5 1B8 1B11 1B12 1B13 1A12 1A11 1A10 1A9 1A8 0A12 0A13 0A14 0B13 0B12 0B11 0B8 0B5 0B4 0B3 0B2 0B1 0B0 1B0 1B1 1B2 1B3 1B4 1B5 1B8 1B11 1B12 1B13 1A14 1A13 1A12 0A14 0B13 0B12 0B11 0B10 0B8 0B7 0B6 0B5 0B4 0B3 0B2 0B1 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B10 1B11 1B12 1B13 1A14 M5-128 M5LV-128* M5-256* M5LV-256* M5-256* M5LV-256* M5-256* M5LV-256* M5-256* M5LV-256* M5-192* M5-192* M5-192* M5-192* M5-128 M5LV-128* M5-128 M5LV-128* M5-128 M5LV-128* GND V CC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 GND I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 V CC GND GND V CC I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 GND I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 V CC GND 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1D3 1D4 1D7 1D8 1D11 1D12 2D12 2D11 2D8 2D7 2D4 2D3 2A1 2A2 2A3 2A4 2A5 2A6 2A7 1A11 1A10 1A8 1A7 1A6 1A5 1A4 1A3 1A2 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D10 2D11 1A13 1A12 1A11 1A10 1A8 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D10 1D11 1D12 1D13 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 GND V CC I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 GND I/O96 I/O95 I/O94 I/O93 I/O92 I/O91 V CC GND GND V CC I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 GND I/O84 I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 V CC GND 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0D3 0D4 0D7 0D8 0D11 0D12 3D12 3D11 3D8 3D7 3D4 3D3 3A1 3A2 3A3 3A4 3A5 3A6 3A7 0A11 0A10 0A8 0A7 0A6 0A5 0A4 0A3 0A2 0D2 0D3 0D4 0D7 0D8 0D11 0D12 0D13 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A10 2A11 0A13 0A12 0A11 A10 0A8 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D10 0D11 0D12 0D13 108 107 106 105 104 103 102 101 100 TDO I/O77 I/O76 I/O75 I/O74 I/O73 GND I/O72 I/O71 I/O70 I/O69 GND I/O68 I/O67 I/O66 I/O65 I3/CLK3 GND V CC I2/CLK2 I/O64 I/O63 I/O62 I/O61 GND I/O60 I/O59 I/O58 I/O57 GND I/O56 I/O55 I/O54 I/O53 I/O52 TMS 3A8 3A9 3A10 3A11 3A12 3B13 3B12 3B11 3B8 3B5 3B4 3B3 3B2 2B2 2B3 2B4 2B5 2B8 2B11 2B12 2B13 2A12 2A11 2A10 2A9 2A8 2A12 2A13 2A14 2B13 2B12 2B11 2B8 2B5 2B4 2B3 2B2 2B1 2B0 2C0 2C1 2C2 2C3 2C4 2C5 2C8 2C11 2C12 2C13 2D14 2D13 2D12 0D14 0C13 0C12 0C11 0C10 0C8 0C7 0C6 0C5 0C4 0C3 0C2 0C1 1C1 1C2 1C3 1C4 1C5 1C6 1C7 1C8 1C10 1C11 1C12 1C13 1D14 *Package obsolete, contact factory. 20446G-019 3D 1 5CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations Macrocell (0-15) PAL Block (A-D) Segment (0-3)

32 MACH 5 Family

144-PIN TQFP CONNECTION DIAGRAM Top View 144-Pin TQFP TDI I/O0 I/O1 I/O2 I/O3 I/O4 GND I/O5 I/O6 I/O7 I/O8 GND I/O9 I/O10 I/O11 I/O12 I0/CLK0 V CC GND I1/CLK1 I/O13 I/O14 I/O15 I/O16 GND I/O17 I/O18 I/O19 I/O20 GND I/O21 I/O22 I/O23 I/O24 I/O25 TCK 0A8 0A9 0A10 0A11 0A12 0B13 0B12 0B11 0B8 0B5 0B4 0B3 0B2 1B2 1B3 1B4 1B5 1B8 1B11 1B12 1B13 1A12 1A11 1A10 1A9 1A8 0A14 0B13 0B12 0B11 0B10 0B8 0B7 0B6 0B5 0B4 0B3 0B2 0B1 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B10 1B11 1B12 1B13 1A14 M5LV-128 M5LV-256 M5LV-256 M5LV-256 M5LV-256 M5LV-128 M5LV-128 M5LV-128 GND V CC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 GND I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 V CC GND GND V CC I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 GND I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 V CC GND 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1D3 1D4 1D7 1D8 1D11 1D12 2D12 2D11 2D8 2D7 2D4 2D3 2A1 2A2 2A3 2A4 2A5 2A6 2A7 1A13 1A12 1A11 1A10 1A8 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D10 1D11 1D12 1D13 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 GND V CC I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 GND I/O96 I/O95 I/O94 I/O93 I/O92 I/O91 V CC GND GND V CC I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 GND I/O84 I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 V CC GND 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0D3 0D4 0D7 0D8 0D11 0D12 3D12 3D11 3D8 3D7 3D4 3D3 3A1 3A2 3A3 3A4 3A5 3A6 3A7 0A13 0A12 0A11 A10 0A8 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D10 0D11 0D12 0D13 108 107 106 105 104 103 102 101 100 TDO I/O77 I/O76 I/O75 I/O74 I/O73 GND I/O72 I/O71 I/O70 I/O69 GND I/O68 I/O67 I/O66 I/O65 I3/CLK3 GND V CC I2/CLK2 I/O64 I/O63 I/O62 I/O61 GND I/O60 I/O59 I/O58 I/O57 GND I/O56 I/O55 I/O54 I/O53 I/O52 TMS 3A8 3A9 3A10 3A11 3A12 3B13 3B12 3B11 3B8 3B5 3B4 3B3 3B2 2B2 2B3 2B4 2B5 2B8 2B11 2B12 2B13 2A12 2A11 2A10 2A9 2A8 0D14 0C13 0C12 0C11 0C10 0C8 0C7 0C6 0C5 0C4 0C3 0C2 0C1 1C1 1C2 1C3 1C4 1C5 1C6 1C7 1C8 1C10 1C11 1C12 1C13 1D14 20446G-020 3D 1 5CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations Macrocell (0-15) PAL Block (A-D) Segment (0-3)

160-PIN PQFP CONNECTION DIAGRAM Top View 160-Pin PQFP (128, 192, 256 Macrocells) TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 V CC GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 TCK 0A8 0A9 0A10 0A11 0A12 0A13 0A14 0A15 0B13 0B12 0B11 0B8 0B5 0B4 0B3 0B2 1B2 1B3 1B4 1B5 1B8 1B11 1B12 1B13 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8 0A12 0A13 0A14 0A15 0B15 0B14 0B13 0B12 0B11 0B8 0B5 0B4 0B3 0B2 0B1 0B0 1B0 1B1 1B2 1B3 1B4 1B5 1B8 1B11 1B12 1B13 1B14 1B15 1A15 1A14 1A13 1A12 0A14 0A15 0B14 0B13 0B12 0B11 0B10 0B9 0B8 0B7 0B6 0B5 0B4 0B3 0B2 0B1 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 1B11 1B12 1B13 1B14 1A15 1A14 GND V CC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND V CC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 V CC GND GND V CC I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 V CC GND I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 V CC GND 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 1D3 1D4 1D7 1D8 1D11 1D12 2D12 2D11 2D8 2D7 2D4 2D3 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 1A11 1A10 1A9 1A8 1A7 1A6 1A5 1A4 1A3 1A2 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 2D10 2D11 1A13 1A12 1A11 1A10 1A9 1A8 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1D10 1D11 1D12 1D13 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 GND V CC I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND V CC I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 V CC GND GND V CC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 V CC GND I/O99 I/O98 I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 V CC GND 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 0D3 0D4 0D7 0D8 0D11 0D12 3D12 3D11 3D8 3D7 3D4 3D3 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 0A11 0A10 0A9 0A8 0A7 0A6 0A5 0A4 0A3 0A2 0D2 0D3 0D4 0D7 0D8 0D11 0D12 0D13 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 0A13 0A12 0A11 0A10 0A9 0A8 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 0D10 0D11 0D12 0D13 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 TDO I/O91 I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 GND I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 I/O77 I/O76 I3/CLK3 GND V CC I2/CLK2 I/O75 I/O74 I/O73 I/O72 I/O71 I/O70 I/O69 I/O68 GND I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 TMS 3A8 3A9 3A10 3A11 3A12 3A13 3A14 3A15 3B13 3B12 3B11 3B8 3B5 3B4 3B3 3B2 2B2 2B3 2B4 2B5 2B8 2B11 2B12 2B13 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 M5-128 M5LV-128 M5-128 M5LV-128 M5-128 M5LV-128 M5-256 M5LV-256 M5-256 M5LV-256 M5-256 M5LV-256 M5-256 M5LV-256 M5-192 M5-192 M5-192 M5-192 M5-128 M5LV-128 2A12 2A13 2A14 2A15 2B15 2B14 2B13 2B12 2B11 2B8 2B5 2B4 2B3 2B2 2B1 2B0 2C0 2C1 2C2 2C3 2C4 2C5 2C8 2C11 2C12 2C13 2C14 2C15 2D15 2D14 2D13 2D12 0D14 0D15 0C14 0C13 0C12 0C11 0C10 0C9 0C8 0C7 0C6 0C5 0C4 0C3 0C2 0C1 1C1 1C2 1C3 1C4 1C5 1C6 1C7 1C8 1C9 1C10 1C11 1C12 1C13 1C14 1D15 1D14 20446G-021 3D 1 5CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations Macrocell (0-15) PAL Block (A-D) Segment (0-3)

34 MACH 5 Family

160-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAM Top View 160-Pin PQFP (320, 384, 512 Macrocells) TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 V CC GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 TCK 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D13 0D12 0D11 0D8 0D7 0D4 0D3 0D2 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D13 0D12 0D11 0D8 0D7 0D4 0D3 0D2 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D13 0D12 0D11 0D8 0D7 0D4 0D3 0D2 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8 GND V CC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND V CC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 V CC GND GND V CC I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 V CC GND I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 V CC GND 2A13 2A12 2A11 2A8 2A7 2A4 2A3 2A2 2B3 2B4 2B7 2B8 2B11 2B12 3B12 3B11 3B8 3B7 3B4 3B3 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 2A12 2A11 2A8 2A7 2A4 2A3 2B3 2B4 2B7 2B8 2B11 2B12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 1B3 1B4 1B7 1B8 1B11 1B12 2B12 2B11 2B8 2B7 2B4 2B3 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 GND V CC I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND V CC I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 V CC GND GND V CC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 V CC GND I/O99 I/O98 I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 V CC GND 7A13 7A12 7A11 7A8 7A7 7A4 7A3 7A2 7B3 7B4 7B7 7B8 7B11 7B12 6B12 6B11 6B8 6B7 6B4 6B3 6A2 6A3 6A4 6A7 6A8 6A11 6A12 6A13 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 5A12 5A11 5A8 5A7 5A4 5A3 5B3 5B4 5B7 5B8 5B11 5B12 4B13 4B12 4B11 4B8 4B7 4B4 4B3 4B2 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 4A12 4A11 4A8 4A7 4A4 4A3 4B3 4B4 4B7 4B8 4B11 4B12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 TDO I/O91 I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 GND I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 I/O77 I/O76 I3/CLK3 GND V CC I2/CLK2 I/O75 I/O74 I/O73 I/O72 I/O71 I/O70 I/O69 I/O68 GND I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 TMS 5A2 5A3 5A4 5A7 5A8 5A11 5A12 5A13 5D13 5D12 5D11 5D8 5D7 5D4 5D3 5D2 4D2 4D3 4D4 4D7 4D8 4D11 4D12 4D13 4A13 4A12 4A11 4A8 4A7 4A4 4A3 4A2 M5-320* M5LV-320 M5-384* M5LV-384 M5-384* M5LV-384 M5-384* M5LV-384 M5-384* M5LV-384 M5-512* M5LV-512 M5-512* M5LV-512 M5-512* M5LV-512 M5-512* M5LV-512 M5-320* M5LV-320 M5-320* M5LV-320 M5-320* M5LV-320 4A2 4A3 4A4 4A7 4A8 4A11 4A12 4A13 4D13 4D12 4D11 4D8 4D7 4D4 4D3 4D2 3D2 3D3 3D4 3D7 3D8 3D11 3D12 3D13 3A13 3A12 3A11 3A8 3A7 3A4 3A3 3A2 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 3D13 3D12 3D11 3D8 3D7 3D4 3D3 3D2 2D2 2D3 2D4 2D7 2D8 2D11 2D12 2D13 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 *Package obsolete, contact factory. 20446G-022 7D 1 5CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations Macrocell (0-15) PAL Block (A-D) Segment (0-7)

208-PIN PQFP CONNECTION DIAGRAM Top View 208-Pin PQFP (192, 256 Macrocells) TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 V CC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I0/CLK0 V CC GND I1/CLK1 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND V CC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 TCK 0A8 0A9 0A10 0A11 0A12 0A13 0A14 0A15 0B13 0B12 0B11 0B10 0B9 0B8 0B7 0B6 0B5 0B4 0B3 0B2 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 1B11 1B12 1B13 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8 TDO I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 V CC GND I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 GND I/O103 I/O102 I/O101 I/O100 I3/CLK3 GND V CC I2/CLK2 I/O99 I/O98 I/O97 I/O96 GND I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND V CC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 TMS 3A8 3A9 3A10 3A11 2A12 3A13 3A14 3A15 3B13 3B12 3B11 3B10 3B9 3B8 3B7 3B6 3B5 3B4 3B3 3B2 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12 2B13 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 M5-256 M5LV-256 M5-256 M5LV-256 M5-256 M5LV-256 M5-256 M5LV-256 100 101 102 103 104 GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 GND V CC I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND I/O56 I/O57 I/O58 I/O59 V CC GND GND V CC I/O60 I/O61 I/O62 I/O63 GND I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 V CC GND I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 GND 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1D10 1D11 1D12 1D13 2D13 2D12 2D11 2D10 2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 GND I/O159 I/O158 I/O157 I/O156 I/O155 I/O154 I/O153 I/O152 GND V CC I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 I/O145 I/O144 GND I/O143 I/O142 I/O141 I/O140 V CC GND GND V CC I/O139 I/O138 I/O137 I/O136 GND I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 I/O129 I/O128 V CC GND I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 GND 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 0D10 0D11 0D12 0D13 3D13 3D12 3D11 3D10 3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 20446G-023 3D 1 5CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations Macrocell (0-15) PAL Block (A-D) Segment (0-3)

36 MACH 5 Family

208-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAM Top View 208-Pin PQFP (320, 384, 512 Macrocells) TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 V CC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I0/CLK0 V CC GND I1/CLK1 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND V CC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 TCK 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D7 0D4 0D3 0D2 1D2 1D3 1D4 1D7 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D7 0D4 0D3 0D2 1D2 1D3 1D4 1D7 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D7 0D4 0D3 0D2 1D2 1D3 1D4 1D7 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8 TDO I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 V CC GND I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 GND I/O103 I/O102 I/O101 I/O100 I3/CLK3 GND V CC I2/CLK2 I/O99 I/O98 I/O97 I/O96 GND I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND V CC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 TMS 5A2 5A3 5A4 5A7 5A8 5A11 5A12 5A13 5D15 5D14 5D13 5D12 5D11 5D10 5D9 5D8 5D7 5D4 5D3 5D2 4D2 4D3 4D4 4D7 4D8 4D9 4D10 4D11 4D12 4D13 4D14 4D15 4A13 4A12 4A11 4A8 4A7 4A4 4A3 4A2 4A2 4A3 4A4 4A7 4A8 4A11 4A12 4A13 4D15 4D14 4D13 4D12 4D11 4D10 4D9 4D8 4D7 4D4 4D3 4D2 3D2 3D3 3D4 3D7 3D8 3D9 3D10 3D11 3D12 3D13 3D14 3D15 3A13 3A12 3A11 3A8 3A7 3A4 3A3 3A2 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 3D15 3D14 3D13 3D12 3D11 3D10 3D9 3D8 3D7 3D4 3D3 3D2 2D2 2D3 2D4 2D7 2D8 2D9 2D10 2D11 2D12 2D13 2D14 2D15 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 M5-384 M5LV-384 M5-384 M5LV-384 M5-384 M5LV-384 M5-384 M5LV-384 M5-320 M5LV-320 M5-320 M5LV-320 M5-320 M5LV-320 M5-320 M5LV-320 M5-512 M5LV-512 M5-512 M5LV-512 M5-512 M5LV-512 M5-512 M5LV-512 100 101 102 103 104 GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 GND V CC I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND I/O56 I/O57 I/O58 I/O59 V CC GND GND V CC I/O60 I/O61 I/O62 I/O63 GND I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 V CC GND I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 GND 2A13 2A12 2A11 2A8 2A7 2A4 2A3 2A2 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B11 2B12 2B13 3B13 3B12 3B11 3B8 3B7 3B6 3B5 3B4 3B3 3B2 3B1 3B0 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 2A7 2A4 2A3 2A2 2B2 2B3 2B4 2B7 2B8 2B9 2B10 2B11 2B12 2B13 2B14 2B15 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B11 1B12 1B13 2B13 2B12 2B11 2B8 2B7 2B6 2B5 2B4 2B3 2B2 2B1 2B0 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 GND I/O159 I/O158 I/O157 I/O156 I/O155 I/O154 I/O153 I/O152 GND V CC I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 I/O145 I/O144 GND I/O143 I/O142 I/O141 I/O140 V CC GND GND V CC I/O139 I/O138 I/O137 I/O136 GND I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 I/O129 I/O128 V CC GND I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 GND 7A13 7A12 7A11 7A8 7A7 7A4 7A3 7A2 7B0 7B1 7B2 7B3 7B4 7B5 7B6 7B7 7B8 7B11 7B12 7B13 6B13 6B12 6B11 6B8 6B7 6B6 6B5 6B4 6B3 6B2 6B1 6B0 6A2 6A3 6A4 6A7 6A8 6A11 6A12 6A13 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 5A15 5A14 5A13 5A12 5A11 5A10 5A9 5A8 5A7 5A4 5A3 5A2 5B2 5B3 5B4 5B7 5B8 5B9 5B10 5B11 5B12 5B13 5B14 5B15 4B13 4B12 4B11 4B8 4B7 4B4 4B3 4B2 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 4A15 4A14 4A13 4A12 4A11 4A10 4A9 4A8 4A7 4A4 4A3 4A2 4B2 4B3 4B4 4B7 4B8 4B9 4B10 4B11 4B12 4B13 4B14 4B15 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 20446G-024 7D 1 5CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations Macrocell (0-15) PAL Block (A-D) Segment (0-7)

240-PIN PQFP CONNECTION DIAGRAM Top View 240-Pin PQFP 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 V CC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I0/CLK0 V CC GND I1/CLK1 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND V CC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 TCK 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D7 0D6 0D5 0D4 0D3 0D2 0D1 0D0 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D7 0D6 0D5 0D4 0D3 0D2 0D1 0D0 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D7 0D6 0D5 0D4 0D3 0D2 0D1 0D0 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8 TDO I/O139 I/O138 I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 V CC GND I/O131 I/O130 I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 GND I/O123 I/O122 I/O121 I/O120 I/O119 I/O118 I/O117 I/O116 I3/CLK3 GND V CC I2/CLK2 I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 GND I/O107 I/O106 I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 GND V CC I/O99 I/O98 I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 TMS 5A2 5A3 5A4 5A7 5A8 5A11 5A12 5A13 5D15 5D14 5D13 5D12 5D11 5D10 5D9 5D8 5D7 5D6 5D5 5D4 5D3 5D2 5D1 5D0 4D0 4D1 4D2 4D3 4D4 4D5 4D6 4D7 4D8 4D9 4D10 4D11 4D12 4D13 4D14 4D15 4A13 4A12 4A11 4A8 4A7 4A4 4A3 4A2 4A2 4A3 4A4 4A7 4A8 4A11 4A12 4A13 4D15 4D14 4D13 4D12 4D11 4D10 4D9 4D8 4D7 4D6 4D5 4D4 4D3 4D2 4D1 4D0 3D0 3D1 3D2 3D3 3D4 3D5 3D6 3D7 3D8 3D9 3D10 3D11 3D12 3D13 3D14 3D15 3A13 3A12 3A11 3A8 3A7 3A4 3A3 3A2 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 3D15 3D14 3D13 3D12 3D11 3D10 3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3D1 3D0 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 2D10 2D11 2D12 2D13 2D14 2D15 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 M5-320* M5LV-320* M5-320* M5LV-320* M5-320* M5LV-320* M5-320* M5LV-320* M5-384* M5LV-384* M5-384* M5LV-384* M5-384* M5LV-384* M5-384* M5LV-384* M5-512* M5LV-512* M5-512* M5LV-512* M5-512* M5LV-512* M5-512* M5LV-512* GND VCC I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND V CC I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 GND I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 V CC GND GND GND GND V CC I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 GND I/O76 I/O77 I/O78 I/O79 I/O80 I/O81 I/O82 I/O83 V CC GND I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 I/O90 I/O91 V CC GND 2A13 2A12 2A11 2A8 2A7 2A4 2A3 2A2 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12 2B13 3B13 3B12 3B11 3B10 3B9 3B8 3B7 3B6 3B5 3B4 3B3 3B2 3B1 3B0 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 2A7 2A6 2A5 2A4 2A3 2A2 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12 2B13 2B14 2B15 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 1B11 1B12 1B13 2B13 2B12 2B11 2B10 2B9 2B8 2B7 2B6 2B5 2B4 2B3 2B2 2B1 2B0 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 GND V CC I/O183 I/O182 I/O181 I/O180 I/O179 I/O178 I/O177 I/O176 GND V CC I/O175 I/O174 I/O173 I/O172 I/O171 I/O170 I/O169 I/O168 GND I/O167 I/O166 I/O165 I/O164 I/O163 I/O162 V CC GND GND GND GND V CC I/O161 I/O160 I/O159 I/O158 I/O157 I/O156 GND I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 V CC GND I/O147 I/O146 I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 V CC GND 7A13 7A12 7A11 7A8 7A7 7A4 7A3 7A2 7B0 7B1 7B2 7B3 7B4 7B5 7B6 7B7 7B8 7B9 7B10 7B11 7B12 7B13 6B13 6B12 6B11 6B10 9B9 6B8 6B7 6B6 6B5 6B4 6B3 6B2 6B1 6B0 6A2 6A3 6A4 6A7 6A8 6A11 6A12 6A13 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 5A15 5A14 5A13 5A12 5A11 5A10 5A9 5A8 5A7 5A6 5A5 5A4 5A3 5A2 5B2 5B3 5B4 5B5 5B6 5B7 5B8 5B9 5B10 5B11 5B12 5B13 5B14 5B15 4B13 4B12 4B11 4B8 4B7 4B4 4B3 4B2 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 4A15 4A14 4A13 4A12 4A11 4A10 4A9 4A8 4A7 4A6 4A5 4A4 4A3 4A2 4B2 4B3 4B4 4B5 4B6 4B7 4B8 4B9 4B10 4B11 4B12 4B13 4B14 4B15 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 155 184 183 182 181 *Package obsolete, contact factory. 20446G-025 7D 1 5CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations Macrocell (0-15) PAL Block (A-D) Segment (0-7)

38 MACH 5 Family

256-BALL BGA CONNECTION DIAGRAM — Bottom View (I/O Pin-outs) 256-Ball BGA 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 A GND I/O11 GND I/O44 I/O58 GND I/O70 I/O76 GND GND GND GND I/O108 I/O116 GND I/O128 I/O134 GND GND GND A B GND I/O12 I/O28 I/O45 I/O59 I/O64 I/O71 I/O77 I/O84 I/O90 I/O96 I/O102 I/O109 I/O117 I/O122 I/O129 I/O135 I/O148 I/O164 GNDB C I/O0 I/O13 V CC I/O46 I/O60 I/O65 I/O72 I/O78 I/O85 I/O91 I/O97 I/O103 I/O110 I/O118 I/O123 I/O130 I/O136 VCC I/O165 I/O181C D I/O1 I/O14 I/O29 V CC VCC I/O66 V CC I/O79 I/O86 I/O92 I/O98 I/O104 I/O111 VCC I/O124 VCC VCC I/O149 I/O166 I/O182D E I/O2 I/O15 I/O30 TDI TDO I/O150 I/O167 I/O183E F GND I/O16 I/O31 I/O47 I/O137 I/O151 I/O168 GND F G I/O3 I/O17 I/O32 V CC VCC I/O152 I/O169 I/O184G H GND I/O18 I/O33 I/O48 I/O138 I/O153 I/O170 GND H J I/O4 I/O19 I/O34 I/O49 I/O139 I/O154 I/O171 I/O185J K GND IO/CLK0 I/O35 I/O50 I/O140 I/O155I3/CLK3 I/O186 K L I/O5 I1/CLK1 I/O36 I/O51 I/O141 I/O156I2/CLK2 GND L M I/O6 I/O20 I/O37 I/O52 I/O142 I/O157 I/O172 I/O187M N GND I/O21 I/O38 I/O53 I/O143 I/O158 I/O173 GND N P I/O7 I/O22 I/O39 V CC VCC I/O159 I/O174 I/O188P R GND I/O23 I/O40 I/O54 I/O144 I/O160 I/O175 GND R T I/O8 I/O24 I/O41 TCK TMS I/O161 I/O176 I/O189T U I/O9 I/O25 I/O42 V CC VCC I/O67 V CC I/O80 I/O87 I/O93 I/O99 I/O105 I/O112 VCC I/O125 VCC VCC I/O162 I/O177 I/O190U V I/O10 I/O26 V CC I/O55 I/O61 I/O68 I/O73 I/O81 I/O88 I/O94 I/O100 I/O106 I/O113 I/O119 I/O126 I/O131 I/O145 VCC I/O178 I/O191V W GND I/O27 I/O43 I/O56 I/O62 I/O69 I/O74 I/O82 I/O89 I/O95 I/O101 I/O107 I/O114 I/O120 I/O127 I/O132 I/O146 I/O163 I/O179 GNDW Y GND GND GND I/O57 I/O63 GND I/O75 I/O83 GND GND GND GND I/O115 I/O121 GND I/O133 I/O147 GND I/O180 GND Y 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 20446G-026 CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations *Package obsolete, contact factory.

256-BALL BGA CONNECTION DIAGRAM — M5-320, M5LV-320* Bottom View (Macrocell Association) 256-Ball BGA 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 A GND 0B2 GND 0B13 4A14 GND 4A8 4A4 GND GND GND GND 4B4 4B8 GND 4B14 3B13 GND GND GND A B GND 0A3 0B8 0B11 4A15 4A11 4A10 4A6 4A3 4A0 4B0 4B3 4B6 4B10 4B11 4B15 3B11 3B8 3B2 GND B C 0D15 0A8 V CC 0B3 0B4 0B12 4A13 4A9 4A5 4A1 4B1 4B5 4B9 4B13 3B12 3B4 3B3 V CC 3A3 3A11 C D 0D13 0A11 0A2 V CC VCC 0B7 V CC 4A12 4A7 4A2 4B2 4B7 4B12 V CC 3B7 V CC VCC 3A2 3A8 3D15 D E 0D10 0A13 0A4 TDI TDO 3A4 3A13 3D12 E F GND 0D12 0A12 0A7 3A7 3A12 3D13 GND F G 0D7 0D8 0D14 V CC VCC 3D14 3D9 3D7 G H GND 0D4 0D9 0D11 3D11 3D10 3D8 GND H J 0D2 0D3 0D5 0D6 3D6 3D5 3D4 3D3 J K GND IO/CLK0 0D0 0D1 3D1 3D0 I3/CLK3 3D2 K L 1D2 I1/CLK1 1D0 1D1 2D1 2D0 I2/CLK2 GND L M 1D3 1D4 1D5 1D6 2D6 2D5 2D3 2D2 M N GND 1D8 1D10 1D11 2D11 2D9 2D4 GND N P 1D7 1D9 1D14 V CC VCC 2D14 2D8 2D7 P R GND 1D13 1A14 1A11 2A11 2A14 2D12 GND R T 1D12 1A15 1A10 TCK TMS 2A10 2A15 2D10 T U 1D15 1A12 1A8 V CC VCC 1A4 V CC 1B3 1B8 1B13 2B13 2B8 2B3 V CC 2A4 V CC VCC 2A8 2A13 2D13 U V 1A13 1A9 V CC 1A6 1A5 1A1 1B2 1B6 1B10 1B14 2B14 2B10 2B6 2B2 2A1 2A5 2A6 V CC 2A12 2D15 V W GND 1A7 1A3 1A2 1B0 1B4 1B5 1B9 1B12 1B15 2B15 2B12 2B9 2B5 2B4 2B0 2A2 2A3 2A9 GND W Y GND GND GND 1A0 1B1 GND 1B7 1B11 GND GND GND GND 2B11 2B7 GND 2B1 2A0 GND 2A7 GND Y 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 20446G-029 CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations 4D 1 5 Macrocell (0-15) PAL Block (A-D) Segment (0-4) *Package obsolete, contact factory.

40 MACH 5 Family

256-BALL BGA CONNECTION DIAGRAM — M5-384*, M5LV-384* Bottom View (Macrocell Association) 256-Ball BGA 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 A GND 0B2 GND 0B13 5A14 GND 5A8 5A4 GND GND GND GND 5B4 5B8 GND 5B14 4B13 GND GND GND A B GND 0A3 0B8 0B11 5A15 5A11 5A10 5A6 5A3 5A0 5B0 5B3 5B6 5B10 5B11 5B15 4B11 4B8 4B2 GND B C 0D15 0A8 V CC 0B3 0B4 0B12 5A13 5A9 5A5 5A1 5B1 5B5 5B9 5B13 4B12 4B4 4B3 V CC 4A3 4A11 C D 0D13 0A11 0A2 V CC VCC 0B7 V CC 5A12 5A7 5A2 5B2 5B7 5B12 V CC 4B7 V CC VCC 4A2 4A8 4D15 D E 0D10 0A13 0A4 TDI TDO 4A4 4A13 4D12 E F GND 0D12 0A12 0A7 4A7 4A12 4D13 GND F G 0D7 0D8 0D14 V CC VCC 4D14 4D9 4D7 G H GND 0D4 0D9 0D11 4D11 4D10 4D8 GND H J 0D2 0D3 0D5 0D6 4D6 4D5 4D4 4D3 J K GND IO/CLK0 0D0 0D1 4D1 4D0 I3/CLK3 4D2 K L 1D2 I1/CLK1 1D0 1D1 3D1 3D0 I2/CLK2 GND L M 1D3 1D4 1D5 1D6 3D6 3D5 3D3 3D2 M N GND 1D8 1D10 1D11 3D11 3D9 3D4 GND N P 1D7 1D9 1D14 V CC VCC 3D14 3D8 3D7 P R GND 1D13 1A12 1A7 3A7 3A12 3D12 GND R T 1D12 1A13 1A4 TCK TMS 3A4 3A13 3D10 T U 1D15 1A8 1A2 V CC VCC 1B7 V CC 2A12 2A7 2A2 2B2 2B7 2B12 V CC 3B7 V CC VCC 3A2 3A11 3D13 U V 1A11 1A3 V CC 1B3 1B4 1B12 2A13 2A9 2A5 2A1 2B1 2B5 2B9 2B13 3B12 3B4 3B3 V CC 3A8 3D15 V W GND 1B2 1B8 1B11 2A15 2A11 2A10 2A6 2A3 2A0 2B0 2B3 2B6 2B10 2B11 2B15 3B11 3B8 3A3 GND W Y GND GND GND 1B13 2A14 GND 2A8 2A4 GND GND GND GND 2B4 2B8 GND 2B14 3B13 GND 3B2 GND Y 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 20446G-028 CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations 5D 1 5 Macrocell (0-15) PAL Block (A-D) Segment (0-5) *Package obsolete, contact factory.

256-BALL BGA CONNECTION DIAGRAM — M5-512*, M5LV-512* Bottom View (Macrocell Association) 256-Ball BGA 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 A GND 7A13 GND 7A2 7B1 GND 7B7 7B11 GND GND GND GND 6B11 6B7 GND 6B1 6A2 GND GND GND A B GND 0A3 7A7 7A4 7B0 7B4 7B5 7B9 7B12 7B15 6B15 6B12 6B9 6B5 6B4 6B0 6A4 6A7 6A13 GND B C 0D15 0A8 V CC 7A12 7A11 7A3 7B2 7B6 7B10 7B14 6B14 6B10 6B6 6B2 6A3 6A11 6A12 V CC 5A3 5A11 C D 0D13 0A11 0A2 V CC VCC 7A8 V CC 7B3 7B8 7B13 6B13 6B8 6B3 V CC 6A8 V CC VCC 5A2 5A8 5D15 D E 0D10 0A13 0A4 TDI TDO 5A4 5A13 5D12 E F GND 0D12 0A12 0A7 5A7 5A12 5D13 GND F G 0D7 0D8 0D14 V CC VCC 5D14 5D9 5D7 G H GND 0D4 0D9 0D11 5D11 5D10 5D8 GND H J 0D2 0D3 0D5 0D6 5D6 5D5 5D4 5D3 J K GND IO/CLK0 0D0 0D1 5D1 5D0 I3/CLK3 5D2 K L 1D2 I1/CLK1 1D0 1D1 4D1 4D0 I2/CLK2 GND L M 1D3 1D4 1D5 1D6 4D6 4D5 4D3 4D2 M N GND 1D8 1D10 1D11 4D11 4D9 4D4 GND N P 1D7 1D9 1D14 V CC VCC 4D14 4D8 4D7 P R GND 1D13 1A12 1A7 4A7 4A12 4D12 GND R T 1D12 1A13 1A4 TCK TMS 4A4 4A13 4D10 T U 1D15 1A8 1A2 V CC VCC 2A8 V CC 2B3 2B8 2B13 3B13 3B8 3B3 V CC 3A8 V CC VCC 4A2 4A11 4D13 U V 1A11 1A3 V CC 2A12 2A11 2A3 2B2 2B6 2B10 2B14 3B14 3B10 3B6 3B2 3A3 3A11 3A12 V CC 4A8 4D15 V W GND 2A13 2A7 2A4 2B0 2B4 2B5 2B9 2B12 2B15 3B15 3B12 3B9 3B5 3B4 3B0 3A4 3A7 4A3 GND W Y GND GND GND 2A2 2B1 GND 2B7 2B11 GND GND GND GND 3B11 3B7 GND 3B1 3A2 GND 3A13 GND Y 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 20446G-027 CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations 5D 1 5 Macrocell (0-15) PAL Block (A-D) Segment (0-5) *Package obsolete, contact factory.

42 MACH 5 Family

352-BALL BGA CONNECTION DIAGRAM — M5-512, M5LV-512 Bottom View (I/O Pin-outs) 352-Ball BGA 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 A NC GND NC I/O51 GND I/O73 I/O80 I/O87 GND I/O101 NC I/O114 GND I/O128 I/O134 I/O142 GND I/O156 I/O162 GND NC GND NC GND NC NC A B NC GND NC I/O52 I/O68 I/O74 I/O81 I/O88 I/O95 I/O102 I/O107 I/O115 I/O122 I/O129 I/O135 I/O143 I/O150 I/O157 I/O163 I/O169 I/O176 I/O183 I/O188 GND NC N C B C GND I/O11 TDI I/O53 I/O69 I/O75 I/O82 I/O89 I/O96 I/O103 I/O108 I/O116 I/O123 I/O130 I/O136 I/O144 I/O151 I/O158 I/O164 I/O170 I/O177 I/O184 NC NC NC NC C D I/O0 I/O12 I/O32 V CC I/O70 I/O76 I/O83 I/O90 V CC I/O104 I/O109 I/O117 VCC I/O131 I/O137 I/O145 VCC I/O159 I/O165 I/O171 I/O178 VCC TDO I/O205 I/O224 GND D E NC I/O13 I/O33 I/O54 I/O189 I/O206 I/O225 NC E F GND I/O14 I/O34 I/O55 I/O190 I/O207 I/O226 I/O245F G I/O1 I/O15 I/O35 V CC I/O191 I/O208 I/O227 GND G H I/O2 I/O16 I/O36 I/O56 VCC I/O209 I/O228 I/O246H J GND I/O17 I/O37 V CC I/O192 I/O210 I/O229 I/O247J K I/O3 I/O18 I/O38 I/O57 VCC I/O211 I/O230 GND K L I/O4 I/O19 I/O39 I/O58 I/O193 I/O212 I/O231 I/O248L M I/O5 I/O20 I/O40 I/O59 I/O194 I/O213 I/O232 I/O249M N GND I/O21 I0/CLK0 VCC I/O195 I/O214 I/O233I3/CLK3 N P I1/CLK1 I/O22 I/O41 I/O60 VCC I2CLK2 I/O234 GND P R I/O6 I/O23 I/O42 I/O61 I/O196 I/O215 I/O235 I/O250R T I/O7 I/O24 I/O43 I/O62 I/O197 I/O216 I/O236 I/O251T U GND I/O25 I/O44 V CC I/O198 I/O217 I/O237 I/O252U V I/O8 I/O26 I/O45 I/O63 VCC I/O218 I/O238 GND V W I/O9 I/O27 I/O46 V CC I/O199 I/O219 I/O239 I/O253W Y GND I/O28 I/O47 I/O64 VCC I/O220 I/O240 I/O254Y A I/O10 I/O29 I/O48 I/O65 I/O200 I/O221 I/O241 GND AA B NC I/O30 I/O49 I/O66 I/O201 I/O222 I/O242 NC AB C GND I/O31 I/O50 TCK V CC I/O77 I/O84 I/O91 I/O97 V CC I/O110 I/O118 I/O124 VCC I/O138 I/O146 I/O152 VCC I/O166 I/O172 I/O179 I/O185 VCC I/O223 I/O243 I/O255AC D NC NC NC NC I/O71 I/O78 I/O85 I/O92 I/O98 I/O105 I/O111 I/O119 I/O125 I/O132 I/O139 I/O147 I/O153 I/O160 I/O167 I/O173 I/O180 I/O186 I/O202 TMS I/O244 G ND AD E NC NC GND I/O67 I/O72 I/O79 I/O86 I/O93 I/O99 I/O106 I/O112 I/O120 I/O126 I/O133 I/O140 I/O148 I/O154 I/O161 I/O168 I/O174 I/O181 I/O187 I/O203 NC GND N C AE AF NC NC GND NC GND NC GND I/O94 I/O100 GND I/O113 I/O121 I/O127 GND I/O141 I/O149 I/O155 GND NC I/O175 I/O182 GND I/O204 NC GND NC AF 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 20446G-030 CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations

352-BALL BGA CONNECTION DIAGRAM — M5-512, M5LV-512 Bottom View (I/O Pin-outs) 352-Ball BGA 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 A NC GND NC 7A10 GND 7A5 7A0 7B1 GND 7B7 NC 7B14 GND 6B14 6B10 6B6 GND 6B1 6A1 GND NC GND NC GND NC NC A B NC GND NC 7A13 7A9 7A6 7A2 7B0 7B3 7B6 7B10 7B13 7B15 6B13 6B9 6B5 6B2 6A0 6A4 6A6 6A9 6A12 6A14 GND NC NC B C GND 0A1 TDI 7A14 7A11 7A7 7A3 7A1 7B2 7B5 7B9 7B12 6B15 6B12 6B8 6B4 6B0 6A2 6A5 6A8 6A10 6A13 NC NC NC NC C D 0A6 0A3 0A2 V CC 7A15 7A12 7A8 7A4 V CC 7B4 7B8 7B11 V CC 6B11 6B7 6B3 V CC 6A3 6A7 6A11 6A15 V CC TDO 5A1 5A2 GND D E NC 0A8 0A5 0A0 5A0 5A4 5A5 NC E F GND 0A9 0A7 0A4 5A3 5A7 5A9 5A12 F G 0A13 0A12 0A10 V CC 5A6 5A8 5A14 GND G H 0D15 0A15 0A14 0A11 VCC 5A10 5A15 5D15 H J GND 0D13 0D14 V CC 5A11 5A13 5D13 5D11 J K 0D9 0D10 0D11 0D12 VCC 5D 14 5D10 GND K L 0D5 0D6 0D7 0D8 5D12 5D9 5D8 5D6 L M 0D1 0D2 0D4 0D3 5D7 5D5 5D4 5D3 M N GND 0D0 I0/CLK0 VCC 5D2 5D1 5D0 I3/CLK3 N P I1/CLK1 1D0 1D1 1D2 VCC I2/CLK2 4D0 GND P R 1D3 1D4 1D5 1D7 4D3 4D4 4D2 4D1 R T 1D6 1D8 1D9 1D12 4D8 4D7 4D6 4D5 T U GND 1D10 1D14 V CC 4D12 4D11 4D10 4D9 U V 1D11 1D13 1A13 1A11 VCC 4D14 4D13 GND V W 1D15 1A15 1A10 V CC 4A11 4A14 4A15 4D15 W Y GND 1A14 1A8 1A6 VCC 4A10 4A12 4A13 Y AA 1A12 1A9 1A7 1A3 4A4 4A7 4A9 GND AA AB NC 1A5 1A4 1A0 4A0 4A5 4A8 NC AB AC GND 1A2 1A1 TCK V CC 2A15 2A11 2A7 2A3 V CC 2B3 2B7 2B11 V CC 3B11 3B7 3B3 V CC 3A2 3A6 3A10 3A14 V CC 4A2 4A3 4A6 AC D NC NC NC NC 2A13 2A10 2A8 2A5 2A2 2B0 2B4 2B8 2B12 2B15 3B12 3B8 3B4 3B1 3A1 3A4 3A8 3A11 3A15 TMS 4A1 GND AD AE NC NC GND 2A14 2A12 2A9 2A6 2A4 2A0 2B2 2B5 2B9 2B13 3B15 3B13 3B9 3B5 3B2 3B0 3A3 3A7 3A9 3A13 NC GND NC AE AF NC NC GND NC GND NC GND 2A1 2B1 GND 2B6 2B10 2B14 GND 3B14 3B10 3B6 GND NC 3A0 3A5 GND 3A12 NC GND NC AF 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 20446G-031 CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations 7D 1 5 Macrocell (0-15) PAL Block (A-D) Segment (0-7)

44 MACH 5 Family

5V M5 ORDERING INFORMATION1,2 Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. *Package obsolete, contact factory. ** Contact Factory for availability. Device Marking Actual device marking differs from the ordering part number (OPN). All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e., M5-512/256-7AC-10AI. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to confirm availability of specific valid combinations and to check on newly released combinations. FAMILY TYPE M5- = MACH 5 (5-V V CC) M5- 512 /256 -7 A C MACROCELL DENSITY 128 = 128 Macrocells 192 = 192 Macrocells 256 = 256 Macrocells 320 = 320 Macrocells 384 = 384 Macrocells 512 = 512 Macrocells I/Os /68 = 68 I/Os in 100-pin PQFP or TQFP /74 = 74 I/Os in 100-pin TQFP /104 = 104 I/Os in 144-pin PQFP or TQFP /120 = 120 I/Os in 160-pin PQFP /160 = 160 I/Os in 208-pin PQFP /192 = 192 I/Os in 256-ball BGA /256 = 256 I/Os in 352-ball BGA OPERATING CONDITIONS C = Commercial (0 °C to +70°C) I = Industrial (-40 °C to +85°C) PACKAGE TYPE Y = Plastic Quad Flat Pack (PQFP) V = Thin Quad Flat Pack (TQFP) A = Ball Grid Array (BGA) H = Plastic Quad Flat Pack (PQFP) with exposed heat sink SPEED -5 = 5.5 ns t PD -6 = 6.5 ns t PD -7 = 7.5 ns t PD -10 = 10 ns t PD -12 = 12 ns t PD -15 = 15 ns t PD -20 = 20 ns t PD Note: 1. See below for valid device/package combinations. 2. M5-128/1, M5-192/1 and M5-256/1 recommended for new designs. PROGRAMMING DESIGNATOR Blank = Initial Algorithm /1 = First Revision Valid Combinations M5-128/68 Commercial: Industrial: YC, VC, YI, VI M5-128/104 YC, YI M5-128/120 YC, YI M5-192/68 YC*, VC, YI*, VI M5-192/104 YC*, YI* M5-192/120 YC, YI M5-256/68 YC*, VC, YI*, VI M5-256/104 YC*, YI* M5-256/120 YC, YI M5-256/160 YC, YI Valid Combinations M5-320/120 Commercial: Industrial: HC*, HI* M5-320/160 HC, YC, HI, YI M5-320/184 HC*, HI* M5-320/192 AC, AI M5-384/120 HC*, HI* M5-384/160 HC, YC, HI, YI M5-384/184 HC*, HI* M5-384/192 AC*, AI* M5-512/120 HC*, HI* M5-512/160 HC, YC, HI, YI M5-512/184 HC*, HI* M5-512/192 AC*, AI* M5-512/256 AC, AI

3.3V M5LV ORDERING INFORMATION1 Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. *Package obsolete, contact factory. ** Contact Factory for availability. Device Marking Actual device marking differs from the ordering part number (OPN). All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e., M5LV-512/256-7AC-10AI. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to confirm availability of specific valid combinations and to check on newly released combinations. FAMILY TYPE M5LV- = MACH 5 Low Voltage (3.3-V VCC) M5LV- 512 /256 -7 A C MACROCELL DENSITY 128 = 128 Macrocells 256 = 256 Macrocells 320 = 320 Macrocells 384 = 384 Macrocells 512 = 512 Macrocells I/Os /68 = 68 I/Os in 100-pin PQFP or TQFP /74 = 74 I/Os in 100-pin TQFP /104 = 104 I/Os in 144-pin PQFP or TQFP /120 = 120 I/Os in 160-pin PQFP /160 = 160 I/Os in 208-pin PQFP /192 = 192 I/Os in 256-ball BGA /256 = 256 I/Os in 352-ball BGA OPERATING CONDITIONS C = Commercial (0 °C to +70°C) I = Industrial (-40 °C to +85°C) PACKAGE TYPE Y = Plastic Quad Flat Pack (PQFP) V = Thin Quad Flat Pack (TQFP) A = Ball Grid Array (BGA) H = Plastic Quad Flat Pack (PQFP) with exposed heat sink SPEED -5 = 5.5 ns t PD -6 = 6.5 ns t PD -7 = 7.5 ns t PD -10 = 10 ns t PD -12 = 12 ns t PD -15 = 15 ns t PD -20 = 20 ns t PD Note: 1. See below for valid device/package combinations. Valid Combinations M5LV-128/68 Commercial: -5, -7, -10, -12 Industrial: -7, -10, -12, -15 YC*, VC, YI*, VI M5LV-128/74 VC, VI M5LV-128/104 YC*, VC, YI*, VI M5LV-128/120 YC, YI M5LV-256/68 YC, VC*, YI, VI* M5LV-256/74 VC, VI M5LV-256/104 YC*, VC, YI*, VI M5LV-256/120 YC, YI M5LV-256/160 YC, YI Valid Combinations M5LV-320/120 Commercial: Industrial: -10, -12, -15, -20 HC, YC, HI, YI M5LV-320/160 HC, YC, HI, YI M5LV-320/184 HC*, HI* M5LV-320/192 AC*, AI* M5LV-384/120 HC, YC, HI, YI M5LV-384/160 HC, YC, HI, YI M5LV-384/184 HC*, HI* M5LV-384/192 AC*, AI* M5LV-512/120 HC, YC, HI, YI M5LV-512/160 HC, YC, HI, YI M5LV-512/184 HC*, HI* M5LV-512/192 AC*, AI* M5LV-512/256 AC, AI

46 MACH 5 Family, 3.3-V Ind

MACH 5 Family, 3.3-V Ind 47