Logic IC

M4LV-32/32-10JC

Lattice Semiconductor

High Performance E 2 CMOS In-System Programmable Logic

Manufacturer: Lattice Semiconductor

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Publication# 17466 Rev: M Amendment/ Issue Date: March 2000 MACH 4 CPLD Family High Performance E CMOS In-System Programmable Logic

FEATURES

N High-performance, E CMOS 3.3-V & 5-V CPLD families N Flexible architecture for rapid logic designs — Excellent First-Time-Fit TM and reﬁt feature — SpeedLocking TM performance for guaranteed ﬁxed timing — Central, input and output switch matrices for 100% routability and 100% pin-out retention N High speed — 7.5ns t PD Commercial and 10ns t PD Industrial — 111.1MHz f CNT N 32 to 256 macrocells; 32 to 384 registers N 44 to 256 pins in PLCC, PQFP , TQFP and BGA packages N Flexible architecture for a wide range of design styles — D/T registers and latches — Synchronous or asynchronous mode — Dedicated input registers — Programmable polarity — Reset/ preset swapping N Advanced capabilities for easy system integration — 3.3-V & 5-V JEDEC-compliant operations — JTAG (IEEE 1149.1) compliant for boundary scan testing — 3.3-V & 5-V JTAG in-system programming — PCI compliant (-7/-10/-12 speed grades) — Safe for mixed supply voltage system designs — Bus-Friendly TM inputs and I/Os — Programmable security bit — Individual output slew rate control N Advanced E CMOS process provides high-performance, cost-effective solutions N Supported by ispDesignEXPERT TM software for rapid logic development — Supports HDL design methodologies with results optimized for MACH 4 — Flexibility to adapt to user requirements — Software partnerships that ensure customer success N Lattice and third-party hardware programming support — LatticePRO TM software for in-system programmability support on PCs and automated test equipment — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General

2 MACH 4 Family

For information on the M4-96/96 device, please refer to the M4-96/96 data sheet at www.latticesemi.com.
“M4-xxx” is for 5-V devices. “M4LV-xxx” is for 3.3-V devices.

Table 1. MACH 4 Device Features

densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation. equipment for device connectivity. SpeedLocking feature when using up to 20 product terms per output (Table 2).

C = Commercial, I = Industrial

transition or for the lowest noise transition. Table 2. MACH 4 Speed Grades

4 MACH 4 Family

Table 3. MACH 4 Package and I/O Options (Number of I/Os and dedicated inputs in Table)

device instead of having to use multiple devices. The key to being able to make effective use of these devices lies in the interconnect schemes. resources provide the ﬂexibility needed to ﬁt designs efﬁciently.

16 for MACH 4 devices with 1:1 macrocell-I/O cell ratio (see next page).
Block clocks do not go to I/O cells in M4(LV)-32/32.
M4(LV)-192/96 and M4(LV)-256/128 have dedicated clock pins which cannot be used as inputs and do not connect to the central

Figure 1. MACH 4 Block Diagram and PAL Block Structure

6 MACH 4 Family

Table 4. Architectural Summary of MACH 4 devices cells internally in a PAL block (Table 4). 4 devices communicate with each other with consistent, predictable delays. internal architecture of the device.

and are provided in both true and complement forms for efﬁcient logic implementation. macrocell within a PAL block are shown in Tables 6 and 7. macrocell that the cluster will drive if not routed away, regardless of the actual routing. allocator are shown in Figures 3 and 4. Table 5. PAL Block Inputs

8 MACH 4 Family

Table 6. Logic Allocator for All MACH 4 Devices (except M4(LV)-32/32) Table 7. Logic Allocator for M4(LV)-32/32

0 Default

Figure 2. Logic Allocator: Conﬁguration of Cluster “n” Set by Mode of Macrocell “n”

10 MACH 4 Family

mode will generally be used, since it provides more product terms in the allocator. Figure 5. Macrocell

cause oscillation if both J and K inputs are HIGH. Figure 6. Primary Macrocell Conﬁgurations

12 MACH 4 Family

Polarity of CLK/LE can be programmed

type, the polarity of the inputs can be programmed. reset and preset are provided, each driven by a product term common to the entire PAL block. Table 8. Register/Latch Operation Figure 7. Synchronous Mode Initialization Conﬁgurations

provided for initialization. It can be selected to control reset or preset.

Transparent latch is unaffected by AR, AP

Table 9. Asynchronous Reset/Preset Operation Figure 8. Asynchronous Mode Initialization Conﬁgurations

14 MACH 4 Family

occur without effecting pinout. with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/O cells (Figure 9). 2:1 macrocell-I/O cell ratio. Figure 9. MACH 4 Output Switch Matrix

Table 10. Output Switch Matrix Combinations for MACH 4 Devices with 2:1 Table 11. Output Switch Matrix Combinations for M4(LV)-32/32

16 MACH 4 Family

second data value is put on the I/O pin and compared with the previous stored value. macrocells. It powers up to a logic low. the clock path. When the fuse is erased, the setup time to the input storage element is minimized. have low (or zero) minimum output propagation delays from clock edges. signals to enter the central switch matrix. Figure 10. I/O Cell for MACH 4 Devices with 2:1 Figure 11. I/O Cell for MACH 4 Devices with 1:1

18 MACH 4 Family

Values in parentheses are for the M4(LV)-32/32 and M4(LV)-64/32.

Table 12. PAL Block Clock Combinations1

matrix after having gone through the output buffer, it is using external feedback. High Speed Design for a more detailed discussion about the timing parameters. with the assistance of an XOR gate without incurring additional timing delays. Figure 15. MACH 4 Timing Model

20 MACH 4 Family

IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY All MACH 4 devices, except the M4(LV)-128N/64, have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for veriﬁcation. In addition, these devices can be linked into a board-level serial scan path for more complete board-level testing. IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of signiﬁcant beneﬁts including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-ﬁeld modiﬁcations. All MACH 4 devices provide In-System Programming (ISP) capability through their Boundary ScanTest Access Ports. This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, customers get the beneﬁt of a standard, well-deﬁned interface. MACH 4 devices can be programmed across the commercial temperature and voltage range. The PC-based LatticePRO software facilitates in-system programming of MACH 4 devices. LatticePRO takes the JEDEC ﬁle output produced by the design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. LatticePRO software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, LatticePRO software can output ﬁles in formats understood by common automated test equipment. This equpment can then be used to program MACH 4 devices during the testing of a circuit board. PCI COMPLIANT MACH 4 devices in the -7/-10/-12 speed grades are compliant with the PCI Local Bus Speciﬁcation version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above V CC because of their 5-V input tolerant feature. SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS Both the 3.3-V and 5-V VCC MACH 4 devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they 5-V and 3.3-V versions have the same high-speed performance and provide easy-to-use mixed- voltage design capability. BUS-FRIENDLY INPUTS AND I/OS All MACH 4 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice/Vantis Data Book CD-ROM or Lattice web site.

Each individual PAL block in MACH 4 devices features a programmable low-power mode, which results in power savings of up to 50%. The signal speed paths in the low-power PAL block will be slower than those in the non-low-power PAL block. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in the low-power mode. PROGRAMMABLE SLEW RATE Each MACH 4 device I/O has an individually programmable output slew rate control bit. Each output can be individually conﬁgured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reﬂections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power. POWER-UP RESET/SET All ﬂip-ﬂops power up to a known state for predictable system initialization. If a macrocell is conﬁgured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is conﬁgured to RESET on a signal from the control generator or is not conﬁgured for set/reset, then that macrocell will RESET on power-up. To guarantee initialization values, the V CC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed. SECURITY BIT A programmable security bit is provided on the MACH 4 devices as a deterrent to unauthorized copying of the array conﬁguration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and veriﬁcation are also defeated by the security bit. The bit can only be reset by erasing the entire device.

22 MACH 4 Family

Figure 16. PAL Block for MACH 4 with 2:1 Macrocell - I/O Cell Ratio

Figure 17. PAL Block for M4(LV)-32/32

24 MACH 4 Family

BLOCK DIAGRAM – M4(LV)-32/32 17466H-019 Central Switch Matrix2 CLK0/I0, CLK1/I1 I/O8–I/O15 I/O0–I/O7 I/O16–I/O23 I/O24–I/O31 I/O Cells Output Switch Matrix Macrocells 4 4 I/O Cells Output Switch Matrix Macrocells

66 X 98

BLOCK DIAGRAM – M4(LV)-64/32 17466H-020 Central Switch Matrix2 CLK0/I0, CLK1/I1 I/O0–I/O7 I/O24 –I/O31 I/O16–I/O23I/O8–I/O15 I/O Cells Output Switch Matrix Macrocells

66 X 90

26 MACH 4 Family

BLOCK DIAGRAM – M4(LV)-96/48 4 4 CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5 I2, I3, I6, I7 I/O16–I/O23 I/O8–I/O15 I/O0–I/O7 I/O40–I/O47I/O32–I/O39I/O24–I/O31 I/O Cells Output Switch Matrix Macrocells

BLOCK DIAGRAM – M4(LV)-128N/64 AND M4(LV)-128/64 Central Switch Matrix4 4 2 CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4 I2, I5 I/O0–I/O7I/O8–I/O15I/O16–I/O23I/O24–I/031 I/O32–I/O39 I/O40 –I/O47 I/O48 –I/O55 I/O56 –I/O63 I/O Cells Output Switch Matrix Macrocells Block ABlock BBlock CBlock D Block HBlock GBlock FBlock E 17466H-022

28 MACH 4 Family

BLOCK DIAGRAM – M4(LV)-192/96 Central Switch Matrix Block B I/O8–I/O15 CLK0 –CLK3 I/O32–I/O39 Block E I/O56–I/O63 Block H I/O48–I/O55 Block G I0–I15I/O40–I/O47 Block F Block A I/O0–I/O7 Block K I/O80–I/O87 Block L I/O88–I/O95 Block C I/O16–I/O23 Block D I/O24–I/O31 I/O72–I/O79 Block J I/O64–I/O71 Block I I/O Cells Macrocells

68 X 90

BLOCK DIAGRAM – M4(LV)-256/128 Central Switch Matrix Block B I/O8–I/O15 CLK0 –CLK3 I/O48–I/O55 Block G I/O72–I/O79 Block J I/O64–I/O71 Block I I0–I13I/O56–I/O63 Block H Block A I/O0–I/O7 Block O I/O112–I/O119 Block P I/O120–I/O127 Block C I/O16–I/O23 Block D I/O24–I/O31 Block E I/O32–I/O39 Block F I/O40–I/O47 I/O104–I/O111 Block N I/O96–I/O103 Block M I/O88–I/O95 Block L I/O80–I/O87 Block K I/O Cells Macrocells

Latchup Current (T Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Supply Voltage (VCC) Industrial (I) Devices Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges deﬁne those limits between which the func- tionality of the device is guaranteed. Notes: 1. Total I OL for one PAL block should not exceed 64 mA. 2. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 3. I/O pin leakage is the worst case of I IL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V IOH = 0 mA, VCC = Max, VIN = VIH or VIL 3.3 V VOL Output LOW Voltage I OL = 24 mA, VCC = Min, VIN = VIH or VIL (Note 1) 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) 2.0 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) 0.8 V IIH Input HIGH Leakage Current V IN = 5.25 V, VCC = Max (Note 3) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 3) –10 µA IOZH Off-State Output Leakage Current HIGH V OUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 3) 10 µA IOZL Off-State Output Leakage Current LOW V OUT = 0 V, VCC = Max , VIN = VIH or VIL (Note 3) –10 µA ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 4) –30 –160 mA

Latchup Current (T Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Supply Voltage (VCC) Industrial (I) Devices Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges deﬁne those limits between which the func- tionality of the device is guaranteed. Notes: 1. Total I OL for one PAL block should not exceed 64 mA. 2. I/O pin leakage is the worst case of I IL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. 3.3-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage VCC = Min VIN = VIH or VIL IOH = –100 µAV CC – 0.2 V IOH = –3.2 mA 2.4 V VOL Output LOW Voltage VCC = Min VIN = VIH or VIL (Note 1) IOL = 100 µA 0.2 V IOL = 24 mA 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs 2.0 5.5 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs –0.3 0.8 V IIH Input HIGH Leakage Current V IN = 3.6 V, VCC = Max (Note 2) 5 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –5 µA IOZH Off-State Output Leakage Current HIGH VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) 5 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –5 µA ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) –15 –160 mA

32 MACH 4 Family

MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 UnitMin Max Min Max Min Max Min Max Min Max Min Max Combinatorial Delay: t Registered Delays: t Latched Delays: t Input Register Delays: t Input Latch Delays: t Input Register Delays with ZHT Option: t

Input Latch Delays with ZHT Option: Output Delays: t Power Delay: t Reset and Preset Delays: t Clock/LE Width: t tGWS Global gate width low (for low transparent) or high tGWA Product term gate width low (for low transparent) or MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) UnitMin Max Min Max Min Max Min Max Min Max Min Max

34 MACH 4 Family

Notes: 1. See “MACH Switching Test Circuit” document on the Literature Download page of the Lattice web site. 2. This parameter does not apply to ﬂip-ﬂops in the emulated mode since the feedback path is required for emulation. CAPACITANCE 1 Note: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modiﬁed where this parameter may be affected. Frequency: fMAXS External feedback, D-type, Min of 1/(tWLS + tWHS) or External feedback, T-type, Min of 1/(tWLS + tWHS) or Internal feedback (fCNT), D-type, Internal feedback (fCNT), T-type, No feedback2, Min of 1/(tWLS + tWHS), 1/(tSS + tHS) or fMAXA External feedback, D-type, Min of 1/(tWLA + tWHA) or External feedback, T-type, Min of 1/(tWLA + tWHA) or Internal feedback (fCNTA), D-type, Internal feedback (fCNTA), T-type, No feedback2, Min of 1/(tWLA + tWHA), fMAXI Maximum input register frequency, Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input capacitance V IN=2.0 V 3.3 V or 5 V, 25°C, 1 MHz 6 pF CI/O Output capacitance V OUT=2.0V 3.3 V or 5 V, 25°C, 1 MHz 8 pF MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) UnitMin Max Min Max Min Max Min Max Min Max Min Max

36 MACH 4 Family

44-PIN PLCC CONNECTION DIAGRAM (M4(LV)-32/32 AND M4(LV)-64/32) Top View 44-Pin PLCC PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 1 44 43 425 4 3 264 1 40 23 24 25 2619 20 21 2218 27 28 I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 B10 A10 A11 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 A12 A13 A14 A15 B15 B14 B13 B12 B11 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 M4(LV)-32/32 M4(LV)-32/32 M4(LV)-64/32 M4(LV)-64/32 M4(LV)-64/32 M4(LV)-64/32 17466G-026 I/O Cell (0-7) PAL Block (A-D)

44-PIN TQFP CONNECTION DIAGRAM (M4(LV)-32/32 AND M4(LV)-64/32) Top View 44-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 A12 A13 A14 A15 B15 B14 B13 B12 B11 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21 B10 I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 A10 A11 M4(LV)-32/32 M4(LV)-32/32 M4(LV)-64/32 M4(LV)-64/32 M4(LV)-64/32 M4(LV)-64/32 I/O Cell (0-7) PAL Block (A-D)

38 MACH 4 Family

48-PIN TQFP CONNECTION DIAGRAM (M4(LV)-32/32 AND M4(LV)-64/32) Top View 48-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output V CC = Supply Voltage NC = No Connect TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out I/O12 I/O13 I/O14 I/O15 VCC NC GND I/O16 I/O17 I/O18 I/O19 I/O20 A12 A13 A14 A15 B15 B14 B13 B12 B11 I/O4 I/O3 I/O2 I/O1 I/O0 GND NC VCC I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 TDO GND NC CLK1/I1 TMS I/O23 I/O22 I/O21 B10 I/O5 I/O6 I/O7 TDI CLK0/I0 NC GND TCK I/O8 I/O9 I/O10 I/O11 A10 A11 M4(LV)-32/32M4(LV)-32/32 M4(LV)-64/32 M4(LV)-64/32 M4(LV)-64/32 M4(LV)-64/32 17466G-028 I/O Cell (0-7) PAL Block (A-D)

100-PIN TQFP CONNECTION DIAGRAM (M4(LV)-96/48) Top View 100-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage NC = No Connect TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out NC TDI NC NC I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I0/CLK0 V CC GND I1/CLK1 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 NC NC TMS TCK NC GND NC NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC NC NC GND V CC I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 NC NC GND 100 GND NC NC I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 V CC GND NC NC NC I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 NC NC GND NC TDO NC NC NC I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I5/CLK3 GND V CC I4/CLK2 I/O35 I/O34 I/O33 I/O32 I/O31 I/O30 NC NC NC NC 17466G-029 I/O Cell (0-7) PAL Block (A-F)

40 MACH 4 Family

84-PIN PLCC CONNECTION DIAGRAM (M4(LV)-128N/64) Top View 84-Pin PLCC Note: Pin-compatible with the MACH131, MACH231, MACH435. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage 123 818283846789 45 80 76777879 75 43424140 4746454437363534 393833 48 52515049 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK 0/I0 VCC GND CLK 1/I1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O8 GND I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK 3/I4 VCC CLK 2/I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 GND I/O40 GND VCC I/O0 I/O62 I/O63 VCC I/O3 I/O4 I/O5 I/O6 I/O1 I/O2 I/O61 I/O57 I/O58 I/O59 I/O60 I/O56 I/O7 GND GND VCC I/O34 I/O33 I/O32 VCC I/O29 I/O28 I/O27 I/O26 I/O31 I/O30 I/O35 I/O39 I/O38 I/O37 I/O36 GND I/O25 I/O24 D017466G-030 I/O Cell (0-7) PAL Block (A-H)

100-PIN PQFP CONNECTION DIAGRAM (M4(LV)-128/64) Top View 100-Pin PQFP Note: The numbers in parentheses reﬂect compatible pin numbers for 84-pin PLCC. PIN DESIGNATIONS I/CLK = Input or Clock GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out TRST = Test Reset ENABLE = Program I/O7 A7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 V CC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND TDI I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 IO/CLK0 GND GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND GND 10031 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 ENABLE GND GND GND TD0 TRST I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND GND I3/CLK2 I/O47 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND GND I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 (83) (12) (13) (14) (15) (16) (17) (18) (19) (20) (23) (24) (25) (26) (27) (28) (29) (30) (31)(33) (34) (35) (36) (37) (38) (39) (40) (45) (46) (47) (48) (49) (50) (51) (52) (62) (61) (60) (59) (58) (57) (56) (55) (54) (41) (73) (72) (71) (70) (69) (68) (67) (66) (65) (10) (9) (8) (7) (6) (5) (4) (3) (82) (81) (80) (79) (78) (77) (76) (75) VCC VCC VCC VCC VCC VCC 17466G-031 I/O Cell (0-7) PAL Block (A-H)

42 MACH 4 Family

100-PIN TQFP CONNECTION DIAGRAM (M4(LV)-128/64) Top View 100-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out TRST = Test Reset ENABLE = Program GND TDI I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 VCC GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 V CC GND GND V CC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND 100 GND GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND GND TDO TRST I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 ENABLE GND 17466G-032 I/O Cell (0-7) PAL Block (A-H)

144-PIN TQFP CONNECTION DIAGRAM (M4(LV)-192/96) Top View 144-Pin TQFP PIN DESIGNATIONS CLK = Clock GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 17466G-033 GND TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 V CC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND V CC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 CLK1 GND V CC CLK2 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 V CC GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND V CC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 CLK0 GND V CC CLK3 I15 I14 I13 I/O79 I/O78 I/O77 I/O76 I/O75 I/O74 I/O73 I/O72 GND 108 107 106 105 104 103 102 101 100 GND TDO NC I/O71 I/O70 I/O69 I/O68 I/O67 I/O66 I/O65 I/O64 I12 V CC GND I11 I10 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND V CC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 NC GND I/O Cell (0-7) PAL Block (A-L) 17466G-044

44 MACH 4 Family

208-PIN PQFP CONNECTION DIAGRAM (M4(LV)-256/128) Top View 208-Pin PQFP GND TDI I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND VCC VCC GND GND VCC VCC GND I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND VCC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 TMS TCK GND GND I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND VCC I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 CLK1 VCC GND GND VCC VCC GND GND VCC CLK2 I/O64 I/O66 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 VCC GND I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 GND 100 101 102 103 104 GND I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLK0 VCC GND GND VCC VCC GND GND VCC CLK3 I13 I12 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 VCC GND I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND GND TDO TRST I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 VCC GND I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 I/O96 I11 GND VCC VCC GND GND VCC VCC GND I10 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 ENABLE GND 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 RECOMMEND TO TIE TO VCC RECOMMEND TO TIE TO GND PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell (0-7) PAL Block (A-HX) Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program 17466G-044 17466H-066

256-BALL BGA CONNECTION DIAGRAM (M4(LV)-256/128) Bottom View 256-Ball BGA GND GND I/O116 I/O120 I/O123 GND I12 GND N/C GND N/C N/C GND A B C D E F G H J K L M N P R T U V W Y A B C D E F G H J K L M N P R T U V W Y N/C I/O113 N/C I/O117 I/O119 I/O122 I/O125 I/O127 N/C CLK3 CLK0 N/C I/O0 I/O1 GND N/C VCC I/O112 I/O114 I/O118 I/O121 I/O126 N/C N/C N/C N/C I/O2 I/O6 I/O108 I/O109 TRST VCC TDI I/O115 VCC I/O124 I13 N/C N/C I/O3 VCC I/O105 I/O106 I/O111 VCC GND I/O103 I/O107 I/O110 I/O100 I/O102 I/O104 VCC I/O96 I/O98 I/O101 N/C GND N/C I/O97 I/O99 GND I11 N/C N/C GND N/C I10 GND N/C I/O94 I/O92 GND I/O82 VCC I/O79 I/O77 I/O73 I/O70 I/O66 N/C N/C N/C N/C I/O61 I/O57 GND 20 19 18 17 16 15 14 13 12 11 10 9 I/O95 I/O93 I/O90 N/C I/O91 I/O89 I/O86 VCC GND I/O88 I/O84 I/O81 I/O87 I/O85 I/O80 VCC N/C I/O83 ENABLE VCC TDO I/O76 VCC I/O67 N/C N/C I/O60 VCC GND N/C I/O78 I/O75 I/O72 I/O69 I/O65 I/O64 N/C CLK2 CLK1 I/O63 I/O59 I/O58 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 GND I/O74 I/O71 I/O68 GND GND N/C N/C GND I/O62 GND GND I/O4 I/O7 I/O5 I/O8 I/O11 I/O9 I/O12 I/O15 N/C TCK VCC VCC I/O18 C5 VCC I/O24 I/O29 D2 I2 N/C I/O35 I/O54 I/O50 I/O48 G7N/C VCC N/C VCC I/O51 TMS VCC I/O56 I/O55 I/O53 GND N/C N/C I/O10 GND GND I/O13 I/O14 GND VCC N/C GND I/O16 N/C N/C I/O17 I/O19 I/O20 I/O21 I/O22 GND I/O23 I/O25 I/O26 I/O27 I/O28 I/O30 I/O31 N/C GND N/C GND N/C GND I/O33 N/C GND VCC N/C GND I/O37 I/O34 I/O32 I/O41 I/O38 I/O36 I/O43 I/O39 GND I/O46 I/O42 I/O40 I/O47 I/O45 I/O44 I/O52 I/O49 N/C N/C GND GND PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell (0-7) PAL Block (A-P) Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program 17466G-045

46 MACH 4 Family

MACH 4 PRODUCT ORDERING INFORMATION MACH 4 Devices Commercial & Industrial - 3.3V and 5V Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Com- bination) is formed by a combination of: All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, i.e., M4-256/128-7YC-10YI Valid Combinations Valid Combinations list conﬁgurations planned to be supported in volume for this device. Consult the local Lattice sales ofﬁce to conﬁrm availability of speciﬁc valid combinations and to check on newly released combinations. 128 FAMILY TYPE M4- = MACH 4 Family (5-V V CC) M4LV- = MACH 4 Family Low Voltage (3.3-V VCC) M4- 256 Y C MACROCELL DENSITY 32 = 32 Macrocells 128N = 128 Macrocells, Non-ISP 64 = 64 Macrocells 192 = 192 Macrocells 96 = 96 Macrocells 256 = 256 Macrocells 128 = 128 Macrocells I/Os /32 = 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP /48 = 48 I/Os in 100-pin TQFP /64 = 64 I/Os in 84-pin PLCC, 100-pin PQFP or 100-pin TQFP /96 = 96 I/Os in 144-pin TQFP /128 = 128 I/Os in 208-pin PQFP or 256-ball BGA OPERATING CONDITIONS C = Commercial (0 °C to +70°C) I = Industrial (-40 °C to +85°C) PACKAGE TYPE A = Ball Grid Array (BGA) J = Plastic Leaded Chip Carrier (PLCC) V = Thin Quad Flat Pack (TQFP) Y = Plastic Quad Flat Pack (PQFP) SPEED -7 = 7.5 ns t PD -10 = 10 ns t PD -12 = 12 ns t PD -14 = 14 ns t PD -15 = 15 ns t PD -18 = 18 ns t PD 48 = 48-pin TQFP for M4(LV)-32/32 or M4(LV)-64/32 Valid Combinations M4-32/32 -7, -10, -12, -15 JC, VC, VC48 M4LV-32/32 JC, VC, VC48 M4-64/32 JC, VC, VC48 M4LV-64/32 JC, VC, VC48 M4-96/48 VC M4LV-96/48 VC M4-128/64 YC, VC M4LV-128/64 YC, VC M4-128N/64 JC M4LV-128N/64 JC M4-192/96 VC M4LV-192/96 VC M4-256/128 YC, AC M4LV-256/128 YC, AC Valid Combinations M4-32/32 -10, -12, -14, -18 JI, VI, VI48 M4LV-32/32 JI, VI, VI48 M4-64/32 JI, VI, VI48 M4LV-64/32 JI, VI, VI48 M4-96/48 VI M4LV-96/48 VI M4-128/64 YI, VI M4LV-128/64 YI, VI M4-128N/64 JI M4LV-128N/64 JI M4-192/96 VI M4LV-192/96 VI M4-256/128 YI, AI M4LV-256/128 YI, AI

Product Information

M4LV-32/32-10JC specifications and overview.

Summary

High Performance E 2 CMOS In-System Programmable Logic

Description

High Performance E 2 CMOS In-System Programmable Logic

Source title M4LV-32/32-10JC Datasheet(PDF) - Lattice Semiconductor

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