ISPMACH4ACPLDFAMILY LATTICE | Alldatasheet
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Publication# ISPM4A Rev: D Amendment/ Issue Date: August 2000 ispMACH 4A CPLD Family High Performance E CMOS In-System Programmable Logic
FEATURES
N High-performance, E CMOS 3.3-V & 5-V CPLD families N Flexible architecture for rapid logic designs — Excellent First-Time-Fit TM and refit feature — SpeedLocking TM performance for guaranteed fixed timing — Central, input and output switch matrices for 100% routability and 100% pin-out retention N High speed — 5.0ns t PD Commercial and 7.5ns t PD Industrial — 182MHz f CNT N 32 to 512 macrocells; 32 to 768 registers N 44 to 388 pins in PLCC, PQFP , TQFP , BGA, fpBGA and caBGA packages N Flexible architecture for a wide range of design styles — D/T registers and latches — Synchronous or asynchronous mode — Dedicated input registers — Programmable polarity — Reset/ preset swapping N Advanced capabilities for easy system integration — 3.3-V & 5-V JEDEC-compliant operations — JTAG (IEEE 1149.1) compliant for boundary scan testing — 3.3-V & 5-V JTAG in-system programming — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades) — Safe for mixed supply voltage system designs — Programmable pull-up or Bus-Friendly TM inputs and I/Os — Hot-socketing — Programmable security bit — Individual output slew rate control N Advanced E CMOS process provides high-performance, cost-effective solutions N Supported by ispDesignEXPERT TM software for rapid logic development — Supports HDL design methodologies with results optimized for ispMACH 4A — Flexibility to adapt to user requirements — Software partnerships that ensure customer success N Lattice and third-party hardware programming support — LatticePRO TM software for in-system programmability support on PCs and automated test equipment — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General
- Advance information. Please contact a Lattice sales representative for details on availability.
- M4A3-256/128 available now in 5.5ns. Contact factory for availability of 7.5ns M4A3-256/160 and M4A3-256/192
Table 1. ispMACH 4A Device Features
3.3 V Devices
5 V Devices
densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation. ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. equipment for device connectivity. SpeedLocking feature when using up to 20 product terms per output (Table 2).
- C = Commercial, I = Industrial
- Advance information. Please contact a Lattice sales representative for details on availability.
Table 2. ispMACH 4A Speed Grades
- Advance information. Please contact a Lattice sales representative for details on availability.
Table 3. ispMACH 4A Package and I/O Options
device instead of having to use multiple devices. The key to being able to make effective use of these devices lies in the interconnect schemes. matrix. These resources provide the flexibility needed to fit designs efficiently.
- 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).
- Block clocks do not go to I/O cells in M4A(3,5)-32/32.
- M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do
not connect to the central switch matrix. Figure 1. ispMACH 4A Block Diagram and PAL Block Structure
Table 4. Architectural Summary of ispMACH 4A devices cells internally in a PAL block (Table 4). ispMACH 4A devices communicate with each other with consistent, predictable delays. internal architecture of the device.
- M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.
and are provided in both true and complement forms for efficient logic implementation. macrocell within a PAL block are shown in Tables 6 and 7. macrocell that the cluster will drive if not routed away, regardless of the actual routing. allocator are shown in Figures 3 and 4. Table 5. PAL Block Inputs
Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32)
4 C3, C4, C5, C6 M12 C11, C12, C13, C14
Table 7. Logic Allocator for M4A(3,5)-32/32
0 Default
Figure 2. Logic Allocator: Configuration of Cluster “n” Set by Mode of Macrocell “n”
mode will generally be used, since it provides more product terms in the allocator. Figure 5. Macrocell
cause oscillation if both J and K inputs are HIGH. Figure 6. Primary Macrocell Configurations
- Polarity of CLK/LE can be programmed
type, the polarity of the inputs can be programmed. reset and preset are provided, each driven by a product term common to the entire PAL block. Table 8. Register/Latch Operation Figure 7. Synchronous Mode Initialization Configurations
provided for initialization. It can be selected to control reset or preset.
- Transparent latch is unaffected by AR, AP
Table 9. Asynchronous Reset/Preset Operation Figure 8. Asynchronous Mode Initialization Configurations
occur without effecting pinout. Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio 2:1 macrocell-I/O cell ratio. Figure 9. ispMACH 4A Output Switch Matrix
Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192
Table 13. Output Switch Matrix Combinations for M4A3-64/64 Table 12. Output Switch Matrix Combinations for M4A(3,5)-32/32
a large number of combinations of the true and complement edges of the global clock signals. Table 14 lists the possible combinations.
- M4A(3,5)-32/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is
- Values in parentheses are for the M4A(3,5)-32/32 and M4A(3,5)-64/32.
Table 14. PAL Block Clock Combinations1 Figure 14. PAL Block Clock Generator 1
switch matrix after having gone through the output buffer, it is using external feedback. High Speed Design for a more detailed discussion about the timing parameters. macrocell with the assistance of an XOR gate without incurring additional timing delays. Figure 15. ispMACH 4A Timing Model
IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY All ispMACH 4A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board- level serial scan path for more complete board-level testing. IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All ispMACH 4A devices provide In-System Programming (ISP) capability through their Boundary ScanTest Access Ports. This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface. ispMACH 4A devices can be programmed across the commercial temperature and voltage range. The PC-based LatticePRO software facilitates in-system programming of ispMACH 4A devices. LatticePRO takes the JEDEC file output produced by the design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. LatticePRO software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats understood by common automated test equipment. This equpment can then be used to program ispMACH 4A devices during the testing of a circuit board. PCI COMPLIANT ispMACH 4A devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the PCI Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above V CC because of their 5-V input tolerant feature. SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS Both the 3.3-V and 5-V V CC ispMACH 4A devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5 V. Both the 5-V and 3.3-V versions have the same high-speed performance and provide easy-to- use mixed-voltage design capability. PULL UP OR BUS-FRIENDLY INPUTS AND I/Os All ispMACH 4A devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.
All ispMACH 4A devices have a programmable bit that configures all inputs and I/Os with either pull-up or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs and I/O pins are weakly pulled up. For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site. POWER MANAGEMENT Each individual PAL block in ispMACH 4A devices features a programmable low-power mode, which results in power savings of up to 50%. The signal speed paths in the low-power PAL block will be slower than those in the non-low-power PAL block. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in the low-power mode. PROGRAMMABLE SLEW RATE Each ispMACH 4A device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow- slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power. POWER-UP RESET/SET All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee initialization values, the V CC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed. SECURITY BIT A programmable security bit is provided on the ispMACH 4A devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device. HOT SOCKETING ispMACH 4A devices are well-suited for those applications that require hot socketing capability. Hot socketing a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the powered-down MACH devices be minimal on active signals.
Figure 16. PAL Block for ispMACH 4A with 2:1 Macrocell - I/O Cell Ratio
Figure 17. PAL Block for ispMACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32)
Figure 18. PAL Block for M4A (3,5)-32/32
BLOCK DIAGRAM – M4A(3,5)-32/32 17466H-019 Central Switch Matrix2 CLK0/I0, CLK1/I1 I/O8–I/O15 I/O0–I/O7 I/O16–I/O23 I/O24–I/O31 I/O Cells Output Switch Matrix Macrocells 4 4 I/O Cells Output Switch Matrix Macrocells
66 X 98
BLOCK DIAGRAM – M4A(3,5)-64/32 17466H-020 Central Switch Matrix2 CLK0/I0, CLK1/I1 I/O0–I/O7 I/O24 –I/O31 I/O16–I/O23I/O8–I/O15 I/O Cells Output Switch Matrix Macrocells
66 X 90
BLOCK DIAGRAM – M4A3-64/64 Central Switch Matrix4 CLK0/I0, CLK1/I1 CLK2/I3, CLK3/I4 I/O Cells Output Switch Matrix Macrocells
BLOCK DIAGRAM – M4A(3,5)-96/48 4 4 CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5 I2, I3, I6, I7 I/O16–I/O23 I/O8–I/O15 I/O0–I/O7 I/O40–I/O47I/O32–I/O39I/O24–I/O31 I/O Cells Output Switch Matrix Macrocells
BLOCK DIAGRAM – M4A(3,5)-128/64 Central Switch Matrix4 4 2 CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4 I2, I5 I/O0–I/O7I/O8–I/O15I/O16–I/O23I/O24–I/031 I/O32–I/O39 I/O40 –I/O47 I/O48 –I/O55 I/O56 –I/O63 I/O Cells Output Switch Matrix Macrocells Block ABlock BBlock CBlock D Block HBlock GBlock FBlock E 17466H-022
BLOCK DIAGRAM – M4A(3,5)-192/96 Central Switch Matrix Block B I/O8–I/O15 CLK0 –CLK3 I/O32–I/O39 Block E I/O56–I/O63 Block H I/O48–I/O55 Block G I0–I15I/O40–I/O47 Block F Block A I/O0–I/O7 Block K I/O80–I/O87 Block L I/O88–I/O95 Block C I/O16–I/O23 Block D I/O24–I/O31 I/O72–I/O79 Block J I/O64–I/O71 Block I I/O Cells Macrocells
68 X 90
BLOCK DIAGRAM – M4A(3,5)-256/128 Central Switch Matrix Block B I/O8–I/O15 CLK0 –CLK3 I/O48–I/O55 Block G I/O72–I/O79 Block J I/O64–I/O71 Block I I0–I13I/O56–I/O63 Block H Block A I/O0–I/O7 Block O I/O112–I/O119 Block P I/O120–I/O127 Block C I/O16–I/O23 Block D I/O24–I/O31 Block E I/O32–I/O39 Block F I/O40–I/O47 I/O104–I/O111 Block N I/O96–I/O103 Block M I/O88–I/O95 Block L I/O80–I/O87 Block K I/O Cells Macrocells
BLOCK DIAGRAM – M4A3-256/160, M4A3-256/192 Central Switch Matrix Block B CLK0 –CLK3 Block G Block JBlock IBlock H Block A Block OBlock P Block C Block D Block E Block F Block N Block M Block L Block K I/O Cells Macrocells
72 X 98
BLOCK DIAGRAM – M4A3-384/160, M4A3-384/192 Central Switch Matrix Block B CLK0 –CLK3 Block A Block GXBlock HX Block C Block F Block D Block E Block FX Block CX Block EX Block DX I/O Cells Macrocells
72 X 90
Block LBlock K Block M Block N 17466G-067
BLOCK DIAGRAM - M4A3-512/160, M4A3-512/192, M4A3-512/256 Central Switch Matrix Block B CLK0 –CLK3 Block A Block OXBlock PX Block C Block F Block D Block E Block NX Block KX Block MX Block LX I/O Cells Macrocells Block PBlock O Block AX Block BX 4 4 17466G-068
Latchup Current (T Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Supply Voltage (VCC) Industrial (I) Devices Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges define those limits between which the func- tionality of the device is guaranteed. Notes: 1. Total I OL for one PAL block should not exceed 64 mA. 2. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 3. I/O pin leakage is the worst case of I IL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V IOH = –2.5 mA, VCC = Max, VIN = VIH or VIL 3.6 V VOL Output LOW Voltage I OL = 24 mA, VCC = Min, VIN = VIH or VIL (Note 1) 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) 2.0 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) 0.8 V IIH Input HIGH Leakage Current V IN = 5.25 V, VCC = Max (Note 3) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 3) –10 µA IOZH Off-State Output Leakage Current HIGH V OUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 3) 10 µA IOZL Off-State Output Leakage Current LOW V OUT = 0 V, VCC = Max , VIN = VIH or VIL (Note 3) –10 µA ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 4) –30 –160 mA
Latchup Current (T Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Supply Voltage (VCC) Industrial (I) Devices Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges define those limits between which the func- tionality of the device is guaranteed. Notes: 1. Total I OL for one PAL block should not exceed 64 mA. 2. I/O pin leakage is the worst case of I IL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Notes: 1. See “MACH Switching Test Circuit” document on the Literature Download page of the Lattice web site. 2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 3.3-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage VCC = Min VIN = VIH or VIL IOH = –100 µAV CC – 0.2 V IOH = –3.2 mA 2.4 V VOL Output LOW Voltage VCC = Min VIN = VIH or VIL (Note 1) IOL = 100 µA 0.2 V IOL = 24 mA 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs 2.0 5.5 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs –0.3 0.8 V IIH Input HIGH Leakage Current V IN = 3.6 V, VCC = Max (Note 2) 5 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –5 µA IOZH Off-State Output Leakage Current HIGH VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) 5 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –5 µA ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) –15 –160 mA
ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Combinatorial Delay: tPDi Internal combinatorial propagation Registered Delays: tSS Synchronous clock setup time, D-type tSST Synchronous clock setup time, T-type tSA Asynchronous clock setup time, D-type tSAT Asynchronous clock setup time, T-type Latched Delays: t tPDL Propagation delay through transparent Input Register Delays: t Input Latch Delays: t tPDILi Transparent input latch to internal
Input Register Delays with ZHT Option: Input Latch Delays with ZHT Option: t tPDIL Zi Transparent input latch to internal Output Delays: Power Delay: t Reset and Preset Delays: tSRi Asynchronous reset or preset to internal tSR Asynchronous reset or preset to register tSRR Asynchronous reset and preset register Clock/LE Width: t tGWS Global gate width low (for low transparent) or high (for high transparent) t GWA Product term gate width low (for low transparent) or high (for high transparent) t ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Notes: 1. See “Switching Test Circuit” document on the Literature Download page of the Lattice web site. 2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. CAPACITANCE 1 Note: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where this parameter may be affected. Frequency: fMAXS External feedback, D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS) 143 133 125 118 95.2 87.0 74.1 60.6 MHz External feedback, T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOS) 125 125 118 111 87.0 80.0 69.0 57.1 MHz Internal feedback (fCNT), D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOSi) 182 167 160 154 125 118 95.0 74.1 MHz Internal feedback (fCNT), T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOSi) 154 154 148 143 111 105 87.0 69.0 MHz No feedback2, Min of 1/(tWLS + tWHS), 1/(tSS + tHS) or 1/(tSST + tHS) 250 250 200 200 154 125 100 83.3 MHz fMAXA External feedback, D-type, Min of 1/ (tWLA + tWHA) or 1/(tSA + tCOA) 111 111 108 100 83.3 66.7 55.6 43.5 MHz External feedback, T-type, Min of 1/(tWLA Internal feedback (fCNTA), D-type, Min of 1/(tWLA + tWHA) or 1/(tSA + tCOAi) 133 133 125 125 105 83.3 66.7 50.0 MHz Internal feedback (fCNTA), T-type, Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOAi) 125 125 125 118 95.2 76.9 62.5 47.6 MHz No feedback2, Min of 1/(tWLA + tWHA), 1/(tSA + tHA) or 1/(tSAT + tHA) 167 167 143 143 125 100 62.5 55.6 MHz fMAXI Maximum input register frequency, Min of 1/(tWIRH + tWIRL) or 1/(tSIRS + tHIRS) 167 167 143 143 125 100 83.3 83.3 MHz Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input capacitance V IN=2.0 V 3.3 V or 5 V, 25°C, 1 MHz 6 pF CI/O Output capacitance V OUT=2.0V 3.3 V or 5 V, 25°C, 1 MHz 8 pF ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
ercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. est frequency signals (MSBs) are placed in a common PAL block and set to lowest power. Figure 19. ispMACH 4A ICC Curves at High Speed Mode
400 M4A-512/160
Figure 20. ispMACH 4A ICC Curves at Low Power Mode
44-PIN PLCC CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View 44-Pin PLCC PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 1 44 43 425 4 3 264 1 40 23 24 25 2619 20 21 2218 27 28 I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 B10 A10 A11 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 A12 A13 A14 A15 B15 B14 B13 B12 B11 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 M4A(3,5)-32/32 M4A(3,5)-32/32 M4A(3,5)-64/32 M4A(3,5)-64/32 M4A(3,5)-64/32 M4A(3,5)-64/32 17466G-026 I/O Cell PAL Block
44-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View 44-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 A12 A13 A14 A15 B15 B14 B13 B12 B11 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21 B10 I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 A10 A11 M4A(3,5)-32/32 M4A(3,5)-32/32 M4A(3,5)-64/32 M4A(3,5)-64/32 M4A(3,5)-64/32 M4A(3,5)-64/32 I/O Cell PAL Block
48-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View 48-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output V CC = Supply Voltage NC = No Connect TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out I/O12 I/O13 I/O14 I/O15 VCC NC GND I/O16 I/O17 I/O18 I/O19 I/O20 A12 A13 A14 A15 B15 B14 B13 B12 B11 I/O4 I/O3 I/O2 I/O1 I/O0 GND NC VCC I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 TDO GND NC CLK1/I1 TMS I/O23 I/O22 I/O21 B10 I/O5 I/O6 I/O7 TDI CLK0/I0 NC GND TCK I/O8 I/O9 I/O10 I/O11 A10 A11 M4A(3,5)-64/32 M4A(3,5)-64/32 M4A(3,5)-64/32 M4A(3,5)-64/32 I/O Cell PAL Block 17466G-028
100-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-96/48) Top View 100-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage NC = No Connect TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out NC TDI NC NC I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I0/CLK0 V CC GND I1/CLK1 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 NC NC TMS TCK NC GND NC NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC NC NC GND V CC I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 NC NC GND 100 GND NC NC I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 V CC GND NC NC NC I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 NC NC GND NC TDO NC NC NC I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I5/CLK3 GND V CC I4/CLK2 I/O35 I/O34 I/O33 I/O32 I/O31 I/O30 NC NC NC NC 17466G-029 I/O Cell PAL Block
100-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-128/64) Top View 100-Pin PQFP PIN DESIGNATIONS I/CLK = Input or Clock GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out TRST = Test Reset ENABLE = Program I/O7 A7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 V CC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND TDI I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 IO/CLK0 GND GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND GND 10031 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 ENABLE GND GND GND TD0 TRST I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND GND I3/CLK2 I/O47 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND GND I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 (83) (12) (13) (14) (15) (16) (17) (18) (19) (20) (23) (24) (25) (26) (27) (28) (29) (30) (31)(33) (34) (35) (36) (37) (38) (39) (40) (45) (46) (47) (48) (49) (50) (51) (52) (62) (61) (60) (59) (58) (57) (56) (55) (54) (41) (73) (72) (71) (70) (69) (68) (67) (66) (65) (10) (9) (8) (7) (6) (5) (4) (3) (82) (81) (80) (79) (78) (77) (76) (75) VCC VCC VCC VCC VCC VCC I/O Cell PAL Block 17466G-031
100-PIN TQFP CONNECTION DIAGRAM (M4A3-64/64 AND M4A(3,5)-128/64) Top View 100-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out TRST = Test Reset ENABLE = Program GND TDI I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 VCC GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND A11 A13 A15 B15 B13 B11 GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 V CC GND GND V CC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND B14 B12 B10 C10 C12 C14 100 GND GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND A14 A12 A10 D10 D12 D14 GND TDO TRST I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 ENABLE GND D11 D13 D15 C15 C13 C11 M4A3-64/64 M4A3-128/64 M4A5-128/64 17466G-032a I/O Cell PAL Block
100-BALL caBGA CONNECTION DIAGRAM (M4A3-128/64) Bottom View 100-Ball caBGA 1 0 987654321 A GND I/O63 I/O60 I/O57 H1 GND GND I/O1 I/O4 I/O7 A7 GND A B TRST GND I/O61 H5 I5 VCC I/O0 I/O6 A6 GND TDI I/O15 B7 B C I/O53 G5 TDO I/O62 I/O58 I/O56 I/O2 A2 GND I/O14 I/O13 I/O12 B4 C D I/O50 I/O55 G7 GND I/O59 I/O3 I/O5 I/O11 I/O10 B2 CLK0/I0 CLK3/I3 I/O9 B1 D E I/O49 I/O51 I/O54 G6 VCC I/O16 I/O20 I/O8 B0 VCC GND E F GND VCC I/O40 I/O52 I/O48 G0 VCC I/O22 I/O19 I/O17 C1 CLK1/I1 F G I/O41 F1 CLK2/I2 I/O42 I/O43 I/O37 I/O35 I/O27 D3 GND I/O23 I/O18 C2 G H I/O44 I/O45 I/O46 F6 GND I/O34 I/O24 I/O26 I/O30 D6 TCK I/O21 C5 H J I/O47 F7 ENABLE GND I/O38 I/O32 E0 VCC I2 I/O29 D5 GND TMS J K GND I/O39 I/O36 I/O33 E1 GND GND I/O25 I/O28 I/O31 D7 GND K 1 0 987654321 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell PAL Block Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program 17466G-100cabga
144-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-192/96) Top View 144-Pin TQFP PIN DESIGNATIONS CLK = Clock GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 17466G-033 GND TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 V CC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND V CC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 CLK1 GND V CC CLK2 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 V CC GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND V CC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 CLK0 GND V CC CLK3 I15 I14 I13 I/O79 I/O78 I/O77 I/O76 I/O75 I/O74 I/O73 I/O72 GND 108 107 106 105 104 103 102 101 100 GND TDO NC I/O71 I/O70 I/O69 I/O68 I/O67 I/O66 I/O65 I/O64 I12 V CC GND I11 I10 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND V CC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 NC GND I/O Cell PAL Block
144-BALL fpBGA CONNECTION DIAGRAM (M4A3-192/96) Bottom View 144-Ball fpBGA 1 2 1 1 1 0 987654321 A GND I/O95 I/O91 L3 I13 GBCLK3 I0 I/O2 I/O6 I/O8 I/O13 I/O15 B7 GND A B GND I/O94 I/O90 I/O88 L0 VCC I1 I/O3 I/O7 I/O10 I/O14 I/O31 D7 TDI B C GND TDO I/O93 L5 I14 GND I/O0 I/O4 A4 GND I/O12 I/O30 I/O27 I/O28 D4 C D I/O84 I/O82 I/O80 I/O92 L4 GBCLK0 I/O1 A1 VCC I/O11 I/O29 D5 I2 I/O25 I/O24 D0 D E I12 I/O87 I/O85 I/O81 I/O89 I/O5 I/O9 I/O26 I/O23 C7 I4 GND VCC E F I10 I11 GND I/086 I/O83 K3 I15 I3 GND I/O19 I/O20 I/O21 I/O22 C6 F G I/O75 I/O74 I/O73 I/O72 J0 VCC GND I7 I/O35 I/O38 I/O16 I/O17 I/O18 C2 G H I/O79 I/O78 I/O77 I/O76 I/O66 I/O57 I/O53 I/O41 I/O33 I/O37 I/O39 E7 VCC H J I/O64 I/O65 I1 VCC I/O69 I/O59 H3 VCC I/O49 G1 GBCLK2 I/O44 I/O32 I/O34 I/O36 E4 J K I/O68 I/O67 I/O70 I/O60 H4 GND I/O52 I/O48 G0 VCC I6 I/O45 F5 TCK TMS K L GND I/O71 I/O62 I/O58 I/O55 I/O51 G3 I9 GND I/O40 I/O42 I/O46 F6 GND L M GND I/O63 I/O61 I/O56 I/O54 I/O50 G2 I8 GBCLK1 I5 I/O43 I/O47 F7 GND M 1 2 1 1 1 0 987654321 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell PAL Block Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program m4a3.192.96_144bga
208-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-256/128 AND M4A3-256/160) Top View 208-Pin PQFP GND TDI I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND VCC VCC GND GND VCC VCC GND I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND VCC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 TMS TCK GND GND I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND VCC I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 CLK1 VCC GND GND VCC VCC GND GND VCC CLK2 I/O64 I/O66 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 VCC GND I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 GND 100 101 102 103 104 GND I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLK0 VCC GND GND VCC VCC GND GND VCC CLK3 I13 I12 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 VCC GND I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND GND TDO TRST I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 VCC GND I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 I/O96 I11 GND VCC VCC GND GND VCC VCC GND I10 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 ENABLE GND 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 RECOMMEND TO TIE TO VCC M4A(3, 5)- RECOMMEND TO TIE TO GND PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell PAL Block Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program M4A3-256/160 GND TDI I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 VCC GND I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 GND VCC I/O38 I/O39 I/O40 I/O41 I/O42 GND I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 GND VCC I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 TMS TCK GND C15 C14 C13 C12 C11 C10 D14 D12 E10 F10 F11 F12 F13 F14 F15 GND TDO NC I/O139 I/O138 I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 VCC GND I/O131 I/O130 I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 GND I/O122 I/O121 I/O120 I/O119 I/O118 VCC GND I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 GND VCC I/O107 I/O106 I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 NC GND N15 N14 N13 N12 N11 N10 M10 L12 L14 K10 K11 K12 K13 K14 K15 GND I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 I/O66 I/O67 GND VCC I/O68 I/O69 I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 CLK1 VCC GND I/O78 I/O79 I/O80 I/O81 GND VCC CLK2 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 I/O90 I/O91 VCC GND I/O92 I/O93 I/O94 I/O95 I/O96 I/O97 I/O98 I/O99 GND G15 G14 G13 G12 G11 G10 H14 H12 I12 I14 J10 J11 J12 J13 J14 J15 GND I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 CLK0 VCC GND I/O1 I/O0 I/O159 I/O158 GND VCC CLK3 I/O157 I/O156 I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 VCC GND I/O147 I/O146 I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 GND B15 B14 B13 B12 B11 B10 A14 A12 P12 P14 O10 O11 O12 O13 O14 O15 17466G-044
208-PIN PQFP CONNECTION DIAGRAM (M4A3-384/160 AND M4A3-512/160) Top View 208-Pin PQFP 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 RECOMMEND TO TIE TO VCC M4A3-512/160 RECOMMEND TO TIE TO GND PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell PAL Block Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program GND TDO NC I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 VCC GND I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 GND I/O120 I/O119 I/O118 I/O117 I/O116 VCC GND I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 GND VCC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 NC GND GND I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 GND VCC I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLK0 VCC GND I/O159 I/O158 I/O157 I/O156 GND VCC CLK3 I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 VCC GND I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 I/O139 I/O138 GND GND I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 GND VCC I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 CLK1 VCC GND I/O76 I/O77 I/O78 I/O79 GND VCC CLK2 I/O80 I/O81 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 VCC GND I/O90 I/O91 I/O92 I/O93 I/O94 I/O95 I/O96 I/O97 GND GND TDI I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 VCC GND I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 GND VCC I/O36 I/O37 I/O38 I/O39 I/O40 GND I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 GND VCC I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 TMS TCK GND GND TDI I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 VCC GND I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 GND VCC I/O36 I/O37 I/O38 I/O39 I/O40 GND I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 GND VCC I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 TMS TCK GND GND I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 GND VCC I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 CLK1 VCC GND I/O76 I/O77 I/O78 I/O79 GND VCC CLK2 I/O80 I/O81 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 VCC GND I/O90 I/O91 I/O92 I/O93 I/O94 I/O95 I/O96 I/O97 GND XH1 XH4 XH6 XH7 XE0 XE1 XE2 XE3 XE4 XE5 XE6 XE7 XG0 XG1 XG2 XG3 XG4 XG5 XG6 XG7 GND I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 GND VCC I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLK0 VCC GND I/O159 I/O158 I/O157 I/O156 GND VCC CLK3 I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 VCC GND I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 I/O139 I/O138 GND M4A3-384/160 XF7 XF6 XF5 XF4 XF3 XF2 XF1 XF0 XC7 XC6 XC5 XC4 XC3 XC2 XC1 XC0 XD5 XD3 XD2 XD0 XA0 XA2 XA5 XA7 XB0 XB1 XB2 XB3 XB4 XB5 XB6 XB7 GND TDO NC I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 VCC GND I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 GND I/O120 I/O119 I/O118 I/O117 I/O116 VCC GND I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 GND VCC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 NC GND XA1 XA4 XA6 XA7 XC0 XC1 XC2 XC3 XC4 XC5 XC6 XC7 XB0 XB1 XB2 XB3 XB4 XB5 XB6 XB7 XK7 XK6 XK5 XK4 XK3 XK2 XK1 XK0 XJ7 XJ6 XJ5 XJ4 XJ3 XJ2 XJ1 XJ0 XL5 XL3 XL2 XL0 XE0 XE2 XE5 XE7 XG0 XG1 XG2 XG3 XG4 XG5 XG6 XG7 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XP1 XP4 XP6 XP7 XN0 XN1 XN2 XN3 XN4 XN5 XN6 XN7 XO0 XO1 XO2 XO3 XO4 XO5 XO6 XO7 17466Ga-044
256-BALL BGA CONNECTION DIAGRAM (M4A(3,5)-256/128) Bottom View 256-Ball BGA GND GND I/O116 I/O120 I/O123 GND I12 GND N/C GND N/C N/C GND A B C D E F G H J K L M N P R T U V W Y A B C D E F G H J K L M N P R T U V W Y N/C I/O113 N/C I/O117 I/O119 I/O122 I/O125 I/O127 N/C CLK3 CLK0 N/C I/O0 I/O1 GND N/C VCC I/O112 I/O114 I/O118 I/O121 I/O126 N/C N/C N/C N/C I/O2 I/O6 I/O108 I/O109 TRST VCC TDI I/O115 VCC I/O124 I13 N/C N/C I/O3 VCC I/O105 I/O106 I/O111 VCC GND I/O103 I/O107 I/O110 I/O100 I/O102 I/O104 VCC I/O96 I/O98 I/O101 N/C GND N/C I/O97 I/O99 GND I11 N/C N/C GND N/C I10 GND N/C I/O94 I/O92 GND I/O82 VCC I/O79 I/O77 I/O73 I/O70 I/O66 N/C N/C N/C N/C I/O61 I/O57 GND 20 19 18 17 16 15 14 13 12 11 10 9 I/O95 I/O93 I/O90 N/C I/O91 I/O89 I/O86 VCC GND I/O88 I/O84 I/O81 I/O87 I/O85 I/O80 VCC N/C I/O83 ENABLE VCC TDO I/O76 VCC I/O67 N/C N/C I/O60 VCC GND N/C I/O78 I/O75 I/O72 I/O69 I/O65 I/O64 N/C CLK2 CLK1 I/O63 I/O59 I/O58 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 GND I/O74 I/O71 I/O68 GND GND N/C N/C GND I/O62 GND GND I/O4 I/O7 I/O5 I/O8 I/O11 I/O9 I/O12 I/O15 N/C TCK VCC VCC I/O18 C5 VCC I/O24 I/O29 D2 I2 N/C I/O35 I/O54 I/O50 I/O48 G7N/C VCC N/C VCC I/O51 TMS VCC I/O56 I/O55 I/O53 GND N/C N/C I/O10 GND GND I/O13 I/O14 GND VCC N/C GND I/O16 N/C N/C I/O17 I/O19 I/O20 I/O21 I/O22 GND I/O23 I/O25 I/O26 I/O27 I/O28 I/O30 I/O31 N/C GND N/C GND N/C GND I/O33 N/C GND VCC N/C GND I/O37 I/O34 I/O32 I/O41 I/O38 I/O36 I/O43 I/O39 GND I/O46 I/O42 I/O40 I/O47 I/O45 I/O44 I/O52 I/O49 N/C N/C GND GND PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell PAL Block Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program 17466G-045
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/192) Bottom View 256-Ball fpBGA PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell PAL Block Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 A I/O167 N15 I/O181 O13 I/O180 O12 I/O177 I/O174 I/O172 I/O191 P14 I/O186 I/O1 I/O3 A6 GCLK0 I/O9 I/O13 I/O15 I/O18 B10 I/O20 B12 A B I/O165 N13 I/O166 N14 I/O182 O14 I/O179 O11 I/O175 I/O173 I/O168 I/O187 I/O0 I/O5 A10 I/O7 A14 I/O10 I/O16 I/O19 B11 I/O21 B13 NC B C I/O163 N11 I/O164 N12 NC I/O183 O15 I/O178 O10 I/O170 I/O171 I/O189 P10 I/O184 I/O6 A12 I/O12 I/O14 I/O23 B15 I/O22 B14 TDI I/O39 C15 C D I/O158 I/O159 N7 TDO GND GND VCC GND VCC GND GND VCC GND VCC I/O17 I/O38 C14 I/O37 C13 D E I/O156 N4 NC I/O162 N10 VCC I/O160 I/O161 I/O190 P12 GCLK3 I/O188 I/O2 I/O8 B0 NC GND I/O36 C12 I/O35 C11 I/O31 C7 E F I/O152 I/O157 I/O155 N3 GND I/O154 I/O153 I/O176 I/O169 I/O185 I/O4 I/O11 I/O34 C10 VCC I/O32 I/O30 I/O29 C5 F G I/O147 I/O150 M12 I/O149 M10 VCC I/O148 I/O151 M14 VCC GND GND VCC I/O33 I/O28 C4 GND I/O26 I/O25 I/O47 D14 G H I/O144 I/O146 I/145 OM2 GND I/O136 I/O137 L2 GND VCC VCC GND I/O27 I/O24 C0 VCC I/O44 I/O43 I/O42 D4 H J I/O138 I/O139 I/O140 L8 GND I/O142 L12 I/O141 L10 GND VCC VCC GND I/O46 D12 I/O45 D10 GND I/O49 I/O48 I/O50 E4 J K I/O143 L14 I/O120 I/O121 K1 VCC I/O123 I/O122 K2 VCC GND GND VCC I/O41 I/O40 D0 VCC I/O55 E14 I/O54 E12 I/O56 F0 K L I/O124 I/O125 I/O127 K7 GND I/O130 K10 I/O126 I/O98 I/O91 I/O75 I/O77 I/O52 I/O51 E6 GND I/O59 I/O60 I/O57 F1 L M I/O128 I/O129 I/O131 K11 GND I/O107 I/O105 I/O100 I/O90 I/O74 I/O80 I/O83 G11 I/O53 E10 VCC I/O68 F12 I/O63 I/O58 F2 M N I/O132 K12 I/O133 K13 I/O135 K15 VCC GND VCC GND VCC GND GND VCC GND GND TCK I/O64 I/O61 F5 N P I/O134 K14 I/O117 J13 I/O118 J14 I/O119 J15 I/O108 I/O106 I/O101 I10 I/O89 I/O93 H10 I/O94 H12 I/O79 I/O84 G12 I/O87 G15 TMS I/O65 I/O62 F6 P R I/O116 J12 I/O115 J11 I/O112 I/O111 I/O104 I/O102 I12 I/O99 I/O96 I/O92 I/O72 I/O76 I/O81 I/O85 G13 I/O71 F15 I/O67 F11 I/O66 F10 R T I/O114 J10 I/O113 I/O110 I/O109 I/O103 I14 GCLK2 I/O97 I/O88 H0 GCLK1 I/O95 H14 I/O73 I/O78 I/O82 G10 I/O86 G14 I/O70 F14 I/O69 F13 T 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 17466G-047
256-BALL BGA CONNECTION DIAGRAM - (M4A3-384/192) Bottom View 256-Ball BGA GND GND I/O0 XG6 I/O1 XE7 I/O2 XE0 GND I/O3 XH6 GND I/O4 XH0 GND I/O5 I/O6 GND I/O7 A B C D E F G H J K L M N P R T U V W Y A B C D E F G H J K L M N P R T U V W Y I/O11 XF7 I/O12 XG7 I/O13 XG5 I/O14 XG3 I/O15 XG0 I/O16 XE1 I/O17 XE4 I/O18 XH5 I/O19 XH1 CLK3 CLK0 I/O20 I/O21 I/O22 GND I/O28 XF5 VCC I/O29 XG4 I/O30 XG1 I/O31 XE6 I/O32 XE5 I/O33 XE2 I/O34 XH4 I/O35 XH2 I/O36 I/O37 I/O38 I/O39 I/O44 XF6 I/O45 XF3 I/O46 XF4 VCC TDI I/O47 XG2 VCC I/O48 XE3 I/O49 XH7 I/O50 XH3 I/O51 I/O52 I/O53 VCC I/O58 XC6 I/O59 XC7 I/O60 XF2 VCC GND I/O64 XC5 I/O65 XF1 I/O66 XF0 I/O70 XC2 I/O71 XC3 I/O72 XC4 VCC I/O76 XD6 I/O77 XD7 I/O78 XC0 I/O79 XC1 GND I/O84 XD5 I/O85 XD4 I/O86 XD3 GND I/O90 XD2 I/O91 XD1 I/O92 XD0 GND I/O96 XA0 I/O97 XA1 I/O98 XA2 GND I/O102 XA3 I/O103 XA4 I/O104 XA7 GND I/O148 VCC I/O149 I/O150 I/O151 I/O152 I/O153 I/O154 I/O155 I/O156 I/O157 I/O158 I/O159 GND 20 19 18 17 16 15 14 13 12 11 10 9 I/O108 XA5 I/O109 XA6 I/O110 XB2 I/O111 XB3 I/O116 XB0 I/O117 XB1 I/O118 XB5 VCC GND I/O122 XB4 I/O123 I/O124 I/O128 XB7 I/O129 XB6 I/O130 VCC I/O134 I/O135 I/O136 VCC TDO I/O137 VCC I/O138 I/O139 I/O140 I/O141 I/O142 I/O143 VCC GND I/O164 I/O165 I/O166 I/O167 I/O168 I/O169 I/O170 I/O171 CLK2 CLK1 I/O172 I/O173 I/O174 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 GND I/O181 I/O182 I/O183 GND I/O184 GND I/O185 I/O186 GND I/O187 GND I/O188 GND I/O8 I/O9 I/O23 I/O24 I/O25 I/O40 I/O41 I/O42 I/O54 TCK VCC VCC I/O67 C0 VCC I/O80 I/O87 I/O93 I/O99 I/O105 I/O160 I/O161 I/O162 I/O112 G0 VCC I/O125 J1 VCC I/O144 TMS VCC I/O175 I/O176 I/O177 GND I/O189 I/O190 I/O10 GND GND I/O26 I/O27 GND VCC I/O43 GND I/O55 I/O56 I/O57 I/O61 I/O62 I/O63 I/O68 I/O69 GND I/O73 I/O74 I/O75 I/O81 I/O82 I/O83 I/O88 I/O89 GND I/O94 I/O95 GND I/O100 I/O101 GND I/O106 I/O107 GND VCC I/O163 GND I/O113 I/O114 I/O115 I/O119 I/O120 I/O121 I/O126 I/O127 GND I/O131 I/O132 I/O133 I/O145 I/O146 I/O147 I/O178 I/O179 I/O180 I/O191 GND GND PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO I/O Cell PAL Block Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out 17466G-046
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/128) Bottom View 256-Ball fpBGA 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 A TRST I/O117 I/O116 I/O113 I/O126 I/O124 P4 I12 NC NC NC CLK0 I/O1 I/O5 I/O7 I/O10 I/O12 B4 A B I/O110 I/O111 I/O118 I/O115 I/O127 I/O125 I/O120 P0 NC NC NC I1 I/O2 I/O8 I/O11 I/O13 B5 NC B C I/O108 I/O109 N5 NC I/O119 I/O114 I/O122 I/O123 P3 NC NC I0 I/O4 I/O6 I/O5 I/O14 B6 TDI I/O23 C7 C D NC I/O104 N0 TDO GND GND VCC GND VCC GND GND VCC GND VCC I/O9 I/O22 I/O21 C5 D E I/O102 M6 NC I/O107 N3 VCC I/O105 I/O106 N2 I13 CLK3 NC NC I/O0 A0 NC GND I/O20 I/O19 I/O31 D7 E F I/O98 I/O103 I/O101 M5 GND I/O100 I/O99 I/O112 I/O121 P1 NC NC I/O3 I/O18 C2 VCC I/O16 I/O30 I/O29 D5 F G NC I/O96 M0 I11 VCC NC I/O97 M1 VCC GND GND VCC I/O17 I/O28 D4 GND I/O26 I/O25 D1 I2 G H I/O88 L0 I10 I9 GND I/O89 I/O90 L2 GND VCC VCC GND I/O27 I/O24 D0 VCC NC NC NC H J I/O91 I/O92 I/O93 L5 GND I/O95 I/O94 L6 GND VCC VCC GND I3 NC GND NC NC NC J K NC NC NC VCC NC NC VCC GND GND VCC NC NC VCC I4 NC I/O32 E0 K L NC NC I/O80 K0 GND I/O83 K3 NC NC NC I/O59 I/O61 H5 NC NC GND I/O35 I/O36 I/O33 E1 L M I/O81 I/O82 I/O84 K4 GND I/O67 I/O65 I1 NC NC I/O58 I/O48 I/O51 G3 NC VCC I/O44 I/O39 I/O34 E2 M N I/O85 I/O86 K6 TENB VCC GND VCC GND VCC GND GND VCC GND GND TCK I/O40 I/O37 E5 N P I/O87 I/O77 I/O78 I/O79 I/O68 I/O66 I2 NC NC NC I6 I/O63 I/O52 I/O55 G7 TMS I/O41 I/O38 E6 P R I/O76 I/O75 I/O72 I/O71 I/O64 I0 I7 NC NC NC I/O56 I/O60 I/O49 I/O53 I/O47 I/O43 I/O42 F2 R T I/O74 I/O73 I/O70 I/O69 I5 I8 CLK2 NC NC CLK1 I5 I/O57 I/O62 I/O50 I/O54 I/O46 I/O45 F5 T 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell PAL Block Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program m4a3.256.128_256bga
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-384/192) Bottom View 256-Ball fpBGA 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 A I/O175 FX7 I/O181 GX5 I/O180 GX4 I/O177 GX1 I/O166 EX6 I/O164 EX4 I/O191 HX7 I/O186 HX2 I/O1 I/O3 A3 CLK0 I/O25 I/O29 I/O31 I/O10 I/O12 B4 A B I/O173 FX5 I/O174 FX6 I/O182 GX6 I/O179 GX3 I/O167 EX7 I/O165 EX5 I/O160 EX0 I/O187 HX3 I/O0 I/O5 I/O7 I/O26 I/O8 I/O11 I/O13 B5 N/C B C I/O171 FX3 I/O172 FX4 N/C I/O183 GX7 I/O178 GX2 I/O162 EX2 I/O163 EX3 I/O189 HX5 I/O184 HX0 I/O6 I/O28 I/O30 I/O15 I/O14 B6 TDI I/O23 C7 C D I/O150 CX6 I/O151 CX7 TDO GND GND VCC GND VCC GND GND VCC GND VCC I/O9 I/O22 I/O21 C5 D E I/O148 CX4 N/C I/O170 FX2 VCC I/O168 FX0 169 FX1 I/O190 HX6 CLK3 I/O188 HX4 I/O2 I/O24 D0 N/C GND I/O20 I/O19 I/O47 F7 E F I/O144 CX0 I/O149 CX5 I/O147 CX3 GND I/O146 CX2 I/O145 CX1 I/O176 GX0 I/O161 EX1 I/O185 HX1 I/O4 I/O27 I/O18 C2 VCC I/O16 I/O46 I/O45 F5 F G I/O155 DX3 I/O158 DX6 I/O157 DX5 VCC I/O156 DX4 I/O159 DX7 VCC GND GND VCC I/O17 I/O44 F4 GND I/O42 I/O41 I/O39 E7 G H I/O152 DX0 I/O154 DX2 I/O153 DX1 GND I/O128 AX0 I/O129 AX1 GND VCC VCC GND I/O43 I/O40 F0 VCC I/O36 I/O35 I/O34 E2 H J I/O130 AX2 I/O131 AX3 I/O132 AX4 GND I/O134 AX6 I/O133 AX5 GND VCC VCC GND I/O38 I/O37 E5 GND I/O57 I/O56 I/O58 H2 J K I/O135 AX7 I/O136 BX0 I/O137 BX1 VCC I/O139 BX3 I/O138 BX2 VCC GND GND VCC I/O33 I/O32 E0 VCC I/O63 I/O62 I/O48 G0 K L I/O140 BX4 I/O141 BX5 I/O143 BX7 GND I/O114 I/O142 BX6 I/O98 I/O91 I/O67 I/O69 I/O60 I/O59 H3 GND I/O51 I/O52 I/O49 G1 L M I/O112 I/O113 I/O115 O3 GND I/O123 I/O121 I/O100 I/O90 I/O66 I/O80 I/O83 I/O61 H5 VCC I/O76 I/O55 I/O50 G2 M N I/O116 I/O117 I/O119 O7 VCC GND VCC GND VCC GND GND VCC GND GND TCK I/O72 I/O53 G5 N P I/O118 I/O109 I/O110 I/O111 I/O124 I/O122 I/O101 I/O89 I/O93 I/O94 I/O71 I/O84 I/O87 K7 TMS I/O73 I/O54 G6 P R I/O108 I/O107 I/O104 I/O127 I/O120 I/O102 I/O99 I/O96 I/O92 I/O64 I/O68 I/O81 I/O85 I/O79 I/O75 I/O74 J2 R T I/O106 I/O105 I/O126 I/O125 I/O103 M7 CLK2 I/O97 I/O88 L0 CLK1 I/O95 I/O65 I/O70 I/O82 I/O86 I/O78 I/O77 J5 T 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell PAL Block Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program m4a3.384.192_256bga
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/192) Bottom View 256-Ball fpBGA 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 A I/O159 KX7 I/O181 OX5 I/O180 OX4 I/O177 OX1 I/O174 NX6 I/O172 NX4 I/O191 PX7 I/O186 PX2 I/O1 I/O3 A3 CLK0 I/O17 I/O21 I/O21 I/O10 I/O12 B4 A B I/O157 KX5 I/O158 KX6 I/O182 OX6 I/O179 OX3 I/O175 NX7 I/O173 NX5 I/O168 NX0 I/O187 PX3 I/O0 I/O5 I/O7 I/O18 I/O8 I/O11 I/O13 B5 N/C B C I/O155 KX3 I/O156 KX4 N/C I/O183 OX7 I/O178 OX2 I/O170 NX2 I/O171 NX3 I/O189 PX5 I/O184 PX0 I/O6 I/O20 I/O22 I/O15 I/O14 B6 TDI I/O39 F7 C D I/O150 JX6 I/O151 JX7 TDO GND GND VCC GND VCC GND GND VCC GND VCC I/O9 I/O38 I/O37 F5 D E I/O148 JX4 N/C I/O154 KX2 VCC I/O152 KX0 I/O153 KX1 I/O190 PX6 CLK3 I/O188 PX4 I/O2 I/O16 C0 N/C GND I/O36 I/O35 I/O47 G7 E F I/O144 JX0 I/O149 JX5 I/O147 JX3 GND I/O146 JX2 I/O145 JX1 I/O176 OX0 I/O169 NX1 I/O185 PX1 I/O4 I/O19 I/O34 F2 VCC I/O32 I/O46 I/O45 G5 F G I/O163 LX3 I/O166 LX6 I/O165 LX5 VCC I/O164 LX4 I/O167 LX7 VCC GND GND VCC I/O33 I/O44 G4 GND I/O42 I/O41 I/O31 E7 G H I/O160 LX0 I/O162 LX2 I/O161 LX1 GND I/O120 EX0 I/O121 EX1 GND VCC VCC GND I/O43 I/O40 G0 VCC I/O28 I/O27 I/O26 E2 H J I/O122 EX2 I/O123 EX3 I/O124 EX4 GND I/O126 EX6 I/O125 EX5 GND VCC VCC GND I/O30 I/O29 E5 GND I/O65 I/O64 I/O66 L2 J K I/O127 EX7 I/O136 GX0 I/O137 GX1 VCC I/O139 GX3 I/O138 GX2 VCC GND GND VCC I/O25 I/O24 E0 VCC I/O71 I/O70 I/O48 J0 K L I/O140 GX4 I/O141 GX5 I/O143 GX7 GND I/O130 FX2 I/O142 GX6 I/O98 AX2 I/O91 I/O75 I/O77 I/O68 I/O67 L3 GND I/O51 I/O52 I/O49 J1 L M I/O128 FX0 I/O129 FX1 I/O131 FX3 GND I/O115 CX3 I/O113 CX1 I/O100 AX4 I/O90 I/O74 I/O80 I/O83 I/O69 L5 VCC I/O60 I/O55 I/O50 J2 M N I/O132 FX4 I/O133 FX5 I/O135 FX7 VCC GND VCC GND VCC GND GND VCC GND GND TCK I/O56 I/O53 J5 N P I/O134 FX6 I/O109 BX5 I/O110 BX6 I/O111 BX7 I/O116 CX4 I/O114 CX2 I/O101 AX5 I/O89 I/O93 I/O94 I/O79 I/O84 I/O87 O7 TMS I/O57 I/O54 J6 P R I/O108 BX4 I/O107 BX3 I/O104 BX0 I/O119 CX7 I/O112 CX0 I/O102 AX6 I/O99 AX3 I/O96 AX0 I/O92 I/O72 I/O76 I/O81 I/O85 I/O63 I/O59 I/O58 K2 R T I/O106 BX2 I/O105 BX1 I/O118 CX6 I/O117 CX5 I/O103 AX7 CLK2 I/O97 AX1 I/O88 P0 CLK1 I/O95 I/O73 I/O78 I/O82 I/O86 I/O62 I/O61 K5 T 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654321 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell PAL Block Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program m4a3.512.192_256bga
388-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/256) Bottom View 388-Ball fpBGA 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A GND I/O243 OX3 I/O240 OX0 I/O241 OX1 I/O236 NX4 I/O231 MX7 I/O228 MX4 I/O226 MX2 I/O255 PX7 I/O251 PX3 I/O248 PX0 I/O0 I/O5 I/O6 I/O27 I/O30 I/O17 I/O22 I/O8 I/O10 B2 N/C GND A B N/C GND I/O245 OX5 I/O242 OX2 I/O238 NX6 I/O234 NX2 I/O232 NX0 I/O229 MX5 I/O224 MX0 I/O253 PX5 I/O249 PX1 I/O2 A2 CLK0 I/O26 I/O29 I/O31 I/O20 I/O9 I/O12 I/O13 B5 GND TDI B C I/O213 KX5 TDO GND I/O247 OX7 I/O244 OX4 I/O239 NX7 I/O235 NX3 I/O230 MX6 I/O227 MX3 CLK3 I/O250 PX2 I/O11 I/O7 I/O25 I/O16 I/O18 I/O23 I/O11 I/O15 B7 GND I/O47 I/O44 F4 C D I/O210 KX2 I/O212 KX4 I/O215 KX7 GND I/O246 OX6 VCC I/O237 NX5 I/O233 NX1 VCC I/O254 PX6 VCC I/O3 I/O24 D0 VCC I/O19 I/O21 C5 VCC I/O14 B6 GND I/O46 I/O43 I/O41 F1 D E I/O207 JX7 I/O209 KX1 I/O211 KX3 I/O214 KX6 I/O45 I/O42 I/O40 I/O54 G6 E F I/O203 JX3 I/O205 JX5 I/O208 KX0 VCC VCC I/O55 I/O52 I/O50 G2 F G I/O200 JX0 I/O202 JX2 I/O204 JX4 I/O206 JX6 VCC VCC N/C I/O225 MX1 I/O252 PX4 I/O4 I/O28 D4 N/C VCC VCC I/O53 I/O51 I/O49 I/O39 E7 G H I/O221 LX5 I/O222 LX6 I/O223 LX7 I/O201 JX1 VCC N/C GND GND GND GND GND GND N/C VCC I/O48 I/O38 I/O37 I/O36 E4 H J I/O218 LX2 I/O219 LX3 I/O220 LX4 VCC N/C GND GND GND GND GND GND GND GND N/C VCC I/O35 I/O34 I/O32 E0 J K I/O197 IX5 I/O198 IX6 I/O199 IX7 I/O216 LX0 I/O217 LX1 GND GND GND GND GND GND GND GND I/O33 I/O63 I/O62 I/O61 I/O60 H4 K L I/O192 IX0 I/O194 IX2 I/O195 IX3 I/O196 IX4 I/O193 IX1 GND GND GND GND GND GND GND GND I/O58 H2 VCC I/O59 I/O57 I/O56 H0 L M I/O184 HX0 I/O185 HX1 I/O187 HX3 VCC I/O186 HX2 GND GND GND GND GND GND GND GND I/O69 I/O67 I/O65 I/O66 I/O64 I0 M N I/O188 HX4 I/O189 HX5 I/O191 HX7 I/O190 HX6 I/O162 EX2 GND GND GND GND GND GND GND GND I/O89 I/O88 I/O71 I/O70 I/O68 I4 N P I/O160 EX0 I/O161 EX1 I/O163 EX3 VCC N/C GND GND GND GND GND GND GND GND N/C VCC I/O92 I/O91 I/O90 L2 P R I/O164 EX4 I/O165 EX5 I/O166 EX6 I/O177 GX1 VCC N/C GND GND GND GND GND GND N/C VCC I/O74 I/O95 I/O94 I/O93 L5 R T I/O167 EX7 I/O176 GX0 I/O179 GX3 I/O181 GX5 VCC VCC N/C I/O152 DX0 I/O131 AX3 I/O122 I/O98 M2 N/C VCC VCC I/O78 I/O76 I/O73 I/O72 J0 T U I/O178 GX2 I/O180 GX4 I/O183 GX7 VCC VCC I/O80 I/O77 I/O75 J3 U V I/O182 GX6 N/C I/O169 FX1 I/O172 FX4 I/O86 I/O83 I/O81 I/O79 J7 V W I/O168 FX0 I/O170 FX2 I/O173 FX5 GND I/O143 BX7 VCC I/O150 CX6 I/O145 CX1 VCC I/O153 DX1 I/O123 P3 VCC I/O96 M0 VCC I/O104 I/O111 N7 VCC I/O119 O7 GND I/O87 I/O84 I/O82 K2 W Y I/O171 FX3 I/O174 FX6 GND I/O141 BX5 I/O138 BX2 I/O136 BX0 I/O147 CX3 I/O158 DX6 I/O156 DX4 CLK2 I/O132 AX4 I/O121 I/O125 I/O99 I/O101 I/O106 I/O110 I/O115 I/O118 O6 GND TMS I/O85 K5 Y AA I/O175 FX7 GND I/O142 BX6 I/O140 BX4 I/O151 CX7 I/O149 CX5 I/O144 CX0 I/O157 DX5 I/O154 DX2 I/O134 AX6 I/O130 AX2 I/O128 AX0 CLK1 I/O127 I/O100 I/O103 I/O108 I/O109 I/O113 I/O116 O4 GND TCK AA AB GND N/C I/O139 BX3 I/O137 BX1 I/O148 CX4 I/O146 CX2 I/O159 DX7 I/O155 DX3 I/O135 AX7 I/O133 AX5 I/O129 AX1 I/O120 I/O124 I/O126 I/O97 I/O102 I/O105 I/O107 I/O112 I/O114 I/O117 O5 GND AB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE I/O Cell PAL Block Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program m4a3.512.256_388bga
ispMACH 4A PRODUCT ORDERING INFORMATION ispMACH 4A Devices Commercial and Industrial - 3.3V and 5V Lattice programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combination of: 1. Contact Factory for 6.5ns availability 128 FAMILY TYPE M4A3- = ispMACH 4A Family Low Voltage Advanced Feature (3.3-V VCC) M4A5- = ispMACH 4A Family Advanced Feature (5-V VCC) M4A3- 256 Y C MACROCELL DENSITY 32=32 Macrocells192 = 192 Macrocells 64=64 Macrocells256 = 256 Macrocells 96=96 Macrocells384 = 384 Macrocells 128=128 Macrocells512 = 512 Macrocells I/Os /32 = 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP /48 = 48 I/Os in 100-pin TQFP /64 = 64 I/Os in 100-pin TQFP , 100-pin PQFP , or 100-ball caBGA /96 = 96 I/Os in 144-pin TQFP or 144-ball fpBGA /128 = 128 I/Os in 208-pin PQFP , 256-ball BGA or 256-ball fpBGA /160 = 160 I/Os in 208-pin PQFP /192 = 192 I/Os in 256-ball BGA or 256-ball fpBGA /256 = 256 I/Os in 388-ball fpBGA OPERATING CONDITIONS C = Commercial (0 °C to +70°C) I = Industrial (-40 °C to +85°C) PACKAGE TYPE A = Ball Grid Array (BGA) J = Plastic Leaded Chip Carrier (PLCC) V = Thin Quad Flat Pack (TQFP) Y = Plastic Quad Flat Pack (PQFP) FA = Fine-pitch Ball Grid Array (fpBGA) CA = Chip-array Ball Grid Array (caBGA) SPEED -5 =5.0 ns t PD -55 =5.5 ns t PD -6 =6.0 ns t PD -65 =6.5 ns t PD -7 =7.5 ns t PD -10 =10 ns t PD -12 =12 ns t PD -14 =14 ns t PD 48 = 48-pin TQFP for M4A3-32/32 or M4A3-64/32 M4A5-32/32 or M4A5-64/32 3.3V Commercial Combinations M4A3-64/32 -55, -7, -10 JC, VC, VC48 M4A3-64/64 VC M4A3-96/48 VC M4A3-128/64 YC, VC, CAC M4A3-256/160 -7, -10 YC M4A3-256/1921 FAC M4A3-384/160 -65, -10, -12 YC M4A3-384/192 AC, FAC M4A3-512/160 -7, -10, -12 YC M4A3-512/192 FAC M4A3-512/256 FAC 3.3V Industrial Combinations M4A3-32/32 -7, -10, -12 JI, VI, VI48 M4A3-64/32 JI, VI, VI48 M4A3-64/64 VI M4A3-96/48 VI M4A3-128/64 YI, VI, CAI M4A3-192/96 -7, -10, -12 VI, FAI M4A3-256/128 YI, AI, FAI M4A3-256/160 -10, -12 YI M4A3-256/192 FAI M4A3-384/160 -10, -12, -14 YI M4A3-384/192 AI, FAI M4A3-512/160 YI M4A3-512/192 FAI M4A3-512/256 FAI
Most ispMACH devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, i.e., M4A3- 256/128-7YC-10YI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to confirm availability of specific valid combinations and to check on newly released combinations. Copyright © 2000 Lattice Semiconductor. All rights reserved. 5V Industrial Combinations M4A5-32/32 -7, -10, -12 JI, VI, VI48 M4A5-64/32 -7, -10, -12 JI, VI, VI48 M4A5-96/48 VI M4A5-128/64 YI, VI M4A5-256/128 -10, -12 YI, AI 5V Commercial Combinations M4A5-64/32 -55, -7, -10 JC, VC, VC48 M4A5-96/48 VC M4A5-128/64 YC, VC M4A5-256/128 -65, -7, -10 YC, AC