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CrossLink Automotive Family Data Sheet FPGA-DS-02013-1.7 December 2020

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02013-1.7 Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 3

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 5 Tables

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 FPGA-DS-02013-1.7 Acronyms in This Document A list of acronyms used in this document. Acronym Definition AR Augmented Reality BGA Ball Grid Array CMOS Complementary Metal Oxide Semiconductor CSI Camera Serial Interface DBI Display Bus Interface DPI Display Pixel Interface DSI Display Serial Interface EBR Embedded Block RAM ECLK Edge Clock FPD Flat Panel Display FPGA Field-Programmable Gate Array GPIO General-Purpose Input/Output HFOSC High Frequency Oscillator HMI Human Machine Interface I2C Inter-Integrated Circuit ISM Industrial, Scientific, Medical LFOSC Low Frequency Oscillator LUT Look Up Table LVCMOS Low-Voltage Complementary Metal Oxide Semiconductor LVDS Low-Voltage Differential Signaling LVTTL Low-Voltage Transistor-Transistor Logic MIPI Mobile Industry Processor Interface NVCM Non-Volatile Configuration Memory OTP One Time Programmable PCLK Primary Clock PFU Programmable Functional Unit PLL Phase Locked Loops PMU Power Management Unit RAM Random Access Memory Rx receive SLVS200 Scalable Low-Voltage Signaling SPI Serial Peripheral Interface TransFR Transparent Field Reconfiguration Tx Transmit UHD Ultra-High Definition VR Virtual Reality WLCSP Wafer Level Chip Scale Packaging

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 7 1. General Description CrossLink™ Automotive from Lattice Semiconductor is a programmable video bridging device that supports a variety of protocols and interfaces for mobile image sensors and displays. The device is based on Lattice mobile FPGA 40nm technology. It combines the extreme flexibility of an FPGA with the low power, low cost and small footprint of an ASIC. CrossLink Automotive supports video interfaces including MIPI® DPI, MIPI DBI, CMOS camera and display interfaces, OpenLDI, FPD-Link, FLATLINK, MIPI D-PHY, MIPI CSI-2, MIPI DSI, SLVS200, subLVDS, HiSPi and more. Lattice Semiconductor provides many pre-engineered IP (Intellectual Property) modules for CrossLink Automotive. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. The Lattice Diamond® design software allows large complex designs to be efficiently implemented using CrossLink Automotive. Synthesis library support for CrossLink Automotive devices is available for popular logic synthesis tools. The Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the CrossLink Automotive device. The tools extract the timing from the routing and back-annotate it into the design for timing verification. Interfaces on CrossLink Automotive provide a variety of bridging solutions for smart phone, tablets, wearables, VR, AR, Drone, Smart Home, HMI as well as adjacent ISM markets. The device is capable of supporting high-resolution, high-bandwidth content for mobile cameras and displays at 4k UHD and beyond. 1.1. Features  Ultra-low power  Sleep Mode Support  Normal Operation – From 5 mW to 150 mW  Small footprint page  80-ball ctfBGA (42 mm2)  80-ball ckfBGA (49 mm2)  81-ball csfBGA (20 mm2)  Programmable architecture  5936 LUTs  180 kb block RAM  47 kb distributed RAM  Two hardened 4-lane MIPI D-PHY interfaces  Transmit and receive  6 Gb/s per D-PHY interface  Programmable source synchronous I/O  MIPI D-PHY Rx, LVDS Rx, LVDS Tx, subLVDS Rx, SLVS200 Rx, HiSPi Rx  Up to 1200 Mb/s per I/O  Four high-speed clock inputs  Programmable CMOS I/O  LVTTL and LVCMOS  3.3 V, 2.5 V, 1.8 V, and 1.2 V (outputs)  LVCMOS differential outputs  Flexible device configuration  One Time Programmable (OTP) non-volatile configuration memory  Master SPI boot from external flash  Dual image booting supported  I2C programming  SPI programming  TransFR™ I/O for simple field updates  Enhanced system level support  Reveal logic analyzer  TraceID for system tracking  On-chip hardened I2C block  AEC-Q100 Tested and Qualified  Applications examples  Dual MIPI CSI-2 to Single MIPI CSI-2 Aggregation  Qual MIPI CSI-2 to Single MIPI CSI-2 Aggregation  Single MIPI DSI to Single MIPI DSI Repeater  Single MIPI CSI-2 to Single MIPI CSI-2 Repeater  Single MIPI DSI to Dual MIPI DSI Splitter  Single MIPI CSI-2 to Dual MIPI CSI-2 Splitter  MIPI DSI to OpenLDI/FPD-Link/LVDS Translator  OpenLDI/FPD-Link/LVDS to MIPI DSI Translator  MIPI DSI/CSI-2 to CMOS Translator  CMOS to MIPI DSI-2 Translator  subLVDS to MIPI CSI-2 Translator

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 FPGA-DS-02013-1.7 2. Product Feature Summary Table 2.1 lists CrossLink Automotive device information and packages. Table 2.1. CrossLink Automotive Feature Summary Device CrossLink Automotive LUTs 5936 sysMEM Blocks (9 kb) 20 Embedded Memory (kb) 180 Distributed RAM Bits (kb) 47 General Purpose PLL 1 NVCM Yes Embedded I2C 2 Oscillator (10 KHz) 1 Oscillator (48 MHz) 1 Hardened MIPI D-PHY 2* Packages (Footprint, Pitch) I/O 80 ctfBGA (6.5 x 6.5 mm2, 0.65 mm) 37 80 ckfBGA (7.0 x 7.0 mm2, 0.65 mm) 37 81 csfBGA (4.5 x 4.5 mm2, 0.5 mm) 37 *Note: Additional D-PHY Rx interfaces are available using programmable I/O.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 9 3. Architecture Overview CrossLink Automotive is designed as a flexible, chip-to-chip bridging solution which supports a wide variety of applications. The device provides three key building blocks for these bridging applications:  Up to two embedded Hard D-PHY blocks  Two banks of flexible programmable I/O supporting a variety of standards including D-PHY Rx, subLVDS, SLVS200, LVDS, and CMOS  A programmable logic core providing the LUTs, memory, and system resources to implement a wide range of bridging operations In addition to these blocks, CrossLink Automotive also provides key system resources including a Power Management Unit, flexible configuration interface, additional CMOS GPIO, and user I2C blocks. The block diagram for the device is shown in Figure 3.1. Programmable IO Rx: D-PHY/subLVDS/LVDS/ SLVS200/CMOS Tx: LVDS/CMOS Up to 1.07 Gb/s per Lane

14 IO/7 Pairs

Rx: D-PHY/subLVDS/LVDS/ SLVS200/CMOS Tx: LVDS/CMOS Up to 1.07 Gb/s per Lane

16 IO/8 Pairs

6 Gb/s

4 Data Lanes

1 Clock Lane

5,936 LUTs 180 kbits block RAM 47 kbits distributed RAM Enough FPGA resources to handle video: Muxing Merging Demuxing Arbitration Splitting Data Conversion Custom Protocol Design Power Management Unit I2C/SPI*GPIOs Figure 3.1. CrossLink Automotive Device Block Diagram *Note: I2C and SPI configuration modes are supported. User mode hardened I2C is also supported.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 11 Bidirectional clk and data TX – CLK HS ports RX - Data LP ports TX – Data HS ports TX – Data LP ports TX – CLK LP ports Control Ports PLL Ports MIPIDPHYA CLKP CLKN DP0 DN0 DP[3:1] DN[3:1] Dy_HSTXDATA[15:0] D0_TXLPP D0_TXLPN D0_TXLPEN CLK_TXHSGATE D0_RXLPP D0_RXLPN TXHSBYTECLK REFCLK LOCK * x = 1, 2, 3 y = 0, 1, 2, 3 D0_TXHSEN CLK_TXHSEN CLK_TXLPP CLK_TXLPN PDPLL USRSTDBY Dx_TXLPP Dx_TXLPN Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-DS-02013-1.7 Bidirectional clk and data TX – CLK HS ports TX – Data HS ports TX – Data LP ports TX – CLK LP ports Control Ports PLL Ports MIPIDPHYA CLKP CLKN DP0 DN0 DP[3:1] DN[3:1] Dy_HSTXDATA[15:0] D0_TXLPEN CLK_TXHSGATE TXHSBYTECLK REFCLK LOCK * x = 1, 2, 3 y = 0, 1, 2, 3 D0_TXHSEN CLK_TXHSEN CLK_TXLPEN CLK_TXLPP CLK_TXLPN PDPLL USRSTDBY Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 13 Bidirectional clk and data RX - Data HS ports RX - CLK HS ports RX - CLK LP ports RX - Data LP ports TX – Data LP ports Control Ports MIPIDPHYA CLKP CLKN DP0 DN0 DPx DNx D0_TXLPP D0_TXLPN D0_RXLPP D0_RXLPN * x = 1, 2, 3 y = 0, 1, 2, 3 USRSTDBY DO_RXHSEN DO_RXLPEN CLKRXHSEN CLKRXLPEN Dy_HSRXDATA[15:0] RXHSBYTECLK CLK_RXLPP CLKHSBYTE CLK_RXLPN CLK_CD D0_CD Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 FPGA-DS-02013-1.7 Bidirectional clk and data RX - Data HS ports RX - CLK HS ports RX - CLK LP ports RX - Data LP ports Control Ports MIPIDPHYA CLKP CLKN DP0 DN0 DPx DNx D0_RXLPP D0_RXLPN * x = 1, 2, 3 y = 0, 1, 2, 3 USRSTDBY Dy_HSRXDATA[15:0] RXHSBYTECLK D0_CD CLK_RXLPP CLKHSBYTE CLK_RXLPN CLK_CD Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 15 3.2. Programmable I/O Banks CrossLink Automotive devices provide programmable I/O which can be used to interface to a variety of external standards on Banks 1 and 2. CrossLink Automotive devices also provide dedicated CMOS GPIOs on Bank 0. Bank 0 GPIOs only support Single Data Rate (SDR) interfaces, while Bank 1 and Bank 2 support both SDR and Double Data Rate (DDR) interfaces. The GPIOs on Bank 0 do not include differential signaling capabilities. The location of the three Banks and their associated supplies are shown in Figure 3.2. Bank 0 features:  Support the following single ended standards  LVCMOS33  LVCMOS25  LVCMOS18  LVTTL33  Tri-state control for output  Input/output register blocks  Open-drain option and programmable input hysteresis  Internal pull-up resistors with configurable values of 3.3 kΩ, 6.8 kΩ and 10 kΩ Bank 1 and Bank 2 features:  Built-in support for the following differential standards  LVDS – Tx and Rx  SLVS200 – Rx  subLVDS – Rx  MIPI – Rx (both LP and HS receive on a single differential pair)  Support for the following single ended standards  LVCMOS33  LVCMOS25  LVCMOS18  LVCMOS12 (Outputs Only)  LVTTL33  Independent voltage levels per bank based on VCCIO supply  Input/output gearboxes per LVDS pair supporting several ratios for video interface applications  DDRX1, DDRX2, DDRX4, DDRX8 and DDRX71, DDRX141  Programmable delay cells to support edge-aligned and center-aligned interfaces  Programmable differential termination (~ 100 Ω) with dynamic enable control  Tri-state control for output  Input/output register blocks  Single-ended standards support open-drain and programmable input hysteresis  Optional weak pull-up resistors Table 3.1. CrossLink Automotive Output Support per Bank Basis OUTPUT BANK 0 BANK 1 BANK 2 LVCMOS12 —   LVCMOS18    LVCMOS25    LVCMOS33    LVTTL33    LVDS25 —  

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 FPGA-DS-02013-1.7 Table 3.2. CrossLink Automotive Input Support per Bank Basis INPUT BANK 0 BANK 1 BANK 2 LVCMOS12 — — — LVCMOS18    LVCMOS25    LVCMOS33    LVTTL33    LVDS25 —   MIPI D-PHY —   SLVS200 —   subLVDS —   3.3. sysI/O Buffers The CrossLink Automotive sysI/O buffers are distributed across three banks located at the bottom of the CrossLink Automotive device as shown in Figure 3.2. The sysI/O buffers support a wide variety of standards to interface to a range of systems including LVDS, subLVDS, LVCMOS, LVTTL, SLVS200 and MIPI. CrossLink Automotive supports single- ended buffers on all three banks. Differential I/O is supported on Bank 1 and Bank 2. 3.3.1. Programmable PULLMODE Settings The CrossLink Automotive sysI/O buffers offer multiple programmable value pull-up resistors on the three banks. The pull-up values are programmable on a “per-pin” basis. The default state of the I/O pins prior to configuration is tri- stated with a weak pull-up to VCCIOx. The I/O pins convert to the software user-defined settings after the configuration bitstream is successfully downloaded to the device. Each sysI/O buffer can be programmed with a 100 kΩ (weak pull- up), 3.3 kΩ, 6.8 kΩ, 10 kΩ or no pull-up. These pull-up options allow an I2C interface to be place on the majority of the pins on the device. These options are not exclusively for I2C protocol and may be used for other functions. 3.3.2. Output Drive Strength Each CrossLink Automotive output can have its own individual drive strength setting, but is predefined based on the VCCIOx setting. Table 3.3 lists the drive settings for the corresponding I/O type. Table 3.3. Drive Strength Values VCCIOx (V) I/O Type Drive Strength (mA)

3.3 LVTTL33 8

3.3 LVCMOS33 8

2.5 LVCMOS25 6

1.8 LVCMOS18 4

1.2 LVCMOS12 2

3.3.3. On-Chip Termination Bank 1 and bank 2 of CrossLink Automotive support LVDS, SLVS200 subLVDS and MIPI D-PHY inputs. These two banks support on-chip 100 Ω input differential termination between LVDS, SLVS200 and subLVDS pairs. For MIPI D-PHY inputs, the on-chip 100 Ω termination is dynamically enabled based on the HSSEL (High Speed Select) signal. See CrossLink High-Speed I/O Interface (FPGA-TN-02012) and CrossLink sysI/O Usage Guide (FPGA-TN-02016) for details.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 17 3.4. Programmable FPGA Fabric CrossLink Automotive is built around a programmable logic fabric consisting of 5936 four input lookup tables (LUT4) arranged alongside dedicated registers in Programmable Functional Units (PFU). These PFU blocks are the building blocks for logic, arithmetic, RAM and ROM functions. The PFU blocks are connected via a programmable routing network. The Lattice Diamond design software configures the PFU blocks and the programmable routing for each unique design. Interspersed between rows of PFU are rows of sysMEM™ Embedded Block RAM (EBR), with programmable I/O banks, embedded I2C and embedded MIPI D-PHY arranged on the top and bottom of the device as shown in Figure 3.7. PFUPFU PFU PFU PFUPFU PFU PFU PFU PFU MIPI D-PHY 0 MIPI D-PHY 1 Bank 2 Bank 1 Bank 0

4 EBR Blocks (9 kb each)

4 EBR Blocks (9 kb each) 4 EBR Blocks (9 kb each) 4 EBR Blocks (9 Kb each) 4 EBR Blocks (9 kb each)

Figure 3.7. CrossLink Automotive Device Simplified Block Diagram (Top Level) 3.4.1. PFU Blocks The core of the CrossLink Automotive device consists of PFU blocks. Each PFU block consists of four interconnected slices numbered 0 – 3 as shown in Figure 3.8. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing. The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic or ROM functions.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 19 LUT4 & CARRY* FF LUT4 & CARRY* FXA FXB FCO FF FCI CE CLK LSR For Slices 0 and 1, memory control signals are generated from Slice 2 as follows: WCK is CLK WRE is from LSR DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2 WAD [A:D] is a 4-bit address from slice 2 LUT input Notes: From Different Slice/PFU Figure 3.9. Slice Diagram

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 FPGA-DS-02013-1.7 SLICE 3 FXB FXA SLICE 2 FXB FXA SLICE 1 FXB FXA SLICE 0 FXB FXA LUT8 LUT5 LUT6 LUT5 LUT6 LUT5 LUT7 LUT5 LUT7 Output To Next PFU PFU Col(n-1) LUT7 Output From Previous PFU PFU Col(n) PFU Col(n+1) SLICE 3 FXB FXA SLICE 2 FXB FXA SLICE 1 FXB FXA SLICE 0 FXB FXA LUT8 LUT5 LUT6 LUT5 LUT6 LUT5 LUT7 LUT5 SLICE 3 FXB FXA SLICE 2 FXB FXA SLICE 1 FXB FXA SLICE 0 FXB FXA LUT8 LUT5 LUT6 LUT5 LUT6 LUT5 LUT7 LUT5 Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8 Table 3.4. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0 Multipurpose Input Input Multi-purpose M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCI Fast Carry-in1 Input Inter-slice signal FXA Intermediate signal to generate LUT6, LUT7 and LUT82 Input Inter-slice signal FXB Intermediate signal to generate LUT6, LUT7 and LUT82 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register outputs Output Inter-PFU signal FCO Fast carry chain output1 Notes: 1. See Table 4.9 for connection details. 2. Requires two adjacent PFUs.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 21 3.5. Clocking Structure The CrossLink Automotive device family provides resources to support a wide range of clocking requirements for programmable video bridging. These resources are described below. For details, refer to CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02015). 3.5.1. sysCLK PLL The CrossLink Automotive sysCLK PLL provides the ability to synthesis clock frequencies (See Table 4.14 for input frequency range). The PLL provides features such as dynamic selectable clock input, clock injection delay removal, independent dynamic output enable control, and programmable output phase adjustment. The architecture of the PLL is shown in Figure 3.11. Figure 3.11. CrossLink Automotive PLL Block Diagram Table 3.5 provides a description of the signals in the PLL block. Table 3.5. CrossLink Automotive PLL Port Definition Signal I/O Description CLKI I Input clock to PLL CLKFB I Feedback clock USRSTDBY I User port to put the PLL to sleep mode PHASESEL[1:0] I Select the output affected by Dynamic Phase adjustment PHASEDIR I Dynamic phase adjustment direction PHASESTEP I Dynamic phase adjustment step PHASELOADREG I Load dynamic phase adjustment values into PLL RST I Resets the whole PLL ENCLKOP I Enable PLL output CLKOP ENCLKOS I Enable PLL output CLKOS ENCLKOS2 I Enable PLL output CLKOS2 ENCLKOS3 I Enable PLL output CLKOS3 PLLWAKESYNC I Enable PLL switching from internal to user feedback path when PLL wake up CLKOP O PLL main output clock CLKOS O PLL output clock CLKOS2 O PLL output clock CLKOS3 O PLL output clock LOCK O PLL LOCK to CLKI, asynchronous signal. Active high indicates PLL lock

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 22 FPGA-DS-02013-1.7 3.5.2. Primary Clocks The primary clock routing network is made up of low skew clock routing resources with connectivity to every synchronous element of the device. Primary clock sources are selected in the center mux and distributed on the primary clock routing to clock the synchronous elements in the FPGA fabric. CrossLink Automotive family of devices provide up to eight unique global primary clocks. Primary clock sources are:  LVDS PIO pins  GPIO pins  PLL outputs  Clock dividers  Fabric internally generated clock signal  Divided down clock from DPHY  OSCI The routing clock structure is shown in Figure 3.12. Center Mux (8 PCLKs out) PLL Bank 0 GRPIO LVDS PIO GRPIO GPIO GPIO CLKDIV CLKDIV CLKDIV CLKDIV OSC CLK_HS_BYTE_0 HS_BYTE_CLK0 (RX and TX) CLK_HS_BYTE_0HS_BYTE_CLK1 (RX and TX) MIPI_DPHY0 MIPI_DPHY1 2 2 Fabric Entry Bank 2 Edge Clock s Edge Clock s Bank 1 Fabric Entry OSC_HF OSC_LF LVDS PIO LVDS PIO LVDS PIO LVDS PIO LVDS PIO Figure 3.12. CrossLink Automotive Clocking Structure 3.5.3. Edge Clocks The CrossLink Automotive device has Edge Clock (ECLK) at the bottom 2 banks (Bank 1 and Bank 2) of the device (Figure 3.2). The CrossLink Automotive device has 2 edge clocks per Programmable I/O bank. These clocks, which have low injection time and skew, are used to clock I/O registers. Edge clock resources are designed for high speed I/O interfaces with high fan-out capability. The sources of edge clocks are:  Dedicated Clock (PCLK) pins muxed with the DLLDEL output  PLL outputs (CLKOP and CLKOS)  Internal nodes ELCK input MUX collects all clock sources as shown in Figure 3.13 below. There are two ECLK Input MUXs, one on each bank. It drives the ECLK SYNC modules and the ECLK Clock Divider through a 2 to 1 MUX.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 FPGA-DS-02013-1.7 3.6. Embedded Block RAM Overview CrossLink Automotive devices contain sysMEM Embedded Block RAM (EBR). The EBR consists of a 9 kb RAM with memory core, dedicated input registers and output registers with separate clock and clock enable. Support for different memory configurations:  Single Port  True Dual Port  Pseudo Dual Port  ROM  FIFO (logic wrapper added automatically by design tools) Flexible customization features:  Initialization of RAM/ROM  Memory cascading (handled automatically by design tools)  Optional parity bit support  Byte-enable  Multiple block size options  RAM modes support optional Write Through or Read-Before-Write modes For details, refer to CrossLink Memory Usage Guide (FPGA-TN-02017). Table 3.8. sysMEM Block Configurations Memory Mode Memory Size Configurations Single Port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 True Dual Port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 Pseudo Dual Port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 ROM 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 25 3.7. Power Management Unit The embedded Power Management Unit (PMU) allows low-power Sleep State of the device. Figure 3.15 shows the block diagram of the PMU IP. When instantiated in the design, PMU is always on, and uses the low-speed clock from oscillator of the device to perform its operations. The typical use case for the PMU is through a user implemented state machine that controls the sleep and wake up of the device. The state machine implemented in the FPGA fabric identifies when the device needs to go into sleep mode, issues the command through PMU’s FPGA fabric interface, assigns the parameters for sleep (time to wake up and so on) and issues Sleep command. The device can be woken up externally using the PMU Wake-Up (USRWKUP) pin, or from the PMU Watch Dog Timer expiry or from I2C0 (address decoding detection or FIFO full in one of hardened I2C). Power Management Unit (PMU) Watch Dog Timer Power Control Unit External User Wake-up (USRWKUPN) PMU Wake-up from I2C0 (PMUWKUP)8-bit Addressable Fabric Interface PMU Sleep Signal, SLEEP PMU Control Register Watch Dog Timer User Mode Signals PMU Clock (From Oscillator) (PMUCLK) From FPGA Fabric Figure 3.15. CrossLink Automotive MIPI D-PHY Block 3.7.1. PMU State Machine PMU can place the device in two mutually exclusive states – Normal State and Sleep State. Figure 3.16 shows the PMU State Machine triggers for transition from one state to the other.  Normal state – All elements of the device are active to the extent required by the design. In this state, the device is at fully active and performing as required by the application. Note that the power consumption of the device is highest in this state.  Sleep state – The device is power gated such that the device is not operational. The configuration of the device and the EBR contents are retained; thus in Sleep mode, the device does not lose configuration SRAM and EBR contents. When it transitions to Normal state, device operates with these contents preserved. The PMU is active along with the associated GPIOs. The power consumption of the device is lowest in this state. This helps reduce the overall power consumption for the device.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 FPGA-DS-02013-1.7 Sleep Mode Normal Mode User Logic Initiated User I2C/ External Wake-up/ WDT Expiry Wake-up Figure 3.16. CrossLink Automotive PMU State Machine For more details, refer to Power Management and Calculation for CrossLink Devices (FPGA-TN-02018). 3.8. User I2C IP CrossLink Automotive devices have two I2C IP cores that can be configured either as an I2C master or as an I2C slave. The I2C0 core has pre-assigned pins, and supports PMU wakeup over I2C. The pins for the I2C1 interface are not pre-assigned – user can use any General Purpose I/O pins. The I2C cores support the following functionality:  Master and Slave operation  7-bit and 10-bit addressing  Multi-master arbitration support  Clock stretching  Up to 1 MHz data transfer speed  General call support  Optionally delaying input or output data, or both  Optional FIFO mode  Transmit FIFO size is 10 bits x 16 bytes, receive FIFO size is 10 bits x 32 bytes For further information on the User I2C, refer to CrossLink I2C Hardened IP Usage Guide (FPGA-TN-02019).

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 27 3.9. Programming and Configuration CrossLink Automotive is a SRAM-based programmable logic device that includes an internal Non-Volatile Configuration Memory (NVCM), as well as flexible SPI and I2C configuration modes. CrossLink Automotive provides four modes for loading the configuration data into the SRAM memory.  Self-Download (NVCM) mode – CrossLink Automotive retrieves bitstream from internal NVCM  Master SPI mode – CrossLink Automotive retrieves bitstream from an external SPI Flash  Slave SPI mode – System microprocessor writes bitstream to CrossLink Automotive through SPI port  Slave I2C mode – System microprocessor writes bitstream to CrossLink Automotive through I2C port CrossLink Automotive provides a set of sysCONFIG I/O pins to program and configure the FPGA. The sysCONFIG pins are grouped together to create ports (I2C, SSPI or MSPI) that are used to interact with the FPGA for programming, configuration, and access of resources inside the FPGA. The sysCONFIG pins (Table 3.9) in a configuration group may be active and used for programming the FPGA or they can be reconfigured to act as general purpose I/O. Table 3.9. CrossLink Automotive sysCONFIG Pins Pin Name Associated sysCONFIG Port CRESETB Self Download Mode/SSPI/MSPI/I2C CDONE Self Download Mode/SSPI/MSPI/I2C SPI_SCK/MCK/SDA SSPI/MSPI/I2C SPI_SS/CSN/SCL SSPI/MSPI/I2C MOSI SSPI/MSPI MISO SSPI/MSPI As external power ramps up, a Power On Reset (POR) circuit inside the FPGA becomes active. When POR conditions are met, the POR circuit releases an internal reset strobe, allowing the device to begin its initialization process. After CrossLink Automotive drives CDONE low, it enters the memory initialization phase where it clears all of the SRAM memory inside the FPGA. CrossLink Automotive remains in initialization state until the CRESETB pin is deasserted or after SSPI/SI2C activation code is received.  After CRESETB goes from low to high, the Configuration Logic puts the device into master auto booting mode where it boots either from the internal NVRAM or an external SPI boot PROM.  Holding the CRESETB low postpones the master auto booting event and allows the slave configuration ports (Slave SPI or Slave I2C) to detect a ‘Slave Active’ condition where the SPI or I2C Master sends an Activation Key code to CrossLink. An external SPI Master or I2C Master needs to write the Activation Key to the FPGA while CRESETB is held LOW and within 9.5 ms from Vcc min during power up to enter into one of the slave configuration modes.  Sources should not drive output to CrossLink until configuration has been completed to ensure CrossLink is in a known state. In addition to the flexible configuration modes, the CrossLink Automotive configuration engine supports the following special features:  TransFR (Transparent Field Reconfiguration) allowing users to update logic in field without interrupting system operation by freezing I/O states during configuration  Dual-Boot Support for primary and golden bitstreams provides automatic recovery from configuration failures  Security and One-Time Programmable (OTP) modes protect bitstream integrity and prevent read back  64-bit unique TraceID per device. For more information, refer to CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014).

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 28 FPGA-DS-02013-1.7 4. DC and Switching Characteristics 4.1. Absolute Maximum Ratings Table 4.1. Absolute Maximum Ratings 1, 2, 3 Symbol Parameter Min Max Unit VCC Core Supply Voltage –0.5 1.32 V VCCGPLL PLL Supply Voltage –0.5 1.32 V VCCAUX Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 2.5 V4 –0.5 2.75 V Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 3.3 V4 –0.5 3.63 V VCCIO I/O Driver Supply Voltage for Banks 0, 1, 2 –0.5 3.63 V — Input or I/O Transient Voltage Applied –0.5 3.63 V VCCA_DPHYx VCCPLL_DPHY MIPI D-PHY Supply Voltages –0.5 1.32 V — Voltage Applied on MIPI D-PHY Pins –0.5 1.32 V TA Storage Temperature (Ambient) –65 150 °C TJ Junction Temperature (TJ) — +125 °C Notes: 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. VCCAUX must be set to 2.5 V when an external I2C Master or SPI Master is used to program CrossLink’s NVCM. This restriction is not applicable for read access of the NVCM, such as Self-Download Mode, where the NVCM is already programmed and CrossLink retrieves the bitstream from the NVCM and programs it to the SRAM memory. 4.2. Recommended Operating Conditions Table 4.2. Recommended Operating Conditions 1, 2 Symbol Parameter Min Max Unit VCC Core Supply Voltage 1.14 1.26 V VCCGPLL PLL Supply Voltage 1.14 1.26 V VCCAUX3 Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 2.5 V4 2.375 2.625 V Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 3.3 V4 3.135 3.465 V VCCIO0 I/O Driver Supply Voltage for Bank 0 1.71 3.465 V VCCIO1/2 I/O Driver Supply Voltage for Bank 1, 2 1.14 3.465 V TJAUTO Junction Temperature, Automotive Operation –40 125 °C D-PHY External Power Supply VCCA_DPHYx Analog Supply Voltage for D-PHY 1.14 1.26 V VCCPLL_DPHYx PLL Supply voltage for D-PHY 1.14 1.26 V Notes: 1. For correct operation, all supplies must be held in their valid operation range. 2. Like power supplies, must be tied together if they are at the same supply voltage. Follow the noise filtering recommendations in CrossLink Hardware Checklist (FPGA-TN-02013). 3. VCCAUX can operate at either 2.5 V +/- 5% or 3.3 V +/- 5%. 4. VCCAUX must be set to 2.5 V when an external I2C Master or SPI Master is used to program CrossLink’s NVCM. This restriction is not applicable for read access of the NVCM such as Self-Download Mode where the NVCM is already programmed and CrossLink retrieves the bitstream from the NVCM and programs it to the SRAM memory.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 29 4.3. Power Supply Ramp Rates Over recommended operating conditions. Table 4.3. Power Supply Ramp Rates Symbol Parameter Min Max Unit tRAMP Power supply ramp rates for all power supplies 0.6 10 V/ms Note: Assume monotonic ramp rates. 4.4. Power-On-Reset Voltage Levels Over recommended operating conditions. Table 4.4. Power-On-Reset Voltage Levels1, 3 Symbol Parameter Min Max Unit VPORUP Power-On-Reset ramp up trip point (Monitoring VCC, VCCIO0, and VCCAUX) VCC 0.62 0.93 V VCCIO0 2 0.87 1.50 V VCCAUX 0.90 1.53 V VPORDN Power-On-Reset ramp down trip point (Monitoring VCC, VCCIO0, and VCCAUX) VCC — 0.79 V VCCIO0 2 — 1.50 V VCCAUX — 1.53 V Notes: 1. These POR ramp up trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. 2. Only VCCIO0 (Config Bank) has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up detection. 3. Configuration starts after VCC, VCCIO0 and VCCAUX reach VPORUP. For details, see tCONFIGURATION time in Table 4.21.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 30 FPGA-DS-02013-1.7 4.5. Power Supply Sequence Requirements CrossLink includes the following supplies:  VCC – Core supply  VCCGPLL – PLL supply  VCCAUX – Auxiliary supply  VCCIOX (includes VCCIO0, VCCIO1 and VCCIO2) – Bank I/O driver supply  VCCA_DPHYX (includes VCCA_DPHY0 and VCCA_DPHY1) – D-PHY analog supply  VCCPLL_DPHYX (includes VCCPLL_DPHY0 and VCCPLL_DPHY1) – D-PHY PLL supply It is recommended to bring up power supplies in the following order. Note that there is no specific timing delay between the power supplies. Power Supply Power-Up Sequence 1. VCCIOX supplies should be powered-up first, before the other supplies. VCCIOx must reach a level of 0.6 V before any subsequent power supplies are ramped. 2. VCC/VCCGPLL/VCCA_DPHYX/VCCPLL_DPHYX/VCCMU_DPHY1 should be powered-up next, after VCCIOX has reached a level of 0.6 V or higher. 3. VCCAUX must be powered up at the same time or after VCC. If VCC and VCCAUX are powered up concurrently, at no point can the VCCAUX supply be higher than VCC until the point when VCC has reached the minimum operating voltage. Power Supply Power-Down Sequence 1. There are no sequencing requirements for the Power-Down of the device. In the event that any supply is powered down below the POR trip point, then all supplies should be powered down before the device can be powered up following the above described sequence. 4.6. ESD Performance Refer to LIFMD Product Family Qualification Summary for complete qualification data, including ESD performance.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 31 4.7. DC Electrical Characteristics Over recommended operating conditions. Table 4.5. DC Electrical Characteristics Symbol Parameter Condition Min Typ Max Unit IIL, IIH 1, 4, 5 Input or I/O Leakage 0 ≤ VIN ≤ VCCIO −10 — +10 µA IPU4 Internal Pull-Up Current VCCIO = 1.8 V between 0 ≤ VIN ≤ 0.65 * VCCIO −3 — −31 µA VCCIO = 2.5 V between 0 ≤ VIN ≤ 0.65 * VCCIO −8 — −72 µA VCCIO = 3.3 V between 0 ≤ VIN ≤ 0.65 * VCCIO −11 — −128 µA 2 I/O Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.2 V, VCC = 1.2 V, VIO = 0 to VIH (MAX) — 6 — pF

2 Dedicated Input

VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.2 V, VCC = 1.2 V, VIO = 0 to VIH (MAX) — 6 — pF C32 MIPI D-PHY High Speed I/O Capacitance VCCIO = 2.5V,VCC = 1.2V, VCC*_DPHY = 1.2V , VIO = 0 to VIH (MAX) — 5 — pF VHYST

3 Hysteresis for Single-

VCCIO = 3.3 V, 2.5 V, 1.8 V VCC = 1.2 V, VIO = 0 to VIH (MAX) — 200 — mV Notes: 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA = 25 oC, f = 1.0 MHz. 3. Hysteresis is not available for VCCIO = 1.2 V. 4. Weak pull-up setting. Programmable pull-up resistors on Bank 0 will see higher current. Refer to CrossLink sysI/O Usage Guide (FPGA-TN-02016) for details on programmable pull-up resistors. 5. Input pins are clamped to VCCIO and GND by a diode. When input is higher than VCCIO, or lower than GND, the Input Leakage current will be higher than the IIL and IIH.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 32 FPGA-DS-02013-1.7 4.8. CrossLink Automotive Supply Current Over recommended operating conditions. Table 4.6. CrossLink Automotive Supply Current Symbol Parameter Typ Unit Normal Operation1 ICC Vcc Power Supply Current 7 mA ICCPLL PLL Power Supply Current 50 µA ICCAUX Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Current 3 mA ICCIOx Bank x Power Supply Current (per Bank) 60 µA ICCA_DPHYx VCCA_DPHYx Power Supply Current 8.5 mA ICCPLL_DPHYx VCCPLL_DPHYx Power Supply Current 1.5 mA Standby Current2 ICC_STDBY Vcc Power Supply Standby Current 4 mA ICCPLL_STDBY PLL Power Supply Standby Current 10 µA ICCAUX_STDBY Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Standby Current 0.2 mA ICCIOx_STDBY Bank Power Supply Standby Current (per Bank) 6 µA ICCA_DPHYx_STDBY VCCA_DPHYx Power Supply Standby Current 6 µA ICCPLL_DPHYx_STDBY VCCPLL_DPHYx Power Supply Standby Current 4 µA Sleep/Power Down Mode Current3 ICC_SLEEP Vcc Power Supply Sleep Current 0.2 mA ICCPLL_SLEEP PLL Power Supply Current 10 µA ICCAUX_SLEEP Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Current 20 µA ICCIOx_SLEEP Bank Power Supply Current (per Bank) 6 µA ICCA_DPHY_SLEEP VCCA_DPHYx Power Supply Sleep Current 6 µA ICCPLL_DPHY_SLEEP VCCPLL_DPHYx Power Supply Sleep Current 4 µA Notes: 1. Normal Operation 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions: a. TJ = 25 °C, all power supplies at nominal voltages. b. Typical processed device in ctfBGA80 package. c. To determine power for all other applications and operating conditions, use Power Calculator in Lattice Diamond design software 2. Standby Operation A typically processed device in ctfBGA80 package with “blank” pattern programmed. A “blank” pattern configures the part to the following conditions: a. All outputs are tri-stated, all inputs are held at either VCCIO, or GND. b. All clock inputs are at 0 MHz. c. TJ = 25 °C, all power supplies at nominal voltages. d. No pull-ups on I/O. 3. Sleep/Power Down Mode 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions: a. Design is put into Sleep/Power Down Mode with user logic powers down D-PHY, and enters into Sleep Mode in PMU. b. TJ = 25 °C, all power supplies at nominal voltages. c. Typical processed device in ctfBGA80 package. 4. To determine the CrossLink Automotive start-up peak current, use the Power Calculator tool in the Lattice Diamond design software.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 33 4.9. Power Management Unit (PMU) Timing Over recommended operating conditions. Table 4.7. PMU Timing* Symbol Parameter Device Max Unit tPMUWAKE Time for PMU to wake from Sleep mode All Devices 0.5 ms *Note: For details on PMU usage, refer to Power Management and Calculation for CrossLink Devices (FPGA-TN-02018). 4.10. sysI/O Recommended Operating Conditions Over recommended operating conditions. Table 4.8. sysI/O Recommended Operating Conditions1 Standard VCCIO Min Typ Max LVCMOS33/LVTTL33 3.135 3.30 3.465 LVCMOS25 2.375 2.50 2.625 LVCMOS18 1.710 1.80 1.890 LVCMOS12 (Output only)2 1.140 1.20 1.260 subLVDS (Input only) 1.710 1.80 1.890 2.375 2.50 2.625 3.135 3.30 3.465 SLVS200 (Input only)3 1.140 1.20 1.260 1.710 1.80 1.890 2.375 2.50 2.625 3.135 3.30 3.465 LVDS (Input only) 1.710 1.80 1.890 2.375 2.50 2.625 3.135 3.30 3.465 LVDS (Output only) 2.375 2.50 2.625 MIPI (Input only) 1.140 1.20 1.260 Note: 1. For input voltage compatibility, refer to CrossLink sysI/O Usage Guide (FPGA-TN-02016). 2. For VCCIO1 and VCCIO2 only. 3. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 34 FPGA-DS-02013-1.7 4.11. sysI/O Single-Ended DC Electrical Characteristics Over recommended operating conditions. Table 4.9. sysI/O Single-Ended DC Electrical Characteristics1 Input/Output Standard VIL VIH VOL Max (V) VOH Min (V) IOL (mA) IOH (mA) Min (V) Max (V) Min (V) Max (V) LVCMOS33/ 0.20 VCCIO − 0.2 0.1 –0.1 LVCMOS25 –0.3 0.7 1.7 VCCIO+0.2 0.40 VCCIO − 0.4 6 –6 0.20 VCCIO − 0.2 0.1 –0.1 LVCMOS18 –0.3 0.35 VCCIO 0.68 VCCIO VCCIO+0.2 0.40 VCCIO − 0.4 4 –4 0.20 VCCIO − 0.2 0.1 –0.1 LVCMOS122 (Output only) — — — — 0.40 VCCIO − 0.4 2 –2 0.20 VCCIO − 0.2 0.1 –0.1 Notes: 1. VCCIO in the table follows the VCCIO power rail setting of the respective bank. 2. For VCCIO1 and VCCIO2 only. 4.12. sysI/O Differential Electrical Characteristics 4.12.1. LVDS/subLVDS/SLVS200 Over recommended operating conditions. Table 4.10. LVDS/subLVDS1/SLVS2001, 2 Parameter Description Test Conditions Min Typ Max Unit VINP, VINN Input Voltage — 0.00 — 2.40 V VCM Input Common Mode Voltage Half the sum of the two inputs 0.05 — 2.35 V VTHD(LVDS) Differential Input Threshold ǀVINP - VINNǀ 100 — — mV VTHD(subLVDS) Differential Input Threshold ǀVINP - VINNǀ 90 — — mV VTHD(SLVS200) Differential Input Threshold ǀVINP - VINNǀ 70 — — mV IIN Input Current Normal Mode −10 — 10 µA Standby Mode −10 — 10 µA VOH Output High Voltage for VOP or VOM RT = 100 Ω — 1.43 1.60 V VOL Output Low Voltage for VOP or VOM RT = 100 Ω 0.90 1.08 — V VOD Output Voltage Differential |VOP - VOM|, RT = 100 Ω 250 350 450 mV ∆VOD Change in VOD between High and Low — — — 50 mV VOS Output Voltage Offset (Common Mode Voltage) (VOP + VOM)/2, RT = 100 Ω 1.080 1.250 1.400 V ∆VOS Change in VOS between H and L — — — 50 mV ISAB Output Short Circuit Current VOD = 0 V driver outputs shorted to each other — — 12 mA Notes: 1. Inputs only for subLVDS and SLVS200. 2. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 35 4.12.2. Hardened MIPI D-PHY I/O Over recommended operating conditions. Table 4.11. MIPI D-PHY Symbol Description Min Typ Max Unit Receiver High Speed VCMRX Common-Mode Voltage HS Receive Mode 70 — 330 mV VIDTH Differential Input High Threshold — — 70 mV VIDTL Differential Input Low Threshold −70 — — mV VIHHS Single-ended input High Voltage — — 460 mV VILHS Single-ended Input Low Voltage −40 — — mV VTERM-EN Single-ended Threshold for HS Termination Enable — — 450 mV ZID Differential Input Impedance 80 100 125 Ω Low Power VIH Logic 1 Input Voltage 880 — — mV VIL Logic 0 Input Voltage, not in ULP State — — 550 mV VIL-ULPS Logic 0 Input Voltage, in ULP State — — 300 mV VHYST Input Hysteresis 23.0 — — mV Transmitter High Speed VCMTX HS Transmit Static Common Mode Voltage 150 200 250 mV VOD HS Transmit Differential Voltage 140 200 270 mV VOHHS HS Single-ended Output High Voltage — — 360 mV ZOS Single-ended Output Impedance 40 50 62.5 Ω ΔZOS Single-ended Output Impedance Mismatch — — 10 % Low Power VOH Output High Voltage 1.1 1.2 1.3 V VOL Output Low Voltage −50 — 50 mV ZOLP Output Impedance in LP Mode 110 — — Ω

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 36 FPGA-DS-02013-1.7 4.13. CrossLink Automotive Maximum General Purpose I/O Buffer Speed Over recommended operating conditions. Table 4.12. CrossLink Automotive Maximum I/O Buffer Speed Buffer Description Max Unit Maximum Input Frequency LVDS25 LVDS, VCCIO = 2.5 V, VID = 200 mV 600 MHz subLVDS subLVDS, VCCIO = 2.5 V, VID = 150 mV 600 MHz MIPI D-PHY (HS Mode)6, 7 MIPI D-PHY 535 MHz MIPI D-PHY (LP Mode) 7 MIPI D-PHY 5 MHz SLVS2007 SLVS200, VCCIO=2.5 V 535 MHz LVCMOS33/LVTTL33 LVCMOS/LVTTL, VCCIO = 3.3 V 300 MHz LVCMOS25D Differential LVCMOS, VCCIO = 2.5 V 300 MHz LVCMOS25 LVCMOS, VCCIO = 2.5 V 300 MHz LVCMOS18 LVCMOS, VCCIO = 1.8 V 155 MHz Maximum Output Frequency LVDS25 LVDS, VCCIO = 2.5 V 555 MHz LVCMOS33/LVTTL33 LVCMOS/LVTTL, VCCIO = 3.3 V 300 MHz LVTTL33D Differential LVTTL, VCCIO = 3.3 V 300 MHz LVCMOS33D Differential LVCMOS, 3.3 V 300 MHz LVCMOS25 LVCMOS, 2.5 V 215 MHz LVCMOS25D Differential LVCMOS, 2.5 V 215 MHz LVCMOS18 LVCMOS, 1.8 V 155 MHz LVCMOS12 LVCMOS, VCCIO1/2 = 1.2 V 70 MHz Notes: 1. These maximum speeds are characterized but not tested on every device. 2. Maximum I/O speed for differential output standards emulated with resistors depends on the layout. 3. LVCMOS timing is measured with the load specified in Table 4.22. 4. Actual system operation may vary depending on user logic implementation. 5. Maximum data rate equals two times the clock rate when utilizing DDR. 6. This is the maximum MIPI D-PHY input rate on the programmable I/O banks 1 and 2. The hardened MIPI D-PHY input and output rates are described in Hardened MIPI D-PHY Performance section. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section. 7. Implement the following guideline for I/O placement when MIPI Rx inputs are present on the programmable I/O banks to ensure optimal performance: Bank 1 Bank 2 SLVS200/MIPI Rx on Bank 1 No LVCMOS Outputs No LVCMOS Outputs SLVS200/MIPI Rx on Bank 2 No LVCMOS Outputs No LVCMOS Outputs SLVS200/MIPI Rx on Bank 1 and Bank 2 No LVCMOS Outputs No LVCMOS Outputs  The Diamond Software PAR Design Strategy setting of LVCMOS12_18_ONLY (default) allows outputs as long as they are LVCMOS12 or LVCMOS18.  The Diamond Software PAR Design Strategy setting of LVCMOS_NOT_PERMITTED will cause an error in PAR regarding IO placement if there are any outputs in Bank 1 or Bank 2 when a MIPI Receiver interface is present.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 37 4.14. CrossLink Automotive External Switching Characteristics Over recommended operating conditions. Table 4.13. CrossLink Automotive External Switching Characteristics3, 4 Parameter Description Conditions –6 Unit Min Max Clocks Primary Clock fMAX_PRI Frequency for Primary Clock Tree — — 150 MHz tW_PRI Clock Pulse Width for Primary Clock — 0.8 — ns tSKEW_PRI Primary Clock Skew Within a Clock — — 450 ps Edge Clock fMAX_EDGE Frequency for Edge Clock Tree — — 600 MHz tW_EDGE Clock Pulse Width for Edge Clock — 0.783 — ns tSKEW_EDGE Edge Clock Skew Within a Bank — — 140 ps Generic DDR Interfaces1 Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Centered at General Purpose Pins (GDDRX8_RX/TX.ECLK.Centered or GDDRX4_RX/TX.ECLK.Centered or GDDRX2_RX/TX.ECLK.Centered) tSU_GDDRX2_4_8_CENTERED Input Data Set-Up Before CLK Rising and Falling edges — 0.167 — ns tHD_GDDRX2_4_8_CENTERED Input Data Hold After CLK Rising and Falling edges — 0.167 — ns tDVB_GDDRX2_4_8_CENTERED Output Data Valid Before CLK Output Rising and Falling edges Data Rate = 1.2 Gb/s5 0.297 — ns Other Data Rates5 −0.120 — ns+1/2UI tDVA_GDDRX2_4_8_CENTERED Output Data Valid After CLK Output Rising and Falling edges Data Rate = 1.2 Gb/s5 0.297 — ns Other Data Rates5 −0.120 — ns+1/2UI fMAX_GDDRX2_4_8_CENTERED Frequency for ECLK2 GDDRX2 — 300 MHz GDDRX4 and GDDRX8 — 600 MHz Generic DDRX1 I/O with Clock and Data Centered at General Purpose Pins (GDDRX1_RX/TX.SCLK.Centered tSU_GDDRX1_CENTERED Input Data Set-Up Before CLK Rising and Falling edges — 0.917 — ns tHD_GDDRX1_CENTERED Input Data Hold After CLK Rising and Falling edges — 0.917 — ns tDVB_GDDRX1_CENTERED Output Data Valid Before CLK Output Rising and Falling edges Data Rate = 300 Mb/s 1.217 — ns+1/2UI Other Data Rates −0.450 — ns+1/2UI tDVA_GDDRX1_CENTERED Output Data Valid After CLK Output Rising and Falling edges Data Rate = 300 Mb/s 1.217 — ns+1/2UI Other Data Rates −0.450 — ns+1/2UI fMAX_GDDRX1_CENTERED Frequency for PCLK2 — — 150 MHz Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Aligned at General Purpose Pins (GDDRX8_RX/TX.ECLK.Aligned or GDDRX4_RX/TX.ECLK.Aligned or GDDRX2_RX/TX.ECLK.Aligned) tSU_GDDRX2_4_8_ALIGNED Input Data Valid After CLK Rising and Falling edges Data Rate = 1.2 Gb/s5 — 0.188 ns Other Data Rates5 — −0.229 ns+1/2UI THD_GDDRX2_4_8_ALIGNED Input Data Hold After CLK Rising and Falling edges Data Rate = 1.2 Gb/s5 0.646 — ns Other Data Rates5 0.229 — ns+1/2UI tDIA_GDDRX2_4_8_ALIGNED Output Data Invalid After CLK Rising and Falling edges Output — — 0.120 ns tDIB_GDDRX2_4_8_ALIGNED Output Data Invalid Before CLK Output Rising and Falling edges — — 0.120 ns fMAX_GDDRX2_4_8_ALIGNED Frequency for ECLK2 GDDRX2 — 300 MHz GDDRX4 and GDDRX8 — 600 MHz

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 38 FPGA-DS-02013-1.7 Generic DDRX1 I/O with Clock and Data Aligned at General Purpose Pins (GDDRX1_RX/TX.SCLK.Aligned) TSU_GDDRX1_ALIGNED Input Data Valid After CLK Rising and Falling edges Data Rate = 300 Mb/s — 0.750 ns Other Data Rates — −0.917 ns+1/2UI THD_GDDRX1_ALIGNED Input Data Hold After CLK Rising and Falling edges Data Rate = 300 Mb/s 2.583 — ns Other Data Rates 0.916 — ns+1/2UI tDIA_GDDRX1_ALIGNED Output Data Invalid After CLK Rising and Falling edges Output — — 0.450 ns tDIB_GDDRX1_ALIGNED Output Data Invalid Before CLK Output Rising and Falling edges — — 0.450 ns fMAX_GDDRX1_ALIGNED Frequency for ECLK2 — — 150 MHz General Purpose I/O MIPI D-PHY Rx with 1:8 or 1:16 Gearing tSU_GDDRX_MP Input Data Set-Up Before CLK

900 Mb/s < Data Rate

≤ 1.07 Gb/s and VIDTH = 140 mV VIDTL = -140 mV 0.200 — UI

870 Mb/s < Data Rate

≤ 900 Mb/s and VIDTH = 140 mV VIDTL = -140 mV 0.160 — UI

450 Mb/s < Data Rate

≤ 870 Mb/s and VIDTH = 140 mV VIDTL = -140 mV 0.150 — UI Data Rate ≤ 450 Mb/s and VIDTH = 70 mV VIDTL = -70 mV 0.150 — UI tHO_GDDRX_MP Input Data Hold After CLK ≤ 1.07 Gb/s and VIDTH = 140 mV VIDTL = -140 mV 0.200 — UI ≤ 900 Mb/s and VIDTH = 140 mV VIDTL = -140 mV 0.160 — UI ≤ 870 Mb/s and VIDTH = 140 mV VIDTL = -140 mV 0.150 — UI Data Rate ≤ 450 Mb/s and VIDTH = 70 mV VIDTL = -70 mV 0.150 — UI fMAX_GDDRX_MP Frequency for ECLK2 — — 535 MHz Generic DDRX71 or DDRX141 Inputs (GDDRX71_RX.ECLK or GDDRX141_RX.ECLK) tRPBi_DVA Input Valid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) — — 0.3 UI — — −0.222 ns+ (i+ 1/2)*UI tRPBi_DVE Input Hold Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) — 0.700 — UI — 0.222 — ns+ (i+ 1/2)*UI fMAX_RX71_141 DDR71/DDR141 ECLK Frequency2 — — 450 MHz

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 39 Generic DDRX71 Outputs with Clock and Data Aligned at Pin (GDDRX71_TX.ECLK) tTPBi_DOV Data Output Valid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) — — 0.143 ns+i*UI tTPBi_DOI Data Output Invalid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) — −0.143 — ns+i*UI tTPBi_skew_UI Tx skew in UI — — 0.15 UI fMAX_TX71 DDR71 ECLK Frequency2 — — 525 MHz Generic DDRX141 Outputs with Clock and Data Aligned at Pin (GDDRX141_TX.ECLK) tTPBi_DOV Data Output Valid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) All Devices — 0.125 ns+i*UI tTPBi_DOI Data Output Invalid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) All Devices −0.125 — ns+i*UI tTPBi_skew_UI TX skew in UI All Devices — 0.15 UI fMAX_TX141 DDR141 ECLK Frequency2 — — 600 MHz Notes: 1. Generic DDRX8, DDRX71 and DDRX141 timing numbers based on LVDS I/O. 2. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment. 3. These numbers are generated using best case PLL location. 4. All numbers are generated with the Lattice Diamond design software. 5. Maximum data rate for GDDRX2 mode is 600 Mbps. tSU/tDVBDQ Rx CLK (in) Rx DATA (in) tHD/tDVADQ tSU/tDVBDQ tHD/tDVADQ Figure 4.1. Receiver RX.CLK.Centered Waveforms

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 41 Figure 4.5. DDRX71, DDRX141 Video Timing Waveforms

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 42 FPGA-DS-02013-1.7 4.15. sysCLOCK PLL Timing Over recommended operating conditions. Table 4.14. sysCLOCK PLL Timing Parameter Descriptions Conditions Min Max Unit fIN Input Clock Frequency (CLKI, CLKFB) — 10 400 MHz fPD Phase Detector Input Clock Frequency — 10 400 MHz fOUT Output Clock Frequency (CLKOP, CLKOS) — 4.6875 600 MHz fVCO PLL VCO Frequency — 600 1200 MHz AC Characteristics tDT Output Clock Duty Cycle — 45.0 55.5 % tPH Output Phase Accuracy — −5 5 % tOPJIT Output Clock Period Jitter3 fOUT ≥ 100 MHz — 100 ps p-p fOUT < 100 MHz — 0.025 UIPP Output Clock Cycle-to-Cycle Jitter3 fOUT ≥ 100 MHz — 200 ps p-p fOUT < 100 MHz — 0.05 UIPP Output Clock Phase Jitter fPD > 100 MHz — 200 ps p-p fPD < 100 MHz — 0.05 UIPP tSPO Static Phase Offset Divider ratio = integer — 400 ps p-p tLOCK

2 PLL Lock-in Time — — 15 ms

tUNLOCK PLL Unlock Time — — 50 ns tIPJIT Input Clock Period Jitter fPD ≥ 20 MHz — 500 ps p-p fPD < 20 MHz — 0.02 UIPP tHI Input Clock High Time 90% to 90% 0.5 — ns tLO Input Clock Low Time 10% to 10% 0.5 — ns Notes: 1. Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPD ≥ 10 MHz. For fPD < 10 MHz, the jitter numbers may not be met in certain conditions.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 43 4.16. Hardened MIPI D-PHY Performance Over recommended operating conditions. Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s) Parameter Description Min Max Unit tSU_MIPIX8 Input Data Setup before CLK 0.227 — UI tHO_MIPIX8 Input Data Hold after CLK 0.305 — UI tDVB_MIPIX8 Output Data Valid before CLK Output 0.200 — UI tDVA_MIPIX8 Output Data Valid after CLK Output 0.200 — UI Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s) Parameter Description Min Max Unit tSU_MIPIX4 Input Data Setup before CLK 0.200 — UI tHO_MIPIX4 Input Data Hold after CLK 0.200 — UI tDVB_MIPIX4 Output Data Valid before CLK Output 0.200 — UI tDVA_MIPIX4 Output Data Valid after CLK Output 0.200 — UI Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s) Parameter Description Min Max Unit tSU_MIPIX4 Input Data Setup before CLK 0.150 — UI tHO_MIPIX4 Input Data Hold after CLK 0.150 — UI tDVB_MIPIX4 Output Data Valid before CLK Output 0.150 — UI tDVA_MIPIX4 Output Data Valid after CLK Output 0.150 — UI 4.17. Internal Oscillators (HFOSC, LFOSC) Over recommended operating conditions. Table 4.18. Internal Oscillators Parameter Parameter Description Min Typ Max Unit fCLKHF HFOSC CLKK Clock Frequency 43.2 48 52.8 MHz fCLKLF LFOSC CLKK Clock Frequency 9 10 11 kHz DCHCLKHF HFOSC Duty Cycle (Clock High Period) 45 50 55 % DCHCLKLF LFOSC Duty Cycle (Clock High Period) 45 50 55 %

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 44 FPGA-DS-02013-1.7 4.18. User I2C1 Over recommended operating conditions. Table 4.19. User I2C1 Symbol Parameter STD Mode FAST Mode FAST Mode Plus2 Units Min Typ Max Min Typ Max Min Typ Max fscl SCL Clock Frequency — — 100 — — 400 — — 10002 kHz TDELAY Optional delay through delay block — 62 — — 62 — — 62 — ns Notes: 1. Refer to the I2C Specification for timing requirements. 2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I2C bus. Internal pull up may not be sufficient to support the maximum speed. 4.19. CrossLink Automotive sysCONFIG Port Timing Specifications Over recommended operating conditions. Table 4.20. CrossLink Automotive sysCONFIG Port Timing Specifications Symbol Parameter Min Max Unit All Configuration Mode tPRGM3 Minimum CRESETB LOW pulse width required to restart configuration (from falling edge to rising edge) 290 — ns Slave SPI1 fCCLK SPI_SCK Input Clock Frequency — 110 MHz tSTSU MOSI Setup Time 0.5 — ns tSTH MOSI Hold Time 2.0 — ns tSTCO SPI_SCK Falling Edge to Valid MISO Output — 13.3 ns tSCS Chip Select HIGH Time 25 — ns tSCSS Chip Select Setup Time 0.5 — ns tSCSH Chip Select Hold Time 0.5 — ns Master SPI fCCLK MCK Output Clock Frequency — 52.8 MHz I2C2 fMAX Maximum SCL Clock Frequency (Fast-Mode Plus) — 1 MHz Notes: 1. Refer to CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014), for timing requirements to enable CrossLink Automotive SSPI Mode. 2. Refer to the I2C specification for timing requirements when configuring with I2C port. 3. tPRGM minimum time does not apply when SLAVE_SPI_PORT, MASTER_SPI_PORT and I2C_PORT are disabled through Diamond Software. Contact your Lattice Sales Representatives for details. 4.20. SRAM Configuration Time from NVCM Over recommended operating conditions. Table 4.21. SRAM Configuration Time from NVCM Symbol Parameter Typ Unit TCONFIGURATION POR/CRESET_B to Device I/O Active* 83 ms *Note: Before and during configuration, the I/O are held in tristate with weak internal pullups enabled. I/O are released to user functionality when the device has finished configuration.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 46 FPGA-DS-02013-1.7 5. Pinout Information The pinout tables below correspond to CrossLink LIF-MD6000 Pinout Version 1.4. GND pins are referenced as VSS in Lattice Diamond Software. 5.1. ctfBGA80/ckfBGA80 Pinout Table 5.1. ctfBGA80/ckfBGA80 Pinout Pin Number Pin Function Bank Dual Function Differential A1 DPHY1_DN2 DPHY1 — Comp_OF_DPHY1_DP2 A2 DPHY1_DN0 DPHY1 — Comp_OF_DPHY1_DP0 A3 DPHY1_CKN DPHY1 — Comp_OF_DPHY1_CKP A4 DPHY1_DN1 DPHY1 — Comp_OF_DPHY1_DP1 A5 DPHY1_DN3 DPHY1 — Comp_OF_DPHY1_DP3 A6 DPHY0_DN2 DPHY0 — Comp_OF_DPHY0_DP2 A7 DPHY0_DN0 DPHY0 — Comp_OF_DPHY0_DP0 A8 DPHY0_CKN DPHY0 — Comp_OF_DPHY0_CKP A9 DPHY0_DN1 DPHY0 — Comp_OF_DPHY0_DP1 A10 DPHY0_DN3 DPHY0 — Comp_OF_DPHY0_DP3 B1 DPHY1_DP2 DPHY1 — True_OF_DPHY1_DN2 B2 DPHY1_DP0 DPHY1 — True_OF_DPHY1_DN0 B3 DPHY1_CKP DPHY1 — True_OF_DPHY1_CKN B4 DPHY1_DP1 DPHY1 — True_OF_DPHY1_DN1 B5 DPHY1_DP3 DPHY1 — True_OF_DPHY1_DN3 B6 DPHY0_DP2 DPHY0 — True_OF_DPHY0_DN2 B7 DPHY0_DP0 DPHY0 — True_OF_DPHY0_DN0 B8 DPHY0_CKP DPHY0 — True_OF_DPHY0_CKN B9 DPHY0_DP1 DPHY0 — True_OF_DPHY0_DN1 B10 DPHY0_DP3 DPHY0 — True_OF_DPHY0_DN3 C1 GND GND — — C2 GNDA_DPHY1 DPHY1 — — C9 GNDA_DPHY0 DPHY0 — — C10 GND GND — — D1 PB48 0 PCLKT0_1/USER_SCL — D2 VCCPLL_DPHY1 DPHY1 — — D4 VCCA_DPHY1 DPHY1 — — D5 VCCAUX VCCAUX — — D6 GNDPLL_DPHYx GND — — D7 VCCPLL_DPHY0 DPHY0 — — D9 PB16A 2 PCLKT2_0 True_OF_PB16B D10 PB16B 2 PCLKC2_0 Comp_OF_PB16A E1 PB34A 1 GR_PCLK1_0 True_OF_PB34B E2 PB34B 1 — Comp_OF_PB34A E4 VCC VCC — — E5 GND GND — — E6 VCC VCC — — E7 VCCA_DPHY0 DPHY0 — — E9 PB12A 2 GPLLT2_0 True_OF_PB12B E10 PB12B 2 GPLLC2_0 Comp_OF_PB12A

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 47 Pin Number Pin Function Bank Dual Function Differential F1 PB38A 1 — True_OF_PB38B F2 PB38B 1 — Comp_OF_PB38A F4 VCCIO0 0 — — F5 VCCIO1 1 — — F6 VCCIO2 2 — — F7 VCCIO2 2 — — F9 PB6A 2 GR_PCLK2_0 True_OF_PB6B F10 PB6B 2 — Comp_OF_PB6A G1 PB50 0 MOSI — G2 GND GND — — G4 VCCIO1 1 — — G5 GND GND — — G6 VCCGPLL VCCGPLL — — G7 GNDGPLL GND — — G9 PB2A 2 — True_OF_PB2B G10 PB2B 2 — Comp_OF_PB2A H1 PB52 0 SPI_SS/CSN/SCL — H2 CRESET_B 0 — — H9 PB2D 2 MIPI_CLKC2_0 Comp_OF_PB2C H10 PB2C 2 MIPI_CLKT2_0 True_OF_PB2D J1 PB53 0 SPI_SCK/MCK/SDA — J2 PB49 0 PMU_WKUPN/CDONE — J3 PB43D 1 — Comp_OF_PB43C J4 PB38D 1 — Comp_OF_PB38C J5 PB34D 1 MIPI_CLKC1_0 Comp_OF_PB34C J6 PB29D 1 PCLKC1_1 Comp_OF_PB29C J7 PB29A 1 PCLKT1_0 True_OF_PB29B J8 PB16D 2 PCLKC2_1 Comp_OF_PB16C J9 PB6D 2 — Comp_OF_PB6C J10 PB6C 2 — True_OF_PB6D K1 PB51 0 MISO — K2 PB47 0 PCLKT0_0/USER_SDA — K3 PB43C 1 — True_OF_PB43D K4 PB38C 1 — True_OF_PB38D K5 PB34C 1 MIPI_CLKT1_0 True_OF_PB34D K6 PB29C 1 PCLKT1_1 True_OF_PB29D K7 PB29B 1 PCLKC1_0 Comp_OF_PB29A K8 PB16C 2 PCLKT2_1 True_OF_PB16D K9 PB12D 2 — Comp_OF_PB12C K10 PB12C 2 — True_OF_PB12D

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 48 FPGA-DS-02013-1.7 5.2. csfBGA81 Pinout Table 5.2. csfBGA81 Pinout Pin Number Pin Function Bank Dual Function Differential A1 DPHY1_CKP DPHY1 — True_OF_DPHY1_CKN A2 DPHY1_CKN DPHY1 — Comp_OF_DPHY1_CKP A3 DPHY1_DP1 DPHY1 — True_OF_DPHY1_DN1 A4 DPHY1_DP3 DPHY1 — True_OF_DPHY1_DN3 A5 VCCA_DPHY1 DPHY1 — — A6 DPHY0_DN2 DPHY0 — Comp_OF_DPHY0_DP2 A7 DPHY0_DN0 DPHY0 — Comp_OF_DPHY0_DP0 A8 DPHY0_CKP DPHY0 — True_OF_DPHY0_CKN A9 DPHY0_CKN DPHY0 — Comp_OF_DPHY0_CKP B1 DPHY1_DP0 DPHY1 — True_OF_DPHY1_DN0 B2 DPHY1_DN0 DPHY1 — Comp_OF_DPHY1_DP0 B3 DPHY1_DN1 DPHY1 — Comp_OF_DPHY1_DP1 B4 DPHY1_DN3 DPHY1 — Comp_OF_DPHY1_DP3 B5 GNDPLL_DPHYx GND — — B6 DPHY0_DP2 DPHY0 — True_OF_DPHY0_DN2 B7 DPHY0_DP0 DPHY0 — True_OF_DPHY0_DN0 B8 DPHY0_DP1 DPHY0 — True_OF_DPHY0_DN1 B9 DPHY0_DN1 DPHY0 — Comp_OF_DPHY0_DP1 C1 DPHY1_DP2 DPHY1 — True_OF_DPHY1_DN2 C2 DPHY1_DN2 DPHY1 — Comp_OF_DPHY1_DP2 C3 GNDA_DPHY1 DPHY1 — — C4 VCCPLL_DPHY1 DPHY1 — — C5 GND GND — — C6 VCCPLL_DPHY0 DPHY0 — — C7 GNDA_DPHY0 DPHY0 — — C8 DPHY0_DP3 DPHY0 — True_OF_DPHY0_DN3 C9 DPHY0_DN3 DPHY0 — Comp_OF_DPHY0_DP3 D1 PB34A 1 GR_PCLK1_0 True_OF_PB34B D2 PB34B 1 — Comp_OF_PB34A D3 VCCA_DPHY1 DPHY1 — — D4 GND GND — — D5 VCCAUX VCCAUX — — D6 GND GND — — D7 VCCA_DPHY0 DPHY0 — — D8 PB16B 2 PCLKC2_0 Comp_OF_PB16A D9 PB16A 2 PCLKT2_0 True_OF_PB16B E1 PB38A 1 — True_OF_PB38B E2 PB38B 1 — Comp_OF_PB38A E3 VCC VCC — — E4 VCC VCC — — E5 GND GND — — E6 VCCIO2 2 — — E7 PB12B 2 GPLLC2_0 Comp_OF_PB12A E8 PB6B 2 — Comp_OF_PB6A E9 PB6A 2 GR_PCLK2_0 True_OF_PB6B

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 49 Pin Number Pin Function Bank Dual Function Differential F1 PB50 0 MOSI — F2 PB48 0 PCLKT0_1/USER_SCL — F3 VCCIO1 1 — — F4 GND GND — — F5 GNDGPLL GND — — F6 VCCIO2 2 — — F7 PB12A 2 GPLLT2_0 True_OF_PB12B F8 PB2B 2 — Comp_OF_PB2A F9 PB2A 2 — True_OF_PB2B G1 PB52 0 SPI_SS/CSN/SCL — G2 CRESET_B 0 — — G3 VCCIO0 0 — — G4 VCCIO1 1 — — G5 VCCGPLL VCCGPLL — — G6 PB29B 1 PCLKC1_0 Comp_OF_PB29A G7 PB29A 1 PCLKT1_0 True_OF_PB29B G8 PB2D 2 MIPI_CLKC2_0 Comp_OF_PB2C G9 PB2C 2 MIPI_CLKT2_0 True_OF_PB2D H1 PB53 0 SPI_SCK/MCK/SDA — H2 PB49 0 PMU_WKUPN/CDONE — H3 PB43D 1 — Comp_OF_PB43C H4 PB38D 1 — Comp_OF_PB38C H5 PB34D 1 MIPI_CLKC1_0 Comp_OF_PB34C H6 PB29D 1 PCLKC1_1 Comp_OF_PB29C H7 PB16D 2 PCLKC2_1 Comp_OF_PB16C H8 PB6D 2 — Comp_OF_PB6C H9 PB6C 2 — True_OF_PB6D J1 PB51 0 MISO — J2 PB47 0 PCLKT0_0/USER_SDA — J3 PB43C 1 — True_OF_PB43D J4 PB38C 1 — True_OF_PB38D J5 PB34C 1 MIPI_CLKT1_0 True_OF_PB34D J6 PB29C 1 PCLKT1_1 True_OF_PB29D J7 PB16C 2 PCLKT2_1 True_OF_PB16D J8 PB12D 2 — Comp_OF_PB12C J9 PB12C 2 — True_OF_PB12D

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 50 FPGA-DS-02013-1.7 5.3. Dual Function Pin Descriptions The following table describes the dual functions available to certain pins on the CrossLink Automotive device. These pins may alternatively be used as general purpose I/O when the described dual function is not enabled. Signal Name I/O Description General Purpose USER_SCL I/O User Slave I2C0 clock input and Master I2C0 clock output. Enables PMU wake-up via I2C0. USER_SDA I/O User Slave I2C0 data input and Master I2C0 data output. Enables PMU wakeup via I2C0. PMU_WKUPN — This pin wakes the PMU from sleep mode when toggled low. Clock Functions GPLL2_0[T, C]_IN I General Purpose PLL (GPLL) input pads: T = true and C = complement. These pins can be used to input a reference clock directly to the General Purpose PLL. These pins do not provide direct access to the primary clock network. GR_PCLK[Bank]0 I These pins provide a short General Routing path to the primary clock network, but should only be used when the design has used up all the PCLK pins. These pins should only be used for low speed clocks that is not sensitive to skew. Refer to CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02015) for details. PCLK[T/C][Bank]_[num] I/O General Purpose Primary CLK pads: [T/C] = True/Complement, [Bank] = (0, 1 and 2). These pins provide direct access to the primary and edge clock networks. MIPI_CLK[T/C][Bank]_0 I/O MIPI D-PHY Reference CLK pads: [T/C] = True/Complement, [Bank] = (0, 1 and 2). These pins can be used to input a reference clock directly to the D-PHY PLLs. These pins do not provide direct access to the primary clock network. Configuration CDONE I/O Open Drain pin. Indicates that the configuration sequence is complete, and the startup sequence is in progress. Holding CDONE delays configuration. SPI_SCK I Input Configuration Clock for configuring CrossLink Automotive in Slave SPI mode (SSPI). MCK O Output Configuration Clock for configuring CrossLink Automotive in Master SPI mode (MSPI). SPI_SS I Input Chip Select for configuring CrossLink Automotive in Slave SPI mode (SSPI). CSN O Output Chip Select for configuring CrossLink Automotive in Master SPI mode (MSPI). MOSI I/O Data Output when configuring CrossLink Automotive in Master SPI mode (MSPI), data input when configuring CrossLink Automotive in Slave SPI mode (SSPI). MISO I/O Data Input when configuring CrossLink Automotive in Master SPI mode (MSPI), data output when configuring CrossLink Automotive in Slave SPI mode (SSPI). SCL I/O Slave I2C clock I/O when configuring CrossLink Automotive in I2C mode. SDA I/O Slave I2C data I/O when configuring CrossLink Automotive in I2C mode.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 51 5.4. Dedicated Function Pin Descriptions Signal Name I/O Description Configuration CRESET_B I Configuration Reset, active LOW. MIPI D-PHY DPHY[num]_CK[P/N] I/O MIPI D-PHY Clock [num] = D-PHY 0 or 1, P = Positive, N = Negative. DPHY[num]_D[P/N][lane] I/O MIPI D-PHY Data [num] = D-PHY 0 or 1, P = Positive, N = Negative, Lane = data lane in the D-PHY block 0, 1, 2 or 3. 5.5. Pin Information Summary Pin Type CrossLink Automotive ctfBGA80 ckfBGA80 csfBGA81 Total General Purpose I/O 37 37 37 VCC/VCCIOx/VCCAUX/VCCGPLL 9 9 10 GND 6 6 6 D-PHY Clock/Data 20 20 20 D-PHY VCC 4 4 4 D-PHY GND 3 3 3 CRESETB 1 1 1 Total Balls 80 80 81 General Purpose I/O per Bank Bank 0 7 7 Bank 1 14 14 Bank 2 16 16 Total General Purpose Single Ended I/O 37 37 Differential I/O pairs per Bank Bank 0 0 0 Bank 1 7 7 Bank 2 8 8 Total General Purpose Differential I/O pairs 15 15

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 52 FPGA-DS-02013-1.7 6. CrossLink Automotive Part Number Description Logic Capacity 6000 = 6000 LUTs Speed Package JMG80 = 80-ball ctfBGA KMG80 = 80-ball ckfBGA MG81 = 81-ball csfBGA Device Family CrossLink Automotive FPGA LIA-MD XXXX-X XXXXX X Grade E = Automotive 6 = Fastest 6.1. Ordering Part Numbers Automotive Part Number Speed Package Pins Temp. Grade LUTs (K) LIA-MD6000-6JMG80E –6 Lead free ctfBGA 80 Automotive 5.9 LIA-MD6000-6KMG80E –6 Lead free ckfBGA 80 Automotive 5.9 LIA-MD6000-6MG81E -6 Lead free csfBGA 81 Automotive 5.9

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 53 References For more information, refer to the following technical notes:  CrossLink High-Speed I/O Interface (FPGA-TN-02012)  CrossLink Hardware Checklist (FPGA-TN-02013)  CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014)  CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02015)  CrossLink sysI/O Usage Guide (FPGA-TN-02016)  CrossLink Memory Usage Guide (FPGA-TN-02017)  Power Management and Calculation for CrossLink Devices (FPGA-TN-02018)  CrossLink I2C Hardened IP Usage Guide (FPGA-TN-02019)  Advanced CrossLink I2C Hardened IP Reference Guide (FPGA-TN-02020) For package information, refer to the following technical notes:  PCB Layout Recommendations for BGA Packages (FPGA-TN-02024, previously TN1074)  Solder Reflow Guide for Surface Mount Devices (FPGA-TN-12041, previously TN1076)  Wafer-Level Chip-Scale Package Guide (TN1242)  Thermal Management (FPGA-TN-02044)  Package Diagrams (FPGA-DS-02053) For further information on interface standards refer to the following websites:  JEDEC Standards (LVTTL, LVCMOS): www.jedec.org  MIPI Standards (D-PHY): www.mipi.org Technical Support For assistance, submit a technical support case at www.latticesemi.com/techsupport.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 54 FPGA-DS-02013-1.7

Revision History

Revision 1.7, December 2020 Section Change Summary Introduction Added AEC-Q100 Tested and Qualified in the Features section. Architecture Overview  Added information on pre-engineered IP modules in the MIPI D-PHY Blocks section.  Updated content of Programming and Configuration section. DC and Switching Characteristics  Updated footnotes in Table 4.4. Power-On-Reset Voltage Levels1, 3.  Added Power Supply Sequence Requirements section  Updated footnote 7 in Table 4.12. CrossLink Automotive Maximum I/O Buffer Speed. — Minor formatting/style adjustments. Revision 1.6, November 2019 Section Change Summary DC and Switching Characteristics  Added footnote to Table 4.9. sysI/O Single-Ended DC Electrical Characteristics.  Revised footnote 7 in Table 4.12. CrossLink Automotive Maximum I/O Buffer Speed. Revision 1.5, May 2019 Section Change Summary — Added Disclaimers section. DC and Switching Characteristics  Added Over recommended operating conditions to the following sections:  Power Supply Ramp Rates  Power-On-Reset Voltage Levels  Power Management Unit (PMU) Timing  sysI/O Recommended Operating Conditions  sysI/O Single-Ended DC Electrical Characteristics  Internal Oscillators (HFOSC, LFOSC)  User I2C  In LVDS/subLVDS/SLVS200, changed VOS Min and Max values in Table 4.10.  Reworded footnote 7 in Table 4.12.  Updated CrossLink Automotive External Switching Characteristics section.  Added Over recommended operating conditions.  Removed Generic SDR Interface section.  Revised tSU_GDDRX_MP and tHO_GDDRX_MP data.  Changed tRPBi_DVE Min value  Adjusted footnotes  Updated Hardened MIPI D-PHY Performance section.  Added Over recommended operating conditions.  Revised MIn values of some parameters in Table 4.15, Table 4.16, and Table 4.17.  Updated CrossLink Automotive sysCONFIG Port Timing Specifications section.  Added Over recommended operating conditions.  Revised Min value of tPRGM and added footnote 3 in Table 4.20. Pinout Information In the Dual Function Pin Descriptions table, added information to GR_PCLK[Bank]0 description. References  Updated document number of PCB Layout Recommendations for BGA Packages.  Fixed link to the Thermal Management document. Revision History Updated format. Back Cover Updated template.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 55 Revision 1.4, July 2018 Section Change Summary DC and Switching Characteristics  Updated Table 4.1. Absolute Maximum Ratings. Added footnote 4 to VCCAUX parameters.  Updated Table 4.2. Recommended Operating Conditions. Added footnote 4 to VCCAUX parameters. Revision 1.3, May 2018 Section Change Summary Features Added 81-ball cafBGA (20 mm2) in Features section. DC and Switching Characteristics Modified conditions for tSU_GDDRX_MP and tHO_GDDRX_MP in Table 4.13. Pinout Information  Added Table 5.1. ctfBGA80/ckfBGA80 Pinout caption.  Added csfBGA81 Pinout section and Table 5.2. csfBGA81 Pinout.  Added csfBGA81 column to the Pin Information Summary table. Ordering Part Numbers Updated Ordering Part Numbers. Revision 1.2, March 2018 Section Change Summary Acronyms in This Document Added entries to the section. Features  Changed footprint to 80-ball ctfBGA (42 mm2).  Removed Application Examples section and its associated references throughout the document. Product Feature Summary Updated packages in Table 2.1. Architecture Overview  Revised introductory paragraph.  Reordered the list of features supported by the hard D-PHY quads.  Added Figure 3.3 to Figure 3.6 to the MIPI D-PHY Blocks section.  Updated the Programmable I/O Banks section.  Added Bank 0 list of features.  Updated Programmable FPGA Fabric section.  Removed FPGA Fabric Overview header.  Added PFU Blocks section.  Added Slice section.  Moved Clocking Overview as a new Clocking Structure (heading 2) section and added contents.  Moved Embedded Block RAM Overview as a new (heading 2) section and added contents.  Removed System Resources section.  Moved Power Management Unit section under Embedded Block RAM Overview.  Removed Device Configuration section.  Moved User I2C IP as a new (heading 2) section. DC and Switching Characteristics  Added Programming and Configuration section.  Revised footnotes in Table 4.6.  Corrected alignment of arrows in Figure 4.4.  Revised Min and Max values in Table 4.15, Table 4.16, and Table 4.17.  Revised footnote in Table 4.20. Pinout Information  Added web link in Pinout Information section.  Placed captions to pinout table.

CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 56 FPGA-DS-02013-1.7 Revision 1.1, December 2017 Section Change Summary All Changed document status from preliminary to final. Acronyms in This Document Added this section. Features  Added 80-ball ckfBGA (49 mm2) under Small footprint.  Removed LVDS under Programmable CMOS I/O. Table 2.8, and Table 2.9. Architecture Overview  Moved Product Feature Summary from section to 2 to section 3. Added 80 ckfBGA (7.0 x 7.0 mm2, 1 mm) in Table 3.1. CrossLink Automotive Feature Summary.  Updated System Resources section.  Removed LVCMOS12 (Outputs Only) from CMOS GPIO (Bank 0) section.  Added information in Device Configuration section. DC and Switching Characteristics  Updated Table 5.1. Absolute Maximum Ratings.  Changed symbol from VCCPLL to VCCGPLL.  Removed VCC_DPHY, VCCA_DPHY, and VCCMU_DPHY symbol; added VCCA_DPHYx.  Updated Table 5.2. Recommended Operating Conditions.  Revised symbols to VCCGPLL, VCCAUX, and VCCIO0.  Added parameter to VCCAUX.  Added row of VCCIO1/2 symbol.  Removed row of VCC_DPHYx and VCCMU_DPHY1 symbol.  Revised note.  Updated Power-On-Reset Voltage Levels section. Added VPORDN to Table 5.4. Power- On-Reset Voltage Levels.and revised footnotes.  Updated LIFMD Product Family Qualification Summary link in ESD Performance section.  Removed VCCIO = 1.2 V between 0 ≤ VIN ≤ 0.65 * VCCIO condition from Table 5.5. DC Electrical Characteristics.  General update to Table 5.6. CrossLink Automotive Supply Current.  Removed Preliminary MIPI D-PHY Supply Current section.  Added notes to Table 5.8. sysI/O Recommended Operating Conditions.  Added note to Table 5.9. sysI/O Single-Ended DC Electrical Characteristics.  Added notes to Table 5.10. LVDS/subLVDS1/SLVS200.  General update to Table 5.12. CrossLink Automotive Maximum I/O Buffer Speed.  General update to Table 5.13. CrossLink Automotive External Switching Characteristics.  General update to Table 5.20. CrossLink Automotive sysCONFIG Port Timing Specifications.  Changed TREFRESH to TCONFIGURATION in Table 5.21. SRAM Configuration Time from NVCM. Pinout Information  Updated section introduction.  Updated section to ctfBGA80/cktBGA80 Pinout.  Updated Pin Information Summary section (general update). CrossLink Automotive Part Number Description Added KMG80 package. References Updated reference to the Solder Reflow Guide for Surface Mount Devices document. Revision 1.0, September 2016 Section Change Summary All First preliminary release.

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