LFMXO5-25 LATTICE | Alldatasheet
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FPGA-DS-02102-0.80 May 2022
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02102-0.80 Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur . The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 3
Contents
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-DS-02102-0.80
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 FPGA-DS-02102-0.80 Tables Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O (Over Recommended Operating Conditions)3 .. 57
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 7
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 FPGA-DS-02102-0.80 Acronyms in This Document A list of acronyms used in this document. Acronym Definition ADC Analog to Digital Converter AHB-Lite Advanced High-performance Bus-Lite AI Artificial Intelligence APB Advanced Peripheral Bus BGA Ball Grid Array CDR Clock and Data Recovery CRC Cycle Redundancy Code CRE Cryptographic Engine CSI-2 Camera Serial Interface-2 DCC Dynamic Clock Control DCS Dynamic Clock Select DDR Double Data Rate DLL Delay Locked Loops D-PHY Display Serial Interface-Physical Layer DRAM Dynamic Random Access Memory DSI Digital Serial Interface DSP Digital Signal Processing DTR Digital Temperature Readout EBR Embedded Block RAM ECC Error Correction Coding ECLK Edge Clock FD-SOI Fully Depleted Silicon on Insulator FFT Fast Fourier Transforms FIFO First In First Out FIR Finite Impulse Response HP High Performance HSP High Speed Port JTAG Joint Test Action Group LC Logic Cell LMMI Lattice Memory Mapped Interface LOL Loss of Lock LRAM Large RAM LVCMOS Low-Voltage Complementary Metal Oxide Semiconductor LVDS Low-Voltage Differential Signaling LVPECL Low Voltage Positive Emitter Coupled Logic LVTTL Low Voltage Transistor-Transistor Logic LUT Look Up Table MIPI Mobile Industry Processor Interface ML Machine Learning MLVDS Multipoint Low-Voltage Differential Signaling MSPS Million Samples per Second PCI Peripheral Component Interconnect PCS Physical Coding Sublayer PCLK Primary Clock PDPR Pseudo Dual Port RAM
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 9 Acronym Definition PFU Programmable Functional Unit PIC Programmable I/O Cells PLL Phase Locked Loops POR Power On Reset RAM Random Access Memory ROM Read Only Memory SAR Successive Approximation Resistor SEC Soft Error Correction SED Soft Error Detection SER Soft Error Rate SEU Single Event Upset SGMII Serial Gigabit Media Independent Interface SLVS Scalable Low-Voltage Signaling SPI Serial Peripheral Interface SPR Single Port RAM SRAM Static Random Access Memory subLVDS (Reduced Voltage) Low Voltage Differential Signaling TAP Test Access Port TDM Time Division Multiplexing UFM User Flash Memory
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 FPGA-DS-02102-0.80 1. General Description The MachXO5™-NX family of low-power FPGAs can be used in a wide range of applications, and are optimized for bridging, I/O expansion, and board control and management. It is built on Lattice Nexus FPGA platform, using low-power 28 nm FD-SOI technology. It combines the extreme flexibility of an FPGA with the low power and high reliability (due to the extreme low Soft Error Rate) of FD-SOI technology, and offers small footprint package options. The MachXO5-NX family supports a variety of interfaces including MIPI D-PHY (CSI-2, DSI), LVDS, SLVS, subLVDS, SGMII (Gigabit Ethernet), and more. It includes embedded flash memory for on-chip multi-boot and UFM. Processing features of the first MachXO5-NX device include 25k logic cells, 20 18 × 18 multipliers, 1.9 Mb of embedded memory (consisting of EBR and LRAM blocks), distributed memory, DRAM interfaces (supporting DDR3, DDR3L, LPDDR2, and LPDDR3 up to 1066 Mbps × 16 data width). The MachXO5-NX FPGA supports the fast configuration of its reconfigurable SRAM-based logic fabric, and ultra-fast configuration of its programmable sysI/O™ from on-chip Flash. To secure user designs, the MachXO5-NX security features include bitstream encryption, authentication, and password protection. In addition to the high reliability inherent to FD-SOI technology (due to its extreme low SER), active reliability features such as built -in frame-based SED/SEC (for SRAM-based logic fabric), and ECC (for EBR and LRAM) are also supported. Built-in ADC is available in each device for system monitoring functions. Lattice Radiant™ design software allows large complex user designs to be efficiently implemented on the MachXO5-NX FPGA family. Synthesis library support for MachXO5-NX devices is available for popular logic synthesis tools. Radiant tools use the synthesis tool output along with constraints from its floor planning tools, to place and route the user design in MachXO5-NX device. The tools extract timing from the routing, and back -annotate it into the design for timing verification. Lattice Semiconductor provides many pre-engineered Intellectual Property (IP) modules for the MachXO5-NX family. By using these configurable soft IP cores as standardized blocks, you are free to concentrate on the unique aspects of your design, increasing your productivity.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 11 1.1. Features Programmable Architecture 25k logic cells 20 18 × 18 multipliers (in sysDSP™ blocks) 1.9 Mb of embedded memory blocks (EBR, LRAM) 200 to 300 programmable sysI/O (High Performance and Wide Range I/O) Programmable sysI/O supports wide varieties of interfaces High Performance (HP) on bottom I/O dual rank Supports up to 1.8 V VCCIO Mixed voltage support (1.0 V, 1.2 V, 1.5 V, 1.8 V) High-speed differential up to 1.2 Gbps Supports soft D-PHY (Tx/Rx), LVDS 7:1 (Tx/Rx), SLVS (Tx/Rx), subLVDS (Rx) Supports SGMII (Gb Ethernet) – two channels (Tx/Rx) at 1.25 Gbps Dedicated DDR3/DDR3L and LPDDR2/LPDDR3 memory support with DQS logic, up to 1066 Mbps data-rate and ×16 data-width Wide Range (WR) on Left, Right and Top I/O Banks Supports up to 3.3 V VCCIO Mixed voltage support (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V) Programmable slew rate (slow, medium, fast) Controlled impedance mode Emulated LVDS support Hot socketing support Power Modes – Low-Power versus High-Performance modes User selectable Low-Power mode for power and/or thermal challenges High-Performance mode for faster processing Small footprint package options 14 mm × 14 mm to 17 mm × 17 mm package options Two channels of Clock Data Recovery (CDR) up to
1.25 Gbps to support SGMII using HP I/O
CDR for RX 8b/10b decoding Independent Loss of Lock (LOL) detector for each CDR block sysCLOCK™ analog PLLs Two for 25k LC device Six outputs per PLL Fractional N Programmable and dynamic phase control sysDSP enhanced DSP blocks Hardened pre-adder Dynamic Shift for AI/ML support Four 18 × 18, eight 9 × 9, two 18 × 36, or 36 × 36 multipliers Advanced 18 × 36, two 18 × 18, or four 8 × 8 MAC Flexible memory resources 1.4 Mb sysMEM™ Embedded Block RAM (EBR) Programmable width Error Correction Coding (ECC)* First Input First Output (FIFO) 80 kbit distributed RAM Large RAM Blocks 0.5 Mb per block Internal bus interface support APB control bus AHB-Lite for data bus AXI4-streaming Non-Volatile Configuration – Fast, Secure, On-chip multi-boot Embedded flash memory Single-chip, secure solution JTAG, SPI, I2C and I3C Ultrafast I/O configuration for instant-on support Multi-sectored UFM for customer data storage Bitstream Security Encryption Authentication Cryptographic engine Bitstream encryption – using AES-256 Bitstream authentication – using ECDSA Hashing algorithms – SHA, HMAC True Random Number Generator AES 128/256 Encryption Single Event Upset (SEU) Mitigation Support Extremely low Soft Error Rate (SER) due to FD-SOI technology Soft Error Detection – Embedded hard macro Soft Error Correction – Continuous user operation mode Soft Error Injection – Emulate SEU event to debug system error handling
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-DS-02102-0.80 Dual ADC – 1 MSPS, 12-bit SAR with Simultaneous Sampling* Two ADCs per device Three Continuous-time Comparators Simultaneous sampling System Level Support IEEE 1149.1 and IEEE 1532 compliant Reveal Logic Analyzer On-chip oscillator for initialization and general use 1.0 V core power supply *Note: Available in select speed grades. See Ordering Information. Table 1.1. MachXO5-NX Commercial/Industrial Family Selection Guide Notes: 1. Logic Cells = LUTs × 1.2 effectiveness. 2. In select speed grades. See Ordering Information. Device LFMXO5-25 Logic Cells1 25k Embedded Memory (EBR) Blocks (18 kb) 80 Embedded Memory (EBR) Bits (kb) 1,440 Distributed RAM Bits (kb) 184 Large Memory (LRAM) Blocks 1 Large Memory (LRAM) Bits (kb) 512
18 X 18 Multipliers 20
450 MHz High Frequency Oscillator 1
128 kHz Low Power Oscillator 1 GPLL 2 UFM (kb) 15,360 Packages (Size, Ball Pitch) Wide Range (WR) GPIO (Top/Left/Right Banks) / High Performance (HP) GPIOs (Bottom Banks) 256 BBG (14 mm × 14 mm, 0.8 mm) 160/40 400 BBG (17 mm × 17 mm, 0.8 mm) 252/48
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 13 2. Architecture 2.1. Overview Each MachXO5-NX device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) and rows of sysDSP Digital Signal Processing blocks, as shown in Figure 2.1. The MachXO5-25 device has one row of DSP blocks and contains four rows of sysMEM EBR blocks. In addition, MachXO5-25 device includes one Large SRAM block. The sysMEM EBR blocks are large, dedicated 18 kbit fast memory blocks and have built-in ECC and FIFO support. Each sysMEM block can be configured to a single, pseudo dual or true dual port memory in a variety of depths and widths as RAM or ROM. Each DSP block supports variety of multiplier, adder configurations with one 108-bit or two 54-bit accumulators supported, which are the building blocks for complex signal processing capabi lities. Each PIC block encompasses two PIO (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the MachXO5-NX devices are arranged in up to twelve banks allowing the implementation of a wide variety of I/O standards. The Wide Range (WR) I/O banks that are located in the top, left and right sides of the device provide flexible ranges of general purpose I/O configurations up to 3.3 V VCCIOs. The banks located in the bottom side of the device are dedicated to High Performance (HP) interfaces such as LVDS, MIPI, DDR3, LPDDR2, and LPDDR3 support up to 1.8 V VCCIOs. The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. The registers in PFU and sysI/O blocks in MachXO5-NX devices can be configured to be SET or RESET. After power up and the device is configured, it enters into user mode with these registers SET/RESET according to the configuration setting, allowing the device to enter to a known state for predictable system function. In addition, MachXO5-NX devices provide various system level hard IP functional and interface blocks such as I2C, SGMII/CDR, and ADC blocks. MachXO5-NX devices also provide security features to help secure user designs and deliver more robust reliability features to the user designs by using enhanced frame -based SED/SEC functions. Other blocks provided include PLLs, DLLs, and configuration functions. The PLL and DLL blocks are located at the corners of each device. MachXO5-NX devices also include Lattice Memory Mapped Interface (LMMI) which is a Lattice standardized interface for simple read and write operations to support controlling internal IPs. MachXO5-NX devices also provide multiple blocks of User Flash Memory (UFM). The UFM interface s to the core logic and completes the routing through the LMMI interface. The UFM space also provides the User Key storage for customer security functions. The UFM can also be accessed through the SPI, I 2C, and JTAG ports. Every device in the family has a JTAG port. This family also provides an on -chip oscillator and soft error detect (SED) capability. The MachXO5-NX devices use 1.0 V as their core voltage.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 FPGA-DS-02102-0.80 PLL OSC Non-volatile Configuration & Security I/O Bank (Bank 1) Large RAM ADC (2Ch) I/O Bank (Bank 2) I/O Bank (Bank 3) I/O Bank (Bank 6) I/O Bank (Bank 5) PLL I/O Bank (Bank 9) I/O Bank (Bank 8) CDR (2Ch) I/O Bank (Bank 0) I/O Bank (Bank 7) I/O Bank (Bank 4) On-chip User Flash Figure 2.1. Simplified Block Diagram, MachXO5-25 Device (Top Level)
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 FPGA-DS-02102-0.80 LUT5 and Carry Figure 2.3. Slice Diagram
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 17 Note: In RAM mode, LUT4s use the following signals: QWD0/1 QWDN0/1 QWAS00~03, QWAS10~13 LUT4 LUT4 SEL Figure 2.4. Slice Configuration for LUT4 and LUT5 Table 2.2. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Data signal M0, M1 Direct input to FF from fabric Input Control signal SEL LUT5 mux control input Input Data signal DI0, DI1 Inputs to FF from LUT4 F0/F1 outputs Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLKIN System Clock Input Inter-PFU signal FCI Fast Carry-in1 Output Data signals F0 LUT4/LUT5 output signal Output Data signals F1 LUT4 output signal Output Data signals Q0, Q1 Register outputs Output Inter-PFU signal FCO Fast carry chain output1 Note: 1. See Figure 2.3 for connection details. 2.2.2. Modes of Operation Slices 0-2 have up to four potential modes of operation: Logic, Ripple, RAM and ROM. Slice 3 can be used in Logic, Ripple, or ROM modes, but not needed for RAM mode.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 FPGA-DS-02102-0.80 2.2.2.1. Logic Mode In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. 2.2.2.2. Ripple Mode Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice: Addition 2-bit Subtraction 2-bit Add/Subtract 2-bit using dynamic control Up counter 2-bit Down counter 2-bit Up/Down counter with asynchronous clear 2-bit using dynamic control Up/Down counter with preload (sync) 2-bit using dynamic control Comparator functions of A and B inputs 2-bit A greater-than-or-equal-to B A not-equal-to B A less-than-or-equal-to B Up/Down counter with A greater-than-or-equal-to B comparator 2-bit using dynamic control Up/Down counter with A less-than-or-equal-to B comparator 2-bit using dynamic control Multiplier support Ai*Bj+1 + Ai+1*Bj in one logic cell with 2 logic cells per slice Serial divider 2-bit mantissa, shift 1bit/cycle Serial multiplier 2-bit, shift 1bit/cycle or 2bit/cycle Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode), two additional signals, Carry Generate and Carry Propagate, are generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices. 2.2.2.3. RAM Mode In this mode, a 16 × 4-bit distributed single or pseudo dual port RAM can be constructed in one PFU using each LUT block in Slice 0 and Slice 1 as a 16 × 2-bit memory in each slice. Slice 2 is used to provide memory address and control signals. MachXO5-NX devices support distributed memory initialization. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 lists the number of slices required to implement different distributed RAM primitives. For more information about using RAM in MachXO5-NX devices, refer to Memory Usage Guide for Nexus Platform (FPGA-TN-02094). Table 2.3. Number of Slices Required to Implement Distributed RAM SPR 16 X 4 PDPR 16 X 4 Number of slices 3 3 Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM 2.2.2.4. ROM Mode ROM mode uses the LUT logic; hence, Slice 0 through Slice 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. For more information, refer to Memory Usage Guide for Nexus Platform (FPGA-TN-02094).
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 19 2.3. Routing There are many resources provided in the MachXO5-NX devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The MachXO5-NX family has an enhanced routing architecture that produces a compact design. The Lattice Radiant software tool suites take the output of the synthesis tool and places and routes the design. 2.3.1. Clocking Structure The MachXO5-NX clocking structure consists of: clock synthesis blocks, sysCLOCK PLL; balanced clock tree networks, PCLK and ECLK; and efficient clock logic modules, Clock Dividers (PCLKDIV and ECLKDIV) and Dynamic Clock Select (DCS), Dynamic Clock Control (DCC), and DLL. Each of these functions is described as follow. 2.3.2. Global PLL The Global PLLs (GPLL) provide the ability to synthesize clock frequencies. The devices in the MachXO5-NX family support two full-featured General Purpose GPLLs. The Global PLLs provide the ability to synthesize clock frequencies. The architecture of the GPLL is shown in Figure 2.5. A description of the GPLL functionality follows. REFCLK is the reference frequency input to the PLL and its source can come from external CLK inputs or from internal routing. The CLKI input feeds into the input Clock Divider block. CLKFB is the feedback signal to the GPLL which can come from internal feedback path or routing. The feedback divider is used to multiply the reference frequency and thus synthesize a higher or lower frequency clock output. The PLL has six clock outputs CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4 , and CLKOS5. Each output has its own output divider, thus allowing the GPLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. Each GPLL output can be used to drive the primary clock or edge clock networks. The setup and hold times of the device can be improved by programming a phase shift into the output clocks which advances or delays the output clock with reference to the un-shifted output clock. This phase shift can either be programmed during configuration or be adjusted dynamically using the DIRSEL, DIR, DYNROTATE, and LOADREG ports. The LOCK signal is asserted when the GPLL determines it has achieved lock and deasserted if a loss of lock is detected.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 FPGA-DS-02102-0.80 (To bypass muxes) Figure 2.5. General Purpose PLL Diagram For more details on the PLL, you can refer to the sysCLOCK PLL Usage Guide for Nexus Platform (FPGA-TN-02095). 2.3.3. Clock Distribution Network There are two main clock distribution networks for any member of the MachXO5-NX product family, namely Primary Clock (PCLK) and Edge Clock (ECLK). These clock networks can be driven from many different sources, such as Clock Pins, PLL outputs, DLLDEL outputs, Clock divider outputs, and user logic. There are clock divider blocks (ECLKDIV and PCLKDIV) to provide a slower clock from these clock sources. MachXO5-NX supports glitchless Dynamic Clock Control (DCC) for the PCLK Clock to save dynamic power. There are also Dynamic Clock Selection logic to allow glitchless selection between two clocks for the PCLK network (DCS). Overview of Clocking Network is shown in Figure 2.6 for MachXO5-NX device.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 21 BMID PLL
12 DCC
16 DCC
18 DCC
BANK 5 PCLKBANK 6 PCLK ECLK ECLK TMI D RMID LMID BANK 1 PCLK BANK 4 PCLK Figure 2.6. Clocking 2.3.4. Primary Clocks The MachXO5-NX device family provides low-skew, high fan-out clock distribution to all synchronous elements in the FPGA fabric through the Primary Clock Network. The MachXO5-NX PCLK clock network is a balanced clock structure which is designed to minimize the clock skew among all the final destination of the IPs in the FPGA core that needs a clock source. The primary clock network is divided into two clock domains depending on t he device density. Each of these domains has 16 clocks that can be distributed to the fabric in the domain. The Lattice Radiant software can automatically route each clock to one of the domains up to a maximum of 16 clocks per domain. You can change how the clocks are routed by specifying a preference in the Lattice Radiant software to locate the clock to a specific domain. The MachXO5-NX device provides you with a maximum of 64 unique clock input sources that can be routed to the primary Clock network. Primary clock sources are: Dedicated clock input pins PLL outputs PCLKDIV, ECLKDIV outputs Internal FPGA fabric entries (with minimum general routing) SGMII-CDR clocks OSC clock These sources are routed to each of four clock switches called a Mid Mux (LMID, R MID, TMID, BMID). The outputs of the Mid MUX are routed to the center of the FPGA where additional clock switches (DSC_CMUX) are used to route the primary clock sources to primary clock distribution to the MachXO5-NX fabric. These routing muxes are shown in Figure 2.6. There are potentially 64 unique clock domains that can be used in the largest MachXO5-NX device. For more information about the primary clock tree and connections, refer to sysCLOCK PLL Usage Guide for Nexus Platform (FPGA-TN-02095).
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 FPGA-DS-02102-0.80 CLK0 CLK1 SEL DCSOUT clk1 pos clk1 neg clk0 pos clk0 neg Figure 2.9. DCS Waveforms 2.3.9. Dynamic Clock Control The Dynamic Clock Control (DCC), Domain Clock enable/disable feature allows internal logic control of the domain primary clock network. When a clock network is disabled, the clock signal is static and not toggle. All the logic fed by that clock does not toggle, reducing the overall power consumption of the device. The disable function is glitchless, and does not increase the clock latency to the primary clock network. Four additional DCC elements control the clock inputs from the MachXO5-NX domain logic to the Center MUX elements (DSC_CMUX). This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center MUXs that drive the domain clock network. For more information about the DCC, refer to sysCLOCK PLL Usage Guide for Nexus Platform (FPGA-TN-02095). 2.3.10. DDRDLL The MachXO5-NX device has two identical DDRDLL blocks located in the lower left and lower right corners of the device. Each DDRDLL (master DLL block) can generate a phase shift code representing the amount of delay in a delay block that corresponding to 90-degree phase of the reference clock input, and provide this code to every individual DQS block and DLLDEL slave delay element. The reference clock can be either from PLL, or input pin. This code is used in the DQSBUF block that controls a set of DQS pin groups to interface with DDR memory (slave DLL). The DQSBUF uses this code to control the DQS input of the DDR memory to 90-degree shift to clock DQs at the center of the data eye for DDR memory interface. The code is also sent to another slave DLL, DLLDEL, which takes a primary clock input and generates a 90-degree shift clock output to drive the clocking structure. This is useful to interface edge-aligned Generic DDR, where 90-degree clocking needs to be created. Not all primary clock inputs have associated DLLDEL control. Figure 2.10 shows DDRDLL connectivity to a DLLDEL block (connectivity to DQSBUF blocks is similar).
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 FPGA-DS-02102-0.80 For more information about how to implement the hardened CDR for your SGMII solution, refer to the MachXO5-NX High-Speed I/O Interface (FPGA-TN-02286). SGMII CDR IP DESERIALIZER FIFODUAL_LOOP CDR rxd_des rclk_des lmmi_rdata[7:0] lmmi_rdata_valid lmmi_ready lmmi_dk lmmi_request lmmi_wrdn lmmi_offset[3:0] lmmi_wdata[7:0] lmmi_reset ip_ready sgmii_cdr_icnst<1:0> sgmii_in dco_calib_rst dco_facq_rst rrst sgmii_refclk(125 MHz) sgmii_pclk sgmii_rclk Figure 2.12. SGMII CDR IP 2.5. sysMEM Memory MachXO5-NX devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18 kb RAM with memory core, dedicated input registers and output registers as well as optional pipeline registers at the outputs. Each EBR includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and built in FIFO. In the MachXO5-NX device, unused EBR blocks is powered down to minimize power consumption. 2.5.1. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as listed in Table 2.4. FIFO can be implemented using the built-in read and write address counters and programmable full, almost full, empty and almost empty flags. The EBR block facilitates parity checking by supporting an optional parity bit for each data byte. EBR blocks provide byte -enable support for configurations with 18-bit and 36-bit data widths. For more information, refer to Memory Usage Guide for Nexus Platform (FPGA-TN- 02094). EBR also provides a build in ECC engine in select speed grades (see Ordering Information). The ECC engine supports a write data width of 32 bits and it can be cascaded for larger data widths such as ×64. The ECC parity generator creates and stores parity data for each 32-bit word written. When a read operation is performed, it compares the data with it s associated parity data and report back if any Single Event Upset (SEU) event has disturbed the data. Any single bit data disturb is automatically corrected at the data output. In addition, two dedicated error flags indicate if a single-bit or two-bit error has occurred.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 27 Table 2.4. sysMEM Block Configurations Memory Mode Configurations Single Port 16,384 × 1 8,192 × 2 4,096 × 4 2,048 × 9 1,024 × 18 512 × 36 True Dual Port 16,384 × 1 8,192 × 2 4,096 × 4 2,048 × 9 1,024 × 18 Pseudo Dual Port 16,384 × 1 8,192 × 2 4,096 × 4 2,048 × 9 1,024 × 18 512 × 36 2.5.2. Bus Size Matching All of the multi-port memory modes support different widths on each of the ports (except ECC mode, which only supports a write data width of 32 bits). The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. 2.5.3. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 2.5.4. Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. 2.5.5. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes, the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. 2.5.6. Memory Output Reset The EBR utilizes latches at the A and B output ports. These latches can be reset asynchro nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and associated reset s for both ports are as shown in Figure 2.13. The optional Pipeline Registers at the outputs of both ports are also reset in the same way.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 28 FPGA-DS-02102-0.80 Q SET D LCLR Output Data Latches Memory Core Port A[17:0] Q SET D Port B[17:0] RSTB GSRN Programmable Disable RSTA LCLR Figure 2.13. Memory Core Reset For further information on the sysMEM EBR block, see the list of technical documentation in Supplemental Information section. 2.6. Large RAM The MachXO5-NX device includes additional memory resources in the form of Large Random-Access Memory (LRAM) blocks. The LRAM is designed to work as Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM, and ROM memories. It is designed to function as additional memory resources for you beyond what is available in the EBR and PFU. Each individual Large RAM block contains 0.5 Mb of memory, and has a programmable data width of up to 32 bits. Cascading Large RAM blocks allows data widths up to 64 bits. Additionally, each LRAM can use either Error Correction Coding (ECC) or byte enable. 2.7. sysDSP The MachXO5-NX family provides an enhanced sysDSP architecture, making it ideally suitable for low-cost, high-performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed -Solomon/Turbo/Convolution encoders and decoders. These complex signal processing functions use similar building blocks , such as multiply-adders and multiply-accumulators. 2.7.1. sysDSP Approach Compared to General DSP Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. In the MachXO5-NX device family, there are many DSP blocks that can be used to support different data widths. This allows you to use highly parallel implementations of the DSP functions. You can optimize DSP performance versus area by choosing appropriate levels of parallelism. Figure 2.14 compares the fully serial implementation to the mixed parallel and serial implementation.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 29 Operand A Operand B X Function Implemented in General Purpose DSP Single Multiplier Accumulator M loops Function Implemented in Control-D6 Devices Operand A Operand A Operand B Operand B X X Multiplier Multiplier X Multiplier k Operand A Operand B Output (k adds) m/k accumulate m/k loops Figure 2.14. Comparison of General DSP and MachXO5-NX Approaches 2.7.2. sysDSP Architecture Features The MachXO5-NX sysDSP Slice has been significantly enhanced to provide functions needed for advanced processing applications. These enhancements provide improved flexibility and resource utilization. The MachXO5-NX sysDSP Slice supports many functions that include the following: Symmetry support. The primary target application is wireless. 1D Symmetry is useful for many applications that use FIR filters when their coefficients have symmetry or asymmetry characteristics. The main motivation for using 1D symmetry is cost/size optimization. The expected size reduction is up to 2x. Odd Mode – Filter with Odd number of taps Even Mode – Filter with Even number of taps Two dimensional (2D) Symmetry Mode – Supports 2D filters for mainly video applications Dual-multiplier architecture. Lower accumulator overhead to half and the latency to half compared to single multiplier architecture. Fully cascadable DSP across slices. Support for symmetric, asymmetric and non -symmetric filters. Multiply (36 × 36, two 18 × 36, four 18 × 18 or eight 9 × 9) Multiply Accumulate (supports one 18 × 36 multiplier result accumulation, two 18 × 18 multiplier result accumulation or four 9 × 9 multiplier result accumulation) Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18 × 18 Multiplies feed into an accumulator that can accumulate up to 54 bits) Pipeline registers 1D Symmetry support. The coefficients of FIR filters have symmetry or negative symmetry characteristics. Odd Mode – Filter with Odd number of taps Even Mode – Filter with Even number of taps 2D Symmetry support. The coefficients of 2D FIR filters have symmetry or n egative symmetry characteristics. 3 × 3 and 3 × 5 – Internal DSP Slice support 5 × 5 and larger size 2D blocks – Semi internal DSP Slice support
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 30 FPGA-DS-02102-0.80 Flexible saturation and rounding options to satisfy a diverse set of applications situations Flexible cascading DSP blocks Minimizes fabric use for common DSP functions Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only Provides matching pipeline registers Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade chains RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applicat ions that require processor-like flexibility that enables different functions for each clock cycle For most cases, as shown in Figure 2.15, the MachXO5-NX sysDSP is backwards-compatible with the LatticeECP3™ sysDSP block, such that, legacy applications can be targeted to MachXO5-NX sysDSP. Figure 2.15 shows the diagram of sysDSP. Input Input Input C REGInput Input Input Input Input C REGInput Input
18 X 18
C REGInput Input Input Input Input C REGInput Input
18 X 36 (CSA)
C REGInput Input Input Input Input C REGInput Input C REGInput Input Input Input Input C REGInput Input
36 X 36 (CSA)
REG 18REG 18REG 18REG 18REG 18REG 18REG 18REG 18 ACC54ACC54 Output RegisterOutput Register Note : All Registers inside the DSP Block are Bypassable via Configuration Setting 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 Figure 2.15. MachXO5-NX DSP Functional Block Diagram The MachXO5-NX sysDSP block supports the following basic elements. MULT (Multiply) MAC (Multiply, Accumulate) MULTADDSUB (Multiply, Addition/Subtraction) MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation)
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 31 Table 2.5 shows the capabilities of MachXO5-NX sysDSP block versus the above functions. Table 2.5. Maximum Number of Elements in a sysDSP block Width of Multiply ×9 ×18 ×36 MULT 8 4 1 MAC 2 2 — MULTADDSUB 2 2 — MULTADDSUBSUM 2 2 — Some options are available in the four elements. The input register in all the elements can be directly loaded or can be loaded as a shift register from previous operand registers. By selecting dynamic operation, the following operations are possible: In the Add/Sub option, the Accumulator can be switched between addition and subtraction on every cycle. The loading of operands can switch between parallel and serial op erations. For further information, refer to sysDSP User Guide for Nexus Platform (FPGA-TN-02096). 2.8. Programmable I/O (PIO) The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective sysI/O buffers and pads. On all the MachXO5-NX devices, two adjacent PIO can be combined to provide a complementary output driver pair. 2.9. Programmable I/O Cell (PIC) The programmable I/O cells (PIC) provide I/O function and necessary gearing logic associated with PIO. MachXO5-NX consists of base PIC and gearing PIC. Base PICs contain three blocks: an input register block, output register block , and tri-state register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. Base PICs cover the top and left/right bank. Gearing PICs contain gearing logic and edge monitor used for locating the center of data window. Gearing PICs cover the bottom banks to support DDR operation.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 36 FPGA-DS-02102-0.80 TSFF TD TQ THSX2 RST SCLK ECLK DQSW DQSW270 T[1:0] Figure 2.23. Tri-state Register Block on Bottom Side Table 2.8. Tri-state Block Port Description Name Type Description TD Input Tri-state Input to Tri-state SDR Register RST Input Reset to the Tri-state Block T[1:0] Input Tri-state input to TSHX2 function SCLK Input Slow Speed System Clock ECLK Input High Speed Edge Clock DQSW Input Clock from DQS control Block used to generate DDR memory DQS output DQSW270 Input Clock from DQS control Block used to generate DDR memory DQ output TQ Output Output of the Tri-state block 2.10. DDR Memory Support 2.10.1. DQS Grouping for DDR Memory Some PICs have additional circuitry to allow the implementation of high -speed source synchronous and DDR3/DDR3L, LPDDR2 or LPDDR3 memory interfaces. The support varies by the edge of the device as detailed below. The Bottom bank PIC has fully functional elements supporting DDR3/DDR3L, LPDDR2, or LPDDR3 memory interfaces. Every 12 PIO on the bottom side are grouped into one DQS group, as shown in Figure 2.24. Within each DQS group, there are two pre-placed pins for DQS and DQS# signals. The rest of the pins in the DQS group can be used as DQ signals and DM signal. The number of the pins in each DQS group bonded out is package dependent. DQS groups with less than 11 pins bonded out can only be used for LPDDR2/3 Command/ Address busses. In DQS groups with more than 11 pins bonded out, up to two pre-defined pins are assigned to be used as virtual VCCIO, by driving th ese pins to HIGH, and connecting these pins to VCCIO power supply. These connections create soft connections to VCCIO thru these output pins, and make better connections on VCCIO to help to reduce SSO noise. For details, refer to MachXO5-NX High-Speed I/O Interface (FPGA-TN-02286).
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 37 PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A DQS PIO B PIO A PIO B PIO A DQSBUF sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer Delay Pad B Pad A Pad B Pad A Pad B (C) Pad A (T) Pad B (C) Pad A (T) Pad B Pad A Pad B (C) Pad A (T) Figure 2.24. DQS Grouping on the Bottom Edge 2.10.2. DLL Calibrated DQS Delay and Control Block (DQSBUF) To support DDR memory interfaces (DDR3/DDR3L, LPDDR2/3), the DQS strobe signal from the memory must be used to capture the data (DQ) in the PIC registers during memory reads. This signal is output from the DDR memory device aligned to data transitions and must be time shifted before it can be used to capture da ta in the PIC. This time shift is achieved by using DQSBUF programmable delay line in the DQS Delay Block (DQS read circuit). The DQSBUF is implemented as a slave delay line and works in conjunction with a master DDRDLL. This block also includes slave delay line to generate delayed clocks used in the write side to generate DQ and DQS with correct phases within one DQS group. There is a third delay line inside this block used to provide the write-leveling feature for DDR write if needed. Each of the read and write side delays can be dynamically shifted using margin control signals that can be controlled by the core logic. FIFO Control Block included here generates the Read and Write Pointers for the FIFO block inside the Input Register Block. These pointers are generated to control the DQS to ECLK domain crossing using the FIFO module.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 38 FPGA-DS-02102-0.80 Slave Delay Line (RD) with Adjustment/Margin Test Slave Delay (WR) with Adjustment/Margin Test and Write Leveling BTDETECT Preamble/Postamble Management FIFO Control and Data Valid Generation RST WRLVDIR WRMOVE DQSW READCOUT WRLOAD_N ECLKIN RSTSM CNT DLLCODE[8:0] WRPNTR[2:0] WRLVCOUT WRCOUT DQSW270 DQSI PAUSE RDCLKSEL[3:0] RDDIR RDLOAD N READMOVE READ[3:0] SCLK SELCLK WRDIR WRLVLOAD_N WRLVMOVE BURST DETECT DAT AVALID DQSWRD RDPNT R[2:0] DQSR90 Figure 2.25. DQS Control and Delay Block (DQSBUF) Table 2.9. DQSBUF Port List Description Name Type Description DQSI Input DQS signal from IO through the PIC. PAUSE Input To stop ECLK for DDR3 Write leveling and DLL code update. RDCLKSEL[3:0] Input Select read clock source and polarity control (from CIB). RDDIR Input 0 – to increase the code. 1 – to decrease the code for DDR read. RDLOADN Input 1b0 – When mc1_mt_en_read=1b1 and read_load_n=1b0 the read_move pulse needs to be generated to the load the preload value consisting of the {mc1_sign_read, mc1_s_read [8:0]} value. 1b1 – When counter has preload value, read_move pulse can be used to increment and decrement the counter based on the read_direction signal value and mc1_mt_en_write should be set 1b1. READ[3:0] Input Read signal for DDR read mode (from CIB). READMOVE Input Move pulse needs to be at least 1 sclk cycle and should be greater than 5ns at TT corner. Pulse is used along with the eclk to generate the internal 'mov' signal to update the counter by one value. The count up or down is determined by the read_direction port. RST Input DQS reset control for both DDR/CDR modes (from CIB). SCLK Input SCLK from SCLK tree (CIB). SELCLK Input Select the clock to be used between the output of the read section's delay cell or sclk. WRDIR Input 0 – to increase the code. 1 – to decrease the code for DDR write.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 39 Name Type Description WRLOAD_N Input 1b0 – When mc1_mt_en_write=1b1 and write_load_n=1b0 the write_move pulse needs to be generated to the load the preload value consisting of the {mc1_sign_write, mc1_s_write [8:0]} value. 1b1 – When counter has preload value, write_move pulse can be used to increment and decrement the counter based on the write_direction signal value and mc1_mt_en_write should be set 1b1. WRLVDIR Input 0 – to increase the code. 1 – to decrease the code for DDR write leveling. WRLVLOAD_N Input 1b0 – 9-bit counter in reset operation. 1b1 – When mc1_mt_en_write_leveling=1b1 and write_leveling_load_n=1b1 the counter can be incremented/decremented based on the direction signal using the write_leveling_move signal. WRLVMOVE Input Move pulse needs to be at least 1 sclk cycle and should be greater than 5 ns at TT corner. Pulse is used along with the eclk to generate the internal 'mov' signal to update the counter by one value. The count up or down is determined by the write_leveling_direction port. WRMOVE Input Move pulse needs to be at least 1 sclk cycle and should be greater than 5ns at TT corner. Pulse is used along with the eclk to generate the internal 'mov' signal to update the counter by one value. The count up or down is determined by the write_direction port. ECLKIN Input ECLK from four different ECLK tree output. RSTSMCNT Input Signal to reset the smoothing counters used for the Read, Write, and Write leveling delays. DLLCODE[8:0] Input DLL code selected from the DLL code routing mux. BTDETECT Output READ burst detect output (to CIB). BURSTDETECT Output The burst_det_sclk signal is generated using burst_det and is asserted on the rising edge of SCLK. DATAVALID Output Data Valid Flag for READ mode (to CIB). DQSW Output ECLK phase shifted or delayed, goes to the dqsw tree through the PIC. DQSWRD Output The read training clock adjusted in the write section. The read_clk_sel[3:0] determines the selected delay and read enable position. RDPNTR[2:0] Output FIFO control READ pointer (3-bits) to FIFO in PIC (through each tree to IOL). READCOUT Output Margin test output flag for READ to indicate the under-flow or over-flow. DQSR90 Output DQSI phase shifted or delayed by 90-degree output (through DQSR tree to IOL). DQSW270 Output ECLK phase shifted or delayed by 270-degree output (through DQSW270 tree to IOL). WRCOUT Output Margin test output flag for WRITE to indicate the under-flow or over-flow. WRLVCOUT Output Margin test output flag for WRITE LEVELING to indicate the under-flow or over-flow.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 40 FPGA-DS-02102-0.80 Name Type Description WRPNTR[2:0] Output FIFO control WRITE pointer (3-bits) to FIFO in PIC (through each tree to IOL). 2.11. sysI/O Buffer Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers a re arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allows you to implement the wide variety of standards that are found in today’s systems including LVDS, HSUL, SSTL Class I and II, LVCMOS, LVTTL, and MIPI. The MachXO5-NX family contains multiple Programmable I/O Cell (PIC) blocks. Each PI C contains two Programmable I/O, PIOA and PIOB. Each PIO includes a sysI/O buffer and I/O logic. Two adjacent PIO can be joined to provide a differential I/O pair. These two pairs are referred to as True and Comp, where True Pad is associated with the positive side of the differential I/O, and the complement with the negative. The top, left and right side banks support I/O standards from 3.3 V to 1.0 V while the bottom supports I/O standards from 1.8 V to 1.0 V. Every pair of I/O on the bottom bank also have a true LVDS and SLVS Tx Driver. In addition, the bottom bank supports single-ended input termination. Both static and dynamic termination are supported. Dynamic termination is used to support the DDR/LPDDR interface standards. For more information about DDR implementation in I/O Logic and DDR memory interface support, refer to MachXO5-NX High-Speed I/O Interface (FPGA-TN-02286). 2.11.1. Supported sysI/O Standards MachXO5-NX sysI/O buffer supports both single-ended differential and differential standards. Single-ended standards can be further subdivided into internally ratioed standards, such as LVCMOS, LVTTL, and external referenced standards Differential standards supported include LVDS, SLVS, differential LVCMOS, differential SSTL, and differen tial HSUL. For better support of video standards, subLVDS and MIPI_D-PHY are also supported. Table 2.10 and Table 2.11 provide a list of sysI/O standards supported in MachXO5-NX devices. Table 2.10. Single-Ended I/O Standards Standard Input Output Bi-directional LVTTL33 Yes Yes Yes LVCMOS33 Yes Yes Yes LVCMOS25 Yes Yes Yes LVCMOS18 Yes Yes Yes LVCMOS15 Yes Yes Yes LVCMOS12 Yes Yes Yes LVCMOS10 Yes No No HTSL15 I Yes Yes Yes SSTL 15 I Yes Yes Yes SSTL 135 I Yes Yes Yes HSUL12 Yes Yes Yes LVCMOS18H Yes Yes Yes LVCMOS15H Yes Yes Yes LVCMOS12H Yes Yes Yes LVCMOS10H Yes Yes Yes LVCMOS10R Yes — Yes* *Note: Output supported by LVCMOS10H.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 41 Table 2.11. Differential I/O Standards Standard Input Output Bi-directional LVDS Yes Yes Yes SUBLVDS Yes No — SLVS Yes Yes — SUBLVDSE — Yes — SUBLVDSEH — Yes — LVDSE — Yes — MIPI_D-PHY Yes Yes Yes HSTL15D_I Yes Yes Yes SSTL15D_I Yes Yes Yes SSTL15D_II Yes Yes Yes SSTL135D_I Yes Yes Yes SSTL135D_II Yes Yes Yes HSUL12D Yes Yes Yes LVTTL33D — Yes — LVCMOS33D — Yes — LVCMOS25D — Yes — 2.11.2. sysI/O Banking Scheme MachXO5-NX device has up to ten banks in total. There are two banks on the top, three banks each at the left and right side of the device, and two on the bottom side of the device. Bank 1 can only support VCCIO 3.3 V, Bank 0, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9 support up to VCCIO 3.3 V, while Bank 5 and Bank 6 can support up to VCCIO 1.8 V. In addition, Bank 5 and Bank 6 support two VREF input for its flexibility to receive two different referenced input levels on the same bank. Figure 2.26 shows the location of each bank.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 42 FPGA-DS-02102-0.80 Bank 9 Bank 8 Bank 6 Bank 5 Bank 0 Bank 2 Bank 3 GND VCCIO(0) GND VCCIO(2) GND VCCIO(3) GND VCCIO(9) GND VCCIO(8) GND GND VCCIO(6) VREF1(6) VREF2(6) VCCIO(5) VREF1(5) VREF2(5) Bank 1 GND VCCIO(1) Bank 4 GND VCCIO(4)Bank 7 GND VCCIO(7) Figure 2.26. sysI/O Banking 2.11.2.1. Typical sysI/O I/O Behavior During Power-up The internal Power-On-Reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is your responsibility to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information on controlling the output logic state with valid input logic levels during power-up in MachXO5-NX devices, refer to the list of technical documentation in Supplemental Information section. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify the system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. For different power supply voltage level by the I/O banks, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for detailed information. 2.11.2.2. VREF1 and VREF2 Bank 5 and Bank 6 can support two separate VREF input voltage, VREF1, and VREF2. To assign a VREF driver, use IO_Type = VREF1_DRIVER or VREF2_DRIVER. To assign VREF to a buffer, use VREF1_LOAD or VREF2_LOAD. 2.11.2.3. sysI/O Standards Supported by I/O Bank All banks can support multiple I/O standards under the VCCIO rules discussed above. Table 2.12 and Table 2.13 summarize the I/O standards supported on various sides of the MachXO5-NX device.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 43 Table 2.12. Single-Ended I/O Standards Supported on Various Sides Standard Top* Left Right Bottom LVTTL33 Yes Yes Yes — LVCMOS33 Yes Yes Yes — LVCMOS25 Yes Yes Yes — LVCMOS18 Yes Yes Yes — LVCMOS15 Yes Yes Yes — LVCMOS12 Yes Yes Yes — LVCMOS10 Yes Yes Yes — LVCMOS18H — — — Yes LVCMOS15H — — — Yes LVCMOS12H — — — Yes LVCMOS10H — — — Yes LVCMOS10R — — — Yes HTSL15 I — — — Yes SSTL 15 I, II — — — Yes SSTL 135 I, II — — — Yes HSUL12 — — — Yes *Note: Bank 1 can only support 3.3V VCCIO. Table 2.13. Differential I/O Standards Supported on Various Sides Standard Top* Left Right Bottom LVDS — — — Yes SUBLVDS — — — Yes SLVS — — — Yes SUBLVDSE Yes Yes Yes — SUBLVDSEH — — — Yes LVDSE Yes Yes Yes — MIPI_D-PHY — — — Yes HSTL15D_I — — — Yes SSTL15D_I — — — Yes SSTL15D_II — — — Yes SSTL135D_I — — — Yes SSTL135D_II — — — Yes HSUL12D — — — Yes LVTTL33D Yes Yes Yes — LVCMOS33D Yes Yes Yes — LVCMOS25D Yes Yes Yes — *Note: Bank 1 can only support 3.3V VCCIO. 2.11.2.4. Hot Socketing MachXO5-NX devices have been carefully designed to ensure predictable behavior during power-up and power-down. During power-up and power-down sequences, the I/O remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified li mits. Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8, and Bank 9 wide range I/O (excluding INITN/DONE) are fully hot socketable, while Bank 5 and Bank 6 are not supported. 2.11.3. sysI/O Buffer Configurations This section describes the various sysI/O features available on the MachXO5-NX device. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for detailed information.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 44 FPGA-DS-02102-0.80 2.12. Analog Interface In select speed grades, the MachXO5-NX family provides an analog interface, consisting of two Analog to Digital Convertors (ADC), three continuous time comparators and an internal junction temperature monitoring diode. See Ordering Information for more details. The two ADCs can sample the input sequentially or simultaneously. 2.12.1. Analog to Digital Converters The Analog to Digital Convertor is a 12-bit, 1 MSPS SAR (Successive Approximation Resistor/capacitor) architecture converter. The ADC supports both continuous and single shot conversion mode s. The ADC input is selected among pre-selected GPIO input pairs, dedicated analog input pair, the internal junction temperature sensing diode and internal voltage rails. The input signal can be converted in either uni -polar or bi-polar mode. The reference voltage is selectable between the 1.2 V internal reference generator and an external reference. The ADC can convert up to a 1.8 V input signal with a 1.8 V external reference voltage. The ADC has an auto -calibration function which calibrates the gain and offset. 2.12.2. Continuous Time Comparators The continuous-time comparator can be used to compare a pre-selected GPIO input pairs or one dedicated comparator input pair. The output of the comparator is provided as continuous and latched data. 2.12.3. Internal Junction Temperature Monitoring Diode On-die junction temperature can be monitored using the internal junction temperature monitoring diode. The PTAT (proportional to absolute temperature) diode voltage can be monitored by the ADC to provide a digital temperature readout. Refer to ADC Usage Guide for Nexus Platform (FPGA-TN-02129) for more details. 2.13. IEEE 1149.1-Compliant Boundary Scan Testability All MachXO5-NX devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/O: TDI, TDO, TCK, and TMS. The test access port uses VCCIO2 for power supply. The test access port is supported for VCCIO2 = 1.8 V - 3.3 V. For more information, refer to MachXO5-NX Programming and Configuration User Guide (FPGA-TN-02271). 2.14. Device Configuration All MachXO5-NX devices contain two ports that can be used for device configuration. The Test Access Port (TAP) that supports bit-wide configuration, and the sysCONFIG port that supports serial, quad, and byte configuration. TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standar d 1532 In-System Configuration specification. The JTAG_EN is the only dedicated pin supported by sysCONFIG. PPROGRAMN/INITN/DONE are enabled by default, but can be turned into GPIO. The remaining sysCONFIG pins are used as dual function pins. Refer to MachXO5-NX Programming and Configuration User Guide (FPGA-TN-02271) for more information about using the dual-use pins as general purpose I/O. There are various ways to configure a MachXO5-NX device: Internal Flash Download JTAG Inter-Integrated Circuit Bus (I2C) Improved Inter-Integrated Circuit Bus (I3C) System microprocessor to drive a serial slave SPI port (SSPI mode) Lattice Memory Mapped Interface (LMMI), refer to sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067) for condition.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 45 JTAG, SSPI, I2C, and I3C are supported for VCCIO = 1.8 V – 3.3 V On power-up, based on the voltage level (high or low) of the PROGRAMN pin, the FPGA SRAM is configured by the appropriate sysCONFIG port. If PROGRAMN pin is low, the FPGA is in the Slave configuration ports (Slave SPI, Slave I2C or Slave I3C) and is waiting for the correct Slave Configuration port activation key. PROGRAMN pin must be driven high within 50 ns of the end of transmission of the Slave Configuration port activation key, that is, the deassertion of SCSN. If no slave port is declared active before the PROGRAMN pin is sensed HIGH, the FPGA is in self download mode. In self download mode, the FPGA boots from on-chip flash. Once a configuration port is activated, it remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by enabling the JTAG_EN pin and sending the appropriate command through the TAP port. 2.14.1. Enhanced Configuration Options MachXO5-NX devices have enhanced configuration features such as: Early I/O release Bitstream decryption Decompression support Watchdog Timer support Dual and Multi-boot image support Early I/O release is a new configuration feature in which certain I/O banks are released earlier so that customer systems have minimal disruption. For more details, refer to MachXO5-NX Programming and Configuration User Guide (FPGA-TN-02271). Watchdog Timer is a new configuration feature that helps you add a programmable timer option for timeout applications. 2.14.2. Dual-Boot and Multi-Boot Image Support Dual-boot and multi-boot images are supported for applications requiring reliable remote updates of configuration data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update , the MachXO5-NX devices can be re-booted from this new configuration file. If there is a problem, such as corrupt data during download or incorrect version number with this new boot image, the MachXO5-NX device can revert back to the original backup golden configuration and try again. This all can be done without power cycling the system. For more information, refer to MachXO5-NX Programming and Configuration User Guide (FPGA-TN-02271).
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 46 FPGA-DS-02102-0.80 2.15. Single Event Upset (SEU) Support MachXO5-NX devices are unique due to the underlying technology used to build these devices , and is much more robust and less prone to soft errors. MachXO5-NX devices have an improved hardware implemented Soft Error Detection (SED) circuit that can be used to detect SRAM errors and thus allow the errors to be corrected. There are two layers of SED implemented in the MachXO5-NX device making it more robust and reliable. The SED hardware in MachXO5-NX devices is part of the Configuration block. The SED module in the MachXO5-NX device is an enhanced version as compared to the SED modules implemented in other Lattice devices. The configuration data is divided into frames so that the entire FPGA can be programmed precisely with ease. The SED hardware reads data from the FPGAs configuration memory and performs Error Correcting Code (ECC) calculation on every frame of configuration data (see Figure 2.1). Once a single bit of error is detected, Soft Error Upset (SEU), a notification is generated and SED resumes operation. For single bit errors, the corrected value is rewritten to the particular frame using ECC information. If more than one-bit error is detected within one frame of configuration data, an error message is generated. MachXO5-NX devices also have a dedicated logic to perform Cycle Redundancy Code (CRC) checks. This CRC runs in parallel for the entire bitstream along with ECC. After the ECC is calculated on all frames of configuration data, Cyclic Redundancy Check (CRC) is calculated for the entire configuration data (bitstream). The data that is read, and the ECC and CRC cal culated, do not include EBR Big SRAM and distributed RAM memory. For further information on SED support, refer to Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform (FPGA-TN-02076). 2.16. On-Chip Oscillator The MachXO5-NX device features two different frequency Oscillators. One is tailored for low -power operation that runs at low frequency (LFOSC). Both Oscillators are controlled with the internally generated current. The LFOSC runs at nominal frequency of 128 kHz. The high frequency oscillator (HFOSC) runs at a nominal frequency of 450 MHz, and is divisible from 2 to 256 for output frequency between 1.758 MHz (div256) and 225 MHz (div2) . The LFOSC always run, thus can be used to perform all always-on functions with the possible lowest power. 2.17. User I²C IP The MachXO5-NX device has one I²C IP core. The core can be configured either as an I²C master or as an I²C slave. The pins for the I²C interface are pre-assigned. The core has the option to delay either the input or the output, or both, by 50 ns nominal, using dedicated on -chip delay elements. This provides an easier interface with any external I2C components. In addition, 50 ns glitch filters are available for both SDA and SCL. When the IP core is configured as master, it can control other devices on the I2C bus through the pre-assigned pin interface. When the core is configured as the slave, the device can provide, for example, I/O expansion to an I²C Master. The I²C core supports the following functionalities: Master and Slave operation 7-bit and 10-bit addressing Multi-master arbitration support Clock stretching Up to 1 MHz data transfer speed (Standard-Mode, Fast-Mode, Fast-Mode Plus) General Call support Optional receive and transmit data FIFOs with programmable sizes Optionally 50 ns delay on input or output data, or both Hard-connection and Programmable I/O connection support Programmable to a mode compliant with I3C requirements on legacy I2C Slave devices Fast-Mode and Fast-Mode Plus support
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 47 Disabled Clock Stretching 50 ns SCL and SDA Glitch Filter Programmable 7-bit address For further information on the User I²C, refer to I2C Hardened IP Usage Guide for Nexus Platform (FPGA-TN-02142). 2.18. User Flash Memory (UFM) MachXO5-NX devices provide a UFM block that can be used for a variety of applications including configuration image overflow, initializing EBRs to store PROM data or, as a general purpose user Flash memor y. The UFM block connects to the device core through the embedded function block LMMI interface. You can also access the UFM block through the JTAG, I2C, and SPI interfaces of the device. The UFM block offers the following features: Non-volatile storage up to 15,360 kb 100 k write cycles Write access is performed page-wise; each page has 2048 bits (256 bytes) Auto-increment addressing LMMI interface Table 2.14. MachXO5-NX UFM Size Device UFM0 (kbit) UFM1 (kbit) UFM2 (kbit) User Data (kbit) LFMXO5-25 2,048 2,048 2,048 9,216 2.19. Trace ID Each MachXO5-NX device contains a unique (per device) TraceID that can be used for tracking purposes or for IP security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits are factory-programmed. The TraceID is accessible through the SPI, I2C, or JTAG interfaces. For further information on TraceID, refer to Using TraceID (FPGA-TN-02084). 2.20. Pin Migration The MachXO5-NX family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when pe rforming design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization impact the likelihood of success in each case. An example is that some user I/O may become No Connects in smaller devices in the same package. Refer to the MachXO5-NX Pin Migration Tables and Lattice Radiant software for specific restrictions and limitations. 2.21. Cryptographic Engine The MachXO5-NX family of devices support several cryptographic features that helps customer secure their design. Some of the key cryptographic features include Advanced Encryption Standard (AES) and Hashing Algorithms and true random number generator (TRNG). The MachXO5-NX device also features the bitstream encryption (using AES-256) used for protecting confidential FPGA bitstream data, and the bitstream authentication (using ECDSA) maintaining the bitstream integrity and protecting the FPGA design bitstream from being copied and tampered. The Cryptographic Engine (CRE) is the main engine (Figure 2.27) that is responsible for the bitstream encryption as well as the authentication of the MachXO5-NX device. Once the bitstream is authenticated and the device is ready for user functions, CRE is available for you to implement various cryptographic functions in your FPGA design. To enable specific cryptographic function, CRE must be configured by setting a few registers. CRE supports the following user-mode features: True Random Number generator (TRNG) Secure Hashing Algorithm (SHA)-256 bit
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 48 FPGA-DS-02102-0.80 Message authentication codes (MACs) – HMAC Lattice Memory Mapped Interface (LMMI) interface to user logic High Speed Port (HSP) for FIFO-based streaming data transfer Cryptographic Engine (CRE) FPGA Fabric LMMI / High Speed Port Control Register CRE Registers True Random Number Generator (TRNG) Bitstream Encryption Bitstream Authentication SHA256 HMAC SHA256 Unique Secret Identity (USID) Advanced Encryption Standard (AES) Figure 2.27. Cryptographic Engine Block Diagram
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 49 3. DC and Switching Characteristics for Commercial and Industrial 3.1. Absolute Maximum Ratings Table 3.1. Absolute Maximum Ratings Symbol Parameter Min Max Unit VCC, VCCECLK Supply Voltage –0.5 1.10 V VCCAUX, VCCAUXA, VCCAUXH5, VCCAUXH6 Supply Voltage –0.5 1.98 V VCCIO0, 1, 2, 3, 4, 7, 8, 9, 10, 11 I/O Supply Voltage –0.5 3.63 V VCCIO5, 6 I/O Supply Voltage –0.5 1.98 V VCCADC18 ADC Block 1.8 V Supply Voltage –0.5 1.98 V — Input or I/O Voltage Applied, Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8, Bank 9 –0.5 3.63 V — Input or I/O Voltage Applied, Bank 5, Bank 6 –0.5 1.98 V TA Storage Temperature (Ambient) –65 150 °C TJ Junction Temperature — +125 °C Notes: 1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. All VCCAUX should be connected on PCB.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 50 FPGA-DS-02102-0.80 3.2. Recommended Operating Conditions1, 2, 3 Table 3.2. Recommended Operating Conditions Symbol Parameter Conditions Min Typ. Max Unit VCC, VCCECLK Core Supply Voltage VCC = 1.0 0.95 1.00 1.05 V VCCAUX Auxiliary Supply Voltage Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8, Bank 9 1.746 1.80 1.89 V VCCAUXH5/6 Auxiliary Supply Voltage Bank 5, Bank 6 1.746 1.80 1.89 V VCCAUXA Auxiliary Supply Voltage for core logic — 1.746 1.80 1.89 V VCCIO I/O Driver Supply Voltage VCCIO = 3.3 V, Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8, Bank 9 3.135 3.30 3.465 V VCCIO = 2.5 V, Bank 0, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8, Bank 9 2.375 2.50 2.625 V VCCIO = 1.8 V, All Banks except Bank 1 1.71 1.80 1.89 V VCCIO = 1.5 V, All Banks except Bank 14 1.425 1.50 1.575 V VCCIO = 1.35 V, All Banks except Bank 14 (For DDR3L Only) 1.2825 1.35 1.4175 V VCCIO = 1.2 V, All Banks except Bank 14 1.14 1.20 1.26 V VCCIO = 1.0 V, Bank 5, Bank 6 0.95 1.00 1.05 V ADC External Power Supplies VCCADC18 ADC 1.8 V Power Supply — 1.71 1.80 1.89 V Operating Temperature tJCOM Junction Temperature, Commercial Operation — 0 — 85 °C tJIND Junction Temperature, Industrial Operation — –40 — 100 °C Notes: 1. For correct operation, all supplies must be held in their valid operation voltage range. 2. All supplies with same voltage should be from the same voltage source. Proper isolation filters are needed to properly isolate noise from each other. 3. Common supply rails must be tied together. 4. JTAG, SSPI, I2C, and I3C (Bank 2) ports are supported for VCCIO = 1.8 V to 3.3 V.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 51 3.3. Power Supply Ramp Rates Table 3.3. Power Supply Ramp Rates Symbol Parameter Min Typ Max Unit tRAMP Power Supply ramp rates for all supplies 1 0.1 — 50 V/ms Notes: 1. Assumes monotonic ramp rates. 2. All supplies need to be in the operating range as defined in Recommended Operating Conditions when the device has completed configuration and entering into User Mode. Supplies that are not in the operating range needs to be adjusted to faster ramp rate, or you have to delay configuration or wake up. 3.4. Power up Sequence Power-On-Reset (POR) puts the MachXO5-NX device into a reset state. There is no power up sequence required for the MachXO5-NX device. Table 3.4. Power-On Reset Symbol Parameter Min Typ Max Unit VPORUP Power-On-Reset ramp-up trip point (Monitoring VCC, VCCAUX, VCCI01, and VCCI02) VCC — — — V VCCAUX — — — V VCCIO1,VCCI02 — — — V VPORDN Power-On-Reset ramp-up trip point (Monitoring VCC and VCCAUX) VCC — — — V VCCAUX — — — V 3.5. On-Chip Programmable Termination The MachXO5-NX devices support a variety of programmable on-chip terminations options, including: Dynamically switchable Single-Ended Termination with programmable resistor values of 40 Ω, 50 Ω, 60 Ω, or 75 Ω. Common mode termination of 100 Ω for differential inputs. Zo Zo Zo -VREF OFF-chip ON-chip Parallel Single-Ended Input Zo TERM control VCCIO Zo = 40 , 50 , 60 , or 75 to VCCIO /2 -2Zo Zo = 50 Differential Input OFF-chip ON-chip Figure 3.1. On-Chip Termination See Table 3.5 for termination options for input modes. Table 3.5. On-Chip Termination Options for Input Modes IO_TYPE Differential Termination Resistor1,2 Terminate to VCCIO/21,2 subLVDS 100, OFF OFF SLVS 100, OFF OFF MIPI_DPHY 100 OFF HSTL15D_I 100, OFF OFF
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 52 FPGA-DS-02102-0.80 IO_TYPE Differential Termination Resistor1,2 Terminate to VCCIO/21,2 SSTL15D_I 100, OFF OFF SSTL135D_I 100, OFF OFF HSUL12D 100, OFF OFF LVCMOS15H OFF OFF LVCMOS12H OFF OFF LVCMOS10H OFF OFF LVCMOS12H OFF OFF LVCMOS10H OFF OFF LVCMOS18H OFF OFF, 40, 50, 60, 75 HSTL15_I OFF 50 SSTL15_I OFF OFF, 40, 50, 60, 75 SSTL135_I OFF OFF, 40, 50, 60, 75 HSUL12 OFF OFF, 40, 50, 60, 75 Notes: TERMINATE to VCCIO/2 (Single-Ended) and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per bank. Only bottom bank have this feature. Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip termination tolerance –10%/+60%. Refer to sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067) for on-chip termination usage and value ranges. 3.6. Hot Socketing Specifications Table 3.6. Hot Socketing Specifications for GPIO Symbol Parameter Condition Min Typ Max Unit IDK Input or I/O Leakage Current for Wide Range I/O (excluding INITN/DONE) 0 < VIN < VIH(max) 0 < VCC < VCC(max) 0 < VCCIO < VCCIO(max) 0 < VCCAUX < VCCAUX(max) –1.5 — 1.5 mA Notes: IDK is additive to IPU, IPD, or IBH. Hot socket specification defines when the hot socketed device's junction temperature is at 85 oC or below. When the hot socketed device's junction temperature is above 85 oC, the IDK current can exceed the above spec. Going beyond the hot socketing ranges specified here will cause exponentially higher Leakage currents and potential reliability issues. A total of 64mA per 8 I/O should not be exceeded. 3.7. ESD Performance Refer to the MachXO5-NX Product Family Qualification Summary for complete qualification data, including ESD performance.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 53 3.8. DC Electrical Characteristics Table 3.7. DC Electrical Characteristics – Wide Range (Over Recommended Operating Conditions) Symbol Parameter Condition Min Typ Max Unit IIL, IIH1 Input or I/O Leakage current (Commercial/Industrial) 0 ≤ VIN ≤ VCCIO — — 10 µA IIH2 Input or I/O Leakage current VCCIO ≤ VIN ≤ VIH (max) — — 100 µA IPU I/O Weak Pull-up Resistor Current 0 ≤ VIN ≤ 0.7 * VCCIO -30 — -150 µA IPD I/O Weak Pull-down Resistor Current VIL (max) ≤ VIN ≤ VCCIO 30 — 150 µA IBHLS Bus Hold Low Sustaining Current VIN = VIL (max) 30 — — µA IBHHS Bus Hold High Sustaining Current VIN = 0.7 * VCCIO -30 — — µA IBHLO Bus hold low Overdrive Current 0 ≤ VIN ≤ VCCIO — — 150 µA IBHHO Bus hold high Overdrive Current 0 ≤ VIN ≤ VCCIO — — -150 µA VBHT Bus Hold Trip Points — VIL (max) — VIH (min) V Notes: 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus Maintenance circuits are disabled. 2. The input leakage current IIH is the worst case input leakage per GPIO when the pad signal is high and also higher than the bank VCCIO. This is considered a mixed mode input. Table 3.8. DC Electrical Characteristics – High Speed (Over Recommended Operating Conditions) Symbol Parameter Condition Min Typ Max Unit IIL, IIH1 Input or I/O Leakage 0 ≤ VIN ≤ VCCIO — — 10 µA IPU I/O Weak Pull-up Resistor Current 0 ≤ VIN ≤ 0.7 * VCCIO -30 — -150 µA IPD I/O Weak Pull-down Resistor Current VIL (max) ≤ VIN ≤ VCCIO 30 — 150 µA IBHLS Bus Hold Low Sustaining Current VIN = VIL (max) 30 — — µA IBHHS Bus Hold High Sustaining Current VIN = 0.7 * VCCIO -30 — — µA IBHLO Bus hold low Overdrive Current 0 ≤ VIN ≤ VCCIO — — 150 µA IBHHO Bus hold high Overdrive Current 0 ≤ VIN ≤ VCCIO — — -150 µA VBHT Bus Hold Trip Points — VIL (max) — VIH (min) V Note: Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus Maintenance circuits are disabled. Table 3.9. Capacitors – Wide Range (Over Recommended Operating Conditions) Symbol Parameter Condition Min Typ Max Unit VCC = typ., VIO = 0 to VCCIO + 0.2V — 6 — pf VCC = typ., VIO = 0 to VCCIO + 0.2V — 6 — pf Note: 1. TA 25 oC, f = 1.0 MHz.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 54 FPGA-DS-02102-0.80 Table 3.10. Capacitors – High Performance (Over Recommended Operating Conditions) Symbol Parameter Condition Min Typ Max Unit C11 I/O Capacitance* VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ., VIO = 0 to VCCIO + 0.2V — 6 — pf C21 Dedicated Input Capacitance* VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ., VIO = 0 to VCCIO + 0.2V — 6 — pf Note: 1. TA 25 oC, f = 1.0 MHz. Table 3.11. Single Ended Input Hysteresis – Wide Range (Over Recommended Operating Conditions) IO_TYPE VCCIO TYP Hysteresis LVCMOS33 3.3 V 250 mV LVCMOS25 3.3 V 200 mV
2.5 V 250 mV
LVCMOS18 1.8 V 180 mV LVCMOS15 1.5 V 50 mV LVCMOS12 1.2 V 0 LVCMOS10 1.2 V 0 Table 3.12. Single Ended Input Hysteresis – High Performance (Over Recommended Operating Conditions) IO_TYPE VCCIO TYP Hysteresis LVCMOS18H 1.8 V 180 mV LVCMOS15H 1.8 V 50 mV
1.5 V 150 mV
LVCMOS12H 1.2 V 0 LVCMOS10H 1.0 V 0 MIPI-LP-RX 1.2 V >25 mV 3.9. Supply Currents For estimating and calculating current, use Power Calculator in Lattice Design Software. This operating and peak current is design dependent, and can be calculated in Lattice Design Software. Some blocks can be placed into low current standby modes. Refer to Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices (FPGA-TN-02257).
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 55 3.10. sysI/O Recommended Operating Conditions Table 3.13. sysI/O Recommended Operating Conditions Standard Support Banks VCCIO (Input) VCCIO (Output) Typ. Typ. Single-Ended LVCMOS33 0, 1, 2, 3, 4, 7, 8, 9 3.3 3.3 LVTTL33 0, 1, 2, 3, 4, 7, 8, 9 3.3 3.3 LVCMOS25¹, ² 0, 1, 2, 3, 4, 7, 8, 9 2.5, 3.3 2.5 LVCMOS18H 5, 6 1.8 1.8 LVCMOS15H¹ 5, 6 1.5, 1.8 1.5 SSTL135_I, SSTL135_II3 5, 6 1.357 1.35 SSTL15_I, SSTL15_II3 5, 6 1.58 1.58 HSTL15_I3 5, 6 1.58 1.58 HSUL123 5, 6 1.2 1.2 MIPI D-PHY LP Input6 5, 6 1.2 1.2 Differential6 LVDSE5 0, 2, 3, 4, 7, 8, 9 — 2.5 subLVDSE5 0, 2, 3, 4, 7, 8, 9 — 1.8 subLVDSEH5 5, 6 — 1.8 MIPI D-PHY6 5, 6 1.2 1.2 LVCMOS33D5 0, 1, 2, 3, 4, 7, 8, 9 — 3.3 LVTTL33D5 0, 1, 2, 3, 4, 7, 8, 9 — 3.3 LVCMOS25D5 0, 2, 3, 4, 7, 8, 9 — 2.5 SSTL135D_I, SSTL135D_II5 5, 6 — 1.357 SSTL15D_I, SSTL15D_II5 5, 6 — 1.5 HSTL15D_I5 5, 6 — 1.5 HSUL12D5 5, 6 — 1.2 Notes: 1. Single-ended input can mix into I/O Banks with VCCIO different from the standard requires due to some of these input standards use internal supply voltage source (VCC, VCCAUX) to power the input buffer, which makes them to be independent of VCCIO voltage. For more details, please refer to sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067). The following is a brief guideline to follow: a. Weak pull-up on the I/O must be set to OFF. b. Bank 5 and Bank 6 I/O can only mix into banks with VCCIO higher than the pin standard, due to clamping diode on the pin in these banks. Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9 does not have this restriction. c. LVCMOS25 uses VCCIO supply on input buffer in Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9. It can be supported with VCCIO = 3.3 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. Hysteresis has to be disabled when using 3.3 V supply voltage. d. LVCMOS15 uses VCCIO supply on input buffer in Bank 5 and Bank 6. It can be supported with VCCIO = 1.8 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 56 FPGA-DS-02102-0.80 2. Single-ended LVCMOS inputs can mixed into I/O Banks with different VCCIO, providing weak pull-up is not used. For additional information on Mixed I/O in Bank VCCIO, refer to sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067). 3. These inputs use differential input comparator in Bank 5 and Bank 6. The differential input comparator uses VCCAUXH power supply. These inputs require the VREF pin to provide the reference voltage in the Bank. Refer to sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067) for details. 4. All differential inputs use differential input comparator in Bank 5 and Bank 6. The differential input comparator uses VCCAUXH power supply. There is no differential input signaling supported in Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9. 5. These outputs are emulating differential output pair with single-ended output drivers with true and complement outputs driving on each of the corresponding true and complement output pair pins. The common mode voltage, VCM, is ½ * VCCIO. Refer to sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067) for details. 6. Soft MIPI D-PHY HS using sysI/O is supported with SLVS input and output that can be placed in banks with VCCIO voltage shown in SLVS. D-PHY with HS and LP modes supported needs to be placed in banks with VCCIO voltage = 1.2 V. Soft MIPI D-PHY LP input and output using sysI/O are supported with LVCMOS12. 7. VCCIO = 1.35 V is only supported in Bank 5 and Bank 6, for use with DDR3L interface in the bank. These Input and Output standards can fit into the same bank with the VCCIO = 1.35 V. 8. LVCMOS15 input uses VCCIO supply voltage. If VCCIO is 1.8 V, the DC levels for LVCMOS15 are still met, but there could be increase in input buffer current. 3.11. sysI/O Single-Ended DC Electrical Characteristics3 Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O (Over Recommended Operating Conditions) Input/Output Standard VIL¹ VIH¹ VOL Max (V) VOH Min² (V) IOL(mA) IOH(mA) Min (V) Max (V) Min (V) Max (V) LVTTL33 2, 4, 8, 12, 16, “50RS”3 –2, –4, – –12, – 16, “50RS”3 2, 4, 8, 10, “50RS”3 –2, –4, – –10, “50RS”3 “50RS”3 –2, –4, – “50RS”3 LVCMOS10 — 0.35 × VCCIO 0.65 × VCCIO 3.4655 No O/P Support Notes: 1. VCCIO for input level refers to the supply rail level associated with a given input standard. 2. VCCIO for the output levels refer to the VCCIO of the CertusPro-NX device. 3. Selecting “50RS” in driver strength is to select 50 Ω series impedance driver. 4. For electro-migration, the combined DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal Connections table (also shown as I/O grouping) shall not exceed a maximum of n × 8 mA. n is the number of I/O pads between the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O Grouping can be found in the Data Sheet Pin Summary Tables, which can also be generated from the Lattice Radiant software. 5. If the input clamp is OFF, VIH (Max) in Banks 0, 1, 2, 3, 4, 7, 8, & 9 can go up to 3.465 V. Otherwise, the input voltage cannot be higher than VCCIO + 0.3 V.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 57 Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O (Over Recommended Operating Conditions)3 Input/Output Standard VIL¹ VIH¹ VOL Max (V) VOH Min² (V) IOL (mA) IOH (mA) Min (V) Max (V) Min (V) Max (V) LVCMOS18H — 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.4 VCCIO – 0.45 2, 4, 8, 12, “50RS”3 –2, –4, –8, –12, “50RS”3 LVCMOS15H — 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.4 VCCIO – 0.4 2, 4, 8, “50RS”3 –2, –4, –8, “50RS”3 LVCMOS12H — 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.4 VCCIO – 0.4 2, 4, 8, “50RS”3 –2, –4, –8, “50RS”3 LVCMOS10H — 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.27 × VCCIO 0.75 × VCCIO 2, 4 –2, –4 SSTL15_I — VREF – 0.10 VREF + 0.1 VCCIO + 0.3 0.30 VCCIO – 0.30 7.5 –7.5 SSTL15_II — VREF – 0.10 VREF + 0.1 VCCIO + 0.3 0.30 VCCIO – 0.30 8.8 –8.8 HSTL15_I — VREF – 0.10 VREF + 0.1 VCCIO + 0.3 0.40 VCCIO – 0.40 8 –8 SSTL135_I — VREF – 0.09 VREF + 0.09 VCCIO + 0.3 0.27 VCCIO – 0.27 6.75 –6.75 SSTL135_II — VREF – 0.09 VREF + 0.09 VCCIO + 0.3 0.27 VCCIO – 0.27 8 –8 LVCMOS10R — VREF – 0.10 VREF + 0.10 VCCIO + 0.3 — — — — HSUL12 — VREF – 0.10 VREF + 0.10 VCCIO + 0.3 0.3 VCCIO – 0.3 8.0, 7.5, 6.25, 5 –8.0, –7.5, –6.25, –5 Notes: 1. VCCIO for input level refers to the supply rail level associated with a given input standard or the upstream driver VCCIO rail levels. 2. VCCIO for the output levels refer to the VCCIO of the MachXO5-NX device. 3. Select “50RS” in driver strength is selecting the 50Ω series impedance driver. 4. For electro-migration, the combined DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal Connections table (also shown as I/O grouping) shall not exceed a maximum of n × 8 mA. n is the number of I/O pads between the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O Grouping can be found in the Data Sheet Pin Summary Tables, which can also be generated from the Lattice Radiant software. Table 3.16. I/O Resistance Characteristics (Over Recommended Operating Conditions) Parameter Description Test Conditions Min Typ Max Unit 50RS Output Drive Resistance when 50RS Drive Strength Selected VCCIO = 1.8 V, 2.5 V, or 3.3 V — 50 — Ω RDIFF Input Differential Termination Resistance Bank 5 and Bank 6 for I/O selected to be differential — 100 — Ω SE Input Termination Input Single Ended Termination Resistance Bank 5 and Bank 6 for I/O selected to be Single Ended 36 40 64 Ω 46 50 80 56 60 96 71 75 120
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 58 FPGA-DS-02102-0.80 3.12. sysI/O Differential DC Electrical Characteristics 3.12.1. LVDS LVDS input buffer on MachXO5-NX is powered by VCCAUX = 1.8 V, and protected by the bank VCCIO. Therefore, the LVDS input voltage cannot exceed the bank VCCIO voltage. LVDS output buffer is powered by the Bank VCCIO at 1.8 V. LVDS can only be supported in Bank 5 and Bank 6. LVDS25 output can be emulated with LVDS25E in Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9. This is described in LVDS25E (Output Only) section. Table 3.17. LVDS DC Electrical Characteristics (Over Recommended Operating Conditions) 1 Parameter Description Test Conditions Min Typ Max Unit VINP, VINM Input Voltage — 0 — 1.603 V VICM Input Common Mode Voltage Half the sum of the two Inputs 0.05 — 1.55Z V VTHD Differential Input Threshold Difference between the two Inputs ±100 — — mV IIN Input Current Power On or Power Off — — ±10 µA VOH Output High Voltage for VOP or VOM RT = 100 Ω — 1.425 1.60 V VOL Output Low Voltage for VOP or VOM RT = 100 Ω 0.9 1.075 — V VOD Output Voltage Differential (VOP - VOM), RT = 100 Ω 250 350 450 mV VOD Change in VOD Between High and Low — — — 50 mV VOCM Output Common Mode Voltage (VOP + VOM)/2, RT = 100 Ω 1.125 1.25 1.375 V VOCM Change in VOCM, VOCM(MAX) - VOCM(MIN) — — — 50 mV ISAB Output Short Circuit Current VOD = 0 V Driver outputs shorted to each other — — 12 mA VOS Change in VOS between H and L — — — 50 mV Notes: 1. LVDS input or output are supported in Bank 3, Bank 4, and Bank 5. LVDS input uses VCCAUX on the differential input comparator, and can be located in any VCCIO voltage bank. LVDS output uses VCCIO on the differential output driver, and can only be located in bank with VCCIO = 1.8 V. 2. VICM is depending on VID, input differential voltage, so the voltage on pin cannot exceed VINP/INM(min/max) requirements. VICM(min) = VINP/INM(min) + ½ VID, VICM(max) = VINP/INM(max) – ½ VID. Values in the table is based on minimum VID of +/- 100 mV. 3. VINP and VINM (max) must be less than or equal to VCCIO in all cases. 3.12.2. LVDS25E (Output Only) Three sides of the MachXO5-NX devices, Top, Left and Right, support LVDS25 outputs with emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3.2 is one possible solution for point-to-point signals. Table 3.18. LVDS25E DC Conditions Parameter Description Typical Unit VCCIO Output Driver Supply (±5%) 2.50 V ZOUT Driver Impedance 20 Ω RS Driver Series Resistor (±1%) 158 Ω RP Driver Parallel Resistor (±1%) 140 Ω RT Receiver Termination (±1%) 100 Ω VOH Output High Voltage 1.43 V VOL Output Low Voltage 1.07 V VOD Output Differential Voltage 0.35 V VCM Output Common Mode Voltage 1.25 V ZBACK Back Impedance 100.5 Ω IDC DC Output Current –6.03 mA
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 60 FPGA-DS-02102-0.80 3.12.4. SubLVDSE/SubLVDSEH (Output Only) SubLVDS output uses a pair of LVCMOS18 drivers with True and Complement outputs. The VCCIO of the bank used for subLVDSE or subLVDSEH needs to be powered by 1.8 V. SubLVDSE is for Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9; and subLVDSEH is for Bank 5 and Bank 6. Performance of the subLVDSE/subLVDSEH driver is limited to the performance of LVCMOS18. Table 3.20. SubLVDS Output DC Electrical Characteristics (Over Recommended Operating Conditions) Parameter Description Test Conditions Min Typ Max Unit VOD Output Differential Voltage Swing — — 150 — mV VOCM Output Common Mode Voltage Half the sum of the two Outputs — 0.9 — V VCCIO = +1.8 V SubLVDS Output SubLVDSE SubLVDSEH Sub-LVDS Recev ier 100 diff erential Rs = 267 ±1% Off-chipOn-chip Z0 = 50 Rs = 267 ±1% Rp = 121 ±1% Z0 = 50 RT = 100 ±1% PCB Traces, Connectors or Cables Off-chipOn-chip Figure 3.4. SubLVDS Output Interface 3.12.5. SLVS Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13 (SLVS-400) standard. This standard evolved from the traditional LVDS standard with smaller voltage swings and a lower common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power. The MachXO5-NX devices receive SLVS differential input with the LVDS input buffer. This LVDS input buffer is designed to cover wide input common mode range that can meet the SLVS input standard specified by the JEDEC standard. Table 3.21. SLVS Input DC Characteristics (Over Recommended Operating Conditions) Parameter Description Test Conditions Min Typ Max Unit VID Input Differential Threshold Voltage Over VICM range 70 — — mV VICM Input Common Mode Voltage Half the sum of the two Inputs 70 200 330 mV The SLVS output on the MachXO5-NX device is supported with the LVDS drivers found in Bank 5 and Bank 6. The LVDS driver on the MachXO5-NX device is a current controlled driver. It can be configured as LVDS driver, or configured with the 100 Ω differential termination with center-tap set to VOCM at 200 mV. This means the differential output driver can be placed into bank with VCCIO = 1.2 V, 1.5 V, or 1.8 V, even if it is powered by VCCIO.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 61 Table 3.22. SLVS Output DC Characteristics (Over Recommended Operating Conditions) Parameter Description Test Conditions Min Typ Max Unit VCCIO Bank VCCIO — –5% 1.2, 1.5, 1.8 + 5% V VOD Output Differential Voltage Swing — 140 200 270 mV VOCM Output Common Mode Voltage Half the sum of the two Outputs 150 200 250 mV ZOS Single-Ended Output Impedance — 37.5 50 62.5 Ω Figure 3.5. SLVS Interface 3.12.6. Soft MIPI D-PHY When Soft D-PHY is implemented inside the FPGA logic, the I/O interface needs to use sysI/O buffers to connect to external D-PHY pins. The MachXO5-NX sysI/O provides support of SLVS, as described in SLVS section, plus the LVCMOS12 input / output buffers together to support the High Speed (HS) and Low Power (LP) mode as defined in MIPI Alliance Specification for D-PHY. To support MIPI D-PHY with SLVS (LVDS) and LVCMOS12, the bank VCCIO cannot be set to 1.5 V or 1.8 V. It has to connect to 1.2 V, or 1.1 V. All other DC parameters are the same as those listed in SLVS section. DC parameters for the LP driver and receiver are the same as those listed in LVCMOS12.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 62 FPGA-DS-02102-0.80 LP Data_P LPenable HSenable HS Data LVCMOS12 SLVS Z0=50 Z0=50 MIPI Receiver
100 Diff
MIPI_LP_RX RXLP_P HS Data LVDS LP Data_N LPenable LVCMOS12 MIPI_LP_RX RXLP_N Figure 3.6. MIPI Interface
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 63 Table 3.23. Soft D-PHY Input Timing and Levels Symbol Description Conditions Min Typ Max Unit High Speed (Differential) Input DC Specifications VCMRX(DC) Common-mode Voltage in High Speed Mode — 70 — 330 mV VIDTH Differential Input HIGH Threshold — 70 — — mV VIDTL Differential Input LOW Threshold — — — –70 mV VIHHS Input HIGH Voltage (for HS mode) — — — 460 mV VILHS Input LOW Voltage — –40 — — mV VTERM-EN Single-ended voltage for HS Termination Enable4 — — — 450 mV ZID Differential Input Impedance — 80 100 125 Ω High Speed (Differential) Input AC Specifications ΔVCMRX(HF)1 Common-mode Interference (>450 MHz) — — — 100 mV ΔVCMRX(LF)2, 3 Common-mode Interference (50 MHz – 450 MHz) — –50 — 50 mV CCM Common-mode Termination — 60 pF Low Power (Single-Ended) Input DC Specifications VIH Low Power Mode Input HIGH Voltage — 740 — — mV VIL Low Power Mode Input LOW Voltage — — — 480 mV VIL-ULP Ultra Low Power Input LOW Voltage — — — 300 mV VHYST Low Power Mode Input Hysteresis — 25 — — mV ℮SPIKE Input Pulse Rejection — — — 300 V∙ps TMIN-RX Minimum Pulse Width Response — 20 — — ns VINT Peak Interference Amplitude — — — 200 mV fINT Interference Frequency — 450 — — MHz Notes: 1. This is peak amplitude of sine wave modulated to the receiver inputs. 2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs. 3. Exclude any static ground shift of 50 mV. 4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 64 FPGA-DS-02102-0.80 Table 3.24. Soft D-PHY Output Timing and Levels Symbol Description Conditions Min Typ Max Unit High Speed (Differential) Output DC Specifications VCMTX Common-mode Voltage in High Speed Mode — 150 200 250 mV |ΔVCMTX(1,0)| VCMTX Mismatch Between Differential HIGH and LOW — — — 7 mV |VOD| Output Differential Voltage |D-PHY-P – D-PHY- N| 140 200 270 mV |ΔVOD| VOD Mismatch Between Differential HIGH and LOW — — — 25 mV VOHHS Single-Ended Output HIGH Voltage — — — 410 mV ZOS Single Ended Output Impedance — 37.5 50 80 Ω ΔZOS ZOS mismatch — — — 20 % High Speed (Differential) Output AC Specifications ΔVCMTX(LF) Common-Mode Variation, 50 MHz–450 MHz — — — 25 mVRMS ΔVCMTX(HF) Common-Mode Variation, above 450 MHz — — — 15 mVRMS tR Output 20%–80% Rise Time Output 80%–20% Fall Time 0.08 Gbps ≤ tR ≤ 1.00 Gbps — — 0.30 UI 1.00 Gbps < tR ≤ 1.25 Gbps — — 0.434 UI tF Output Data Valid After CLK Output 0.08 Gbps ≤ tF ≤ 1.00 Gbps — — 0.30 UI 1.00 Gbps < tF ≤ 1.25 Gbps — — 0.419 UI Low Power (Single-Ended) Output DC Specifications VOH Low Power Mode Output HIGH Voltage 0.08 Gbps – 1.25 Gbps 1.07 1.2 1.3 V VOL Low Power Mode Input LOW Voltage — –50 — 50 mV ZOLP Output Impedance in Low Power Mode — 110 — — Ω Low Power (Single-Ended) Output AC Specifications tRLP 15%–85% Rise Time — — — 25 ns tFLP 85%–15% Fall Time — — — 25 ns tREOT HS – LP Mode Rise and Fall Time, 30%–85% — — — 35 ns TLP-PULSE-TX Pulse Width of the LP Exclusive-OR Clock First LP XOR Clock Pulse after STOP State or Last Pulse before STOP State 40 — — ns All Other Pulses 20 — — ns TLP-PER-TX Period of the LP Exclusive-OR Clock — 90 — — ns CLOAD Load Capacitance — 0 — 70 pF Table 3.25. Soft D-PHY Clock Signal Specification Symbol Description Conditions Min Typ Max Unit Clock Signal Specification UI Instantaneous UIINST — — — 12.5 ns UI Variation ∆UI — –10% — 10% UI — –5% — 5% UI
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 65 Table 3.26. Soft D-PHY Data-Clock Timing Specifications Symbol Description Conditions Min Typ Max Unit Data-Clock Timing Specifications TSKEW[TX] Data to Clock Skew
0.08 Gbps ≤ TSKEW[TX]
≤ 1.00 Gbps –0.15 — 0.15 UIINST
1.00 Gbps < TSKEW[TX]
≤ 1.25 Gbps –0.20 — 0.20 UIINST TSKEW[TLIS] Data to Clock Skew
0.08 Gbps ≤ TSKEW[TLIS]
≤ 1.00 Gbps 0.15 — — UIINST
1.00 Gbps < TSKEW[TLIS]
≤ 1.25 Gbps 0.20 — — UIINST TSETUP[RX] Input Data Setup Before CLK
0.08 Gbps ≤ TSETUP[RX]
≤ 1.00 Gbps 0.15 — — UI
1.00 Gbps < TSETUP[RX]
≤ 1.25 Gbps 0.20 — — UI THOLD[RX] Input Data Hold After CLK
0.08 Gbps ≤ THOLD[RX]
≤ 1.00 Gbps –0.15 — 0.15 UI
1.00 Gbps < THOLD[RX]
≤ 1.25 Gbps –0.20 — 0.20 UI 3.12.7. Differential HSTL15D (Output Only) Differential HSTL outputs are implemented as a pair of complementary single-ended HSTL outputs. 3.12.8. Differential SSTL135D, SSTL15D (Output Only) Differential SSTL is used for differential clock in DDR3/DDR3L memory interface. All differential SSTL outputs are implemented as a pair of complementary single-ended SSTL outputs. All allowable single-ended output classes (class I and class II) are supported. 3.12.9. Differential HSUL12D (Output Only) Differential HSUL is used for differential clock in LPDDR2/LPDDR3 memory interface. All differential HSUL outputs are implemented as a pair of complementary single-ended HSUL12 outputs. All allowable single-ended drive strengths are supported. 3.12.10. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only) Differential LVCMOS and LVTTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output drive strengths are supported.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 66 FPGA-DS-02102-0.80 3.13. MachXO5-NX Maximum sysI/O Buffer Speed Over recommended operating conditions. Table 3.27. MachXO5-NX Maximum I/O Buffer Speed1, 2, 3, 4, 7 Buffer Description Banks Max Unit Maximum sysI/O Input Frequency Single-Ended LVCMOS33 LVCMOS33, VCCIO = 3.3 V 0, 1, 2, 3, 4, 7, 8, 9 200 MHz LVTTL33 LVTTL33, VCCIO = 3.3 V 0, 1, 2, 3, 4, 7, 8, 9 200 MHz LVCMOS25 LVCMOS25, VCCIO = 2.5 V 0, 1, 2, 3, 4, 7, 8, 9 200 MHz LVCMOS18 5 LVCMOS18, VCCIO = 1.8 V 0, 2, 3, 4, 7, 8, 9 200 MHz LVCMOS18H LVCMOS18, VCCIO = 1.8 V 5, 6 200 MHz LVCMOS15 5 LVCMOS15, VCCIO = 1.5 V 0, 2, 3, 4, 7, 8, 9 100 MHz LVCMOS15H 5 LVCMOS15, VCCIO = 1.5 V 5, 6 150 MHz LVCMOS12 5 LVCMOS12, VCCIO = 1.2 V 0, 2, 3, 4, 7, 8, 9 50 MHz LVCMOS12H 5 LVCMOS12, VCCIO = 1.2 V 5, 6 100 MHz LVCMOS10 5 LVCMOS 1.0, VCCIO = 1.2 V 0, 2, 3, 4, 7, 8, 9 50 MHz LVCMOS10H 5 LVCMOS 1.0, VCCIO = 1.0 V 5, 6 50 MHz LVCMOS10R LVCMOS 1.0, VCCIO independent 5, 6 50 MHz SSTL15_I, SSTL15_II SSTL_15, VCCIO = 1.5 V 5, 6 1066 Mbps SSTL135_I, SSTL135_II SSTL_135, VCCIO = 1.35 V 5, 6 1066 Mbps HSUL12 HSUL_12, VCCIO = 1.2 V 5, 6 1066 Mbps HSTL15 HSTL15, VCCIO = 1.5 V 5, 6 1066 Mbps MIPI D-PHY (LP Mode) MIPI, Low Power Mode, VCCIO = 1.2 V 5, 6 10 Mbps Differential LVDS LVDS, VCCIO independent 5, 6 1250 Mbps subLVDS subLVDS, VCCIO independent 5, 6 1250 Mbps SLVS SLVS similar to MIPI HS, VCCIO independent 5, 6 1250 Mbps MIPI D-PHY (HS Mode) MIPI, High Speed Mode, VCCIO = 1.2 V 5, 6 1250 Mbps SSTL15D Differential SSTL15, VCCIO independent 5, 6 1066 Mbps SSTL135D Differential SSTL135, VCCIO independent 5, 6 1066 Mbps HUSL12D Differential HSUL12, VCCIO independent 5, 6 1066 Mbps HSTL15D Differential HSTL15, VCCIO independent 5, 6 250 Mbps Maximum sysI/O Output Frequency Single-Ended LVCMOS33 (all drive strengths) LVCMOS33, VCCIO = 3.3 V 0, 1, 2, 3, 4, 7, 8, 9 200 MHz LVCMOS33 (RS50) LVCMOS33, VCCIO = 3.3 V, RSERIES = 50 Ω 0, 1, 2, 3, 4, 7, 8, 9 200 MHz LVTTL33 (all drive strengths) LVTTL33, VCCIO = 3.3 V 0, 1, 2, 3, 4, 7, 8, 9 200 MHz LVTTL33 (RS50) LVTTL33, VCCIO = 3.3 V, RSERIES = 50 Ω 0, 1, 2, 3, 4, 7, 8, 9 200 MHz LVCMOS25 (all drive strengths) LVCMOS25, VCCIO = 2.5 V 0, 2, 3, 4, 7, 8, 9 200 MHz LVCMOS25 (RS50) LVCMOS25, VCCIO = 2.5 V, RSERIES = 50 Ω 0, 2, 3, 4, 7, 8, 9 200 MHz
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 67 Buffer Description Banks Max Unit LVCMOS18 (all drive strengths) LVCMOS18, VCCIO = 1.8 V 0, 2, 3, 4, 7, 8, 9 200 MHz LVCMOS18 (RS50) LVCMOS18, VCCIO = 1.8 V, RSERIES = 50 Ω 0, 2, 3, 4, 7, 8, 9 200 MHz LVCMOS18H (all drive strengths) LVCMOS18, VCCIO = 1.8 V 5, 6 200 MHz LVCMOS18H (RS50) LVCMOS18, VCCIO = 1.8 V, RSERIES = 50 Ω 5, 6 200 MHz LVCMOS15 (all drive strengths) LVCMOS15, VCCIO = 1.5 V 0, 2, 3, 4, 7, 8, 9 100 MHz LVCMOS15H (all drive strengths) LVCMOS15, VCCIO = 1.5 V 5, 6 150 MHz LVCMOS12 (all drive strengths) LVCMOS12, VCCIO = 1.2 V 0, 2, 3, 4, 7, 8, 9 50 MHz LVCMOS12H (all drive strengths) LVCMOS12, VCCIO = 1.2 V 5, 6 100 MHz LVCMOS10H (all drive strengths) LVCMOS12, VCCIO = 1.2 V 5, 6 50 MHz SSTL15_I, SSTL15_II SSTL_15, VCCIO = 1.5 V 5, 6 1066 Mbps SSTL135_I, SSTL135_II SSTL_135, VCCIO = 1.35 V 5, 6 1066 Mbps HSUL12 (all drive strengths) HSUL_12, VCCIO = 1.2 V 5, 6 1066 Mbps HSTL15 HSTL15, VCCIO = 1.5 V 5, 6 250 Mbps MIPI D-PHY (LP Mode) MIPI, Low Power Mode, VCCIO = 1.2 V 5, 6 10 Mbps Differential9 LVDS LVDS, VCCIO = 1.8 V 5, 6 1250 Mbps LVDS25E6 LVDS25, Emulated, VCCIO = 2.5 V 0, 2, 3, 4, 7, 8, 9 400 Mbps SubLVDSE6 subLVDS, Emulated, VCCIO = 1.8 V 0, 2, 3, 4, 7, 8, 9 400 Mbps SubLVDSEH6 subLVDS, Emulated, VCCIO = 1.8 V 5, 6 800 Mbps SLVS SLVS similar to MIPI, VCCIO = 1.2 V 5, 6 1250 Mbps MIPI D-PHY (HS Mode) MIPI, High Speed Mode, VCCIO = 1.2 V 5, 6 1250 Mbps SSTL15D Differential SSTL15, VCCIO = 1.5 V 5, 6 1066 Mbps SSTL135D Differential SSTL135, VCCIO = 1.35 V 5, 6 1066 Mbps HUSL12D Differential HSUL12, VCCIO = 1.2 V 5, 6 1066 Mbps HSTL15D Differential HSTL15, VCCIO = 1.5 V 5, 6 250 Mbps Notes: 1. Maximum I/O speed is the maximum switching rate of the I/O operating within the guidelines of the defining standard. The actual interface speed performance using the I/O also depends on other factors, such as internal and external timing. 2. These numbers are characterized but not test on every device. 3. Performance is specified in MHz, as defined in clock rate when the sysI/O is used as pin. For data rate performance, this can be converted to Mbps, which equals to 2 times the clock rate. 4. LVCMOS and LVTTL are measured with load specified in Table 3.42. 5. These LVCMOS inputs can be placed in different VCCIO voltage. Performance may vary. Please refer to Lattice Design Software 6. These emulated outputs performance is based on externally properly terminated as described in LVDS25E (Output Only) and SubLVDSE/SubLVDSEH (Output Only). 7. All speeds are measured with fast slew. 8. For maximum differential I/O performance only Differential I/O should be placed in the bottom I/O banks. If this is not possible, the following will impact on maximum performance: a. If Fast Slew Rate LVCMOS I/O are used, they should be limited to no more than nine I/O (adjacent), four I/O (same bank), 55 I/O (left/right banks) to keep degradation below 50%. b. If non-Differential I/O (SLOW SLEW) are placed on the bottom but not within the same bank as differential I/O, then the maximum Differential performance is degraded to 70% of original when 21 aggressors are toggling. c. If non-Differential I/O (SLOW SLEW) are placed within the same bank as Differential I/O then the maximum performance is degraded to 50% of original when 16 aggressor are toggling. d. No performance impact if MIPI LP and MIPI HS are in the same bank. e. If Differential RX/TX I/O are both placed within the same bank then the maximum performance is degraded to 90%. f. For DDR3/3L, LPDDR2/3 separate DQ/DQS groups from Address/Commands/CLK groups into separate banks.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 68 FPGA-DS-02102-0.80 3.14. Typical Building Block Function Performance These building block functions can be generated using Lattice Design Software Tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. Table 3.28. Pin-to-Pin Performance Function Typ. @ VCC =
1.0 V Unit
16-bit Decoder (I/O configured with LVCMOS18, Top, Left and Right Banks) — ns 16-bit Decoder (I/O configured with HSTL15_I, Bottom Banks) — ns 16:1 Mux (I/O configured with LVCMOS18, Top, Left and Right Banks) — ns 16:1 Mux (I/O configured with HSTL15_I, Bottom Banks) — ns Note: These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. Table 3.29. Register-to-Register Performance Function Typ. @ VCC = 16-bit Adder —2 MHz 32-bit Adder — MHz 16-bit Counter — MHz 32-bit Counter — MHz Embedded Memory Functions 512 × 36 Single Port RAM, with Output Register —2 MHz 1024 × 18 True-Dual Port RAM using same clock, with EBR Output Registers —2 MHz 1024 × 18 True-Dual Port RAM using asynchronous clocks, with EBR Output Registers —2 MHz Large Memory Functions 32 k × 32 Single Port RAM, with Output Register —2 MHz 32 k × 32 Single Port RAM with ECC, with Output Register —2 MHz 32 k × 32 True-Dual Port RAM using same clock, with Output Registers — MHz Distributed Memory Functions 16 × 4 Single Port RAM (One PFU) —2 MHz 16 × 2 Pseudo-Dual Port RAM (One PFU) —2 MHz 16 × 4 Pseudo-Dual Port (Two PFUs) —2 MHz DSP Functions 9 × 9 Multiplier with Input Output Registers — MHz 9 × 9 Multiplier with Input/Pipelined/Output Registers — MHz 18 × 18 Multiplier with Input/Output Registers — MHz 18 × 18 Multiplier with Input/Pipelined/Output Registers — MHz 36 × 36 Multiplier with Input/Output Registers — MHz 36 × 36 Multiplier with Input/Pipelined/Output Registers — MHz MAC 9 × 9 with Input/Output Registers — MHz MAC 9 × 9 with Input/Pipelined/Output Registers — MHz Notes: 1. The Clock port is configured with LVDS I/O type. Performance Grade: 9_High-Performance_1.0V. 2. Limited by the Minimum Pulse Width of the component
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 69 3. These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 4. For the Pipelined designs, the number of pipeline stages used are 2. 3.15. LMMI Table 3.30 summarizes the performance of the LMMI interface with supported IPs. Additional timing requirement and constraint can be identified through the Lattice Radiance design tools. Table 3.30. LMMI FMAX Summary IP FMAX (MHz) CDR0 — CDR1 — CRE — I2C — PLL_ULC — PLL_LRC — 3.16. Derating Timing Tables Logic timing provided in the following sections of this data sheet and the Lattice Radiant design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Lattice Radiant design tool can provide logic timing numbers at a particular temperature and voltage. 3.17. MachXO5-NX External Switching Characteristics Over recommended commercial operating conditions. Table 3.31. MachXO5-NX External Switching Characteristics (VCC = 1.0 V) Parameter Description –9 –8 –7 Unit Min Max Min Max Min Max Clocks Primary Clock fMAX_PRI Frequency for Primary Clock — — — — — — MHz tW_PRI Clock Pulse Width for tSKEW_PRI Primary Clock Skew Within a Edge Clock fMAX_EDGE Frequency for Edge Clock tW_EDGE Clock Pulse Width for Edge tSKEW_EDGE Edge Clock Skew Within a Generic SDR Input General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL tCO Clock to Output – PIO Output Register — — — — — — ns
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 73 Parameter Description –9 –8 –7 Unit Min Max Min Max Min Max tDVE_GDDRX5 Input Data Hold After CLK tWINDOW_GDDRX5A Input Data Valid Window — — — — — — ns tDIA_GDDRX5 Output Data Invalid After tDIB_GDDRX5 Output Data Invalid Before fDATA_GDDRX5 Input/Output Data Rate — — — — — — Mbps fMAX_GDDRX5 Frequency for ECLK — — — — — — MHz ½ UI Half of Data Bit Time, or 90 fPCLK PCLK frequency — — — — — — MHz Output TX to Input RX Margin per Edge — — — — — — ns Soft D-PHY DDRX4 Inputs/Outputs with Clock and Data Centered at Pin, using PCLK Clock Input tSU_GDDRX4_MP Input Data Set-Up Before CLK tHO_GDDRX4_MP Input Data Hold After CLK — — — — — — ns tDVB_GDDRX4_MP Output Data Valid Before CLK Output tDQVA_GDDRX4_MP Output Data Valid After CLK Output fDATA_GDDRX4_MP Input Data Bit Rate for MIPI ½ UI Half of Data Bit Time, or 90 fPCLK PCLK frequency — — — — — — MHz Output TX to Input RX Margin per Edge — — — — — — ns Video DDRX71 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) using PLL Clock Input – Figure 3.12 and Figure 3.13 tRPBi_DVA Input Valid Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) tRPBi_DVE Input Hold Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) tTPBi_DOV Data Output Valid Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) tTPBi_DOI Data Output Invalid Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) tTPBi_skew_UI TX skew in UI — — — — — — UI tB Serial Data Bit Time, = 1UI — — — — — — ns fDATA_TX71 DDR71 Serial Data Rate — — — — — — Mbps fMAX_TX71 DDR71 ECLK Frequency — — — — — — MHz fCLKIN 7:1 Clock (PCLK) Frequency — — — — — — MHz
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 74 FPGA-DS-02102-0.80 Parameter Description –9 –8 –7 Unit Min Max Min Max Min Max Output TX to Input RX Margin per Edge — — — — — — ns Memory Interface DDR3/DDR3L/LPDDR2/LPDDR3 READ (DQ Input Data are Aligned to DQS) – Figure 3.8 tDVBDQ_DDR3 tDVBDQ_DDR3L tDVBDQ_LPDDR2 tDVBDQ_LPDDR3 Data Input Valid before DQS tDVADQ_DDR3 tDVADQ_DDR3L tDVADQ_LPDDR2 tDVADQ_LPDDR3 Data Input Valid after DQS fDATA_DDR3 fDATA_DDR3L fDATA_LPDDR2 fDATA_LPDDR3 DDR Memory Data Rate — — — — — — Mb/s fMAX_ECLK_DDR3 fMAX_ECLK_DDR3L fMAX_ECLK_LPDDR2 fMAX_ECLK_LPDDR3 DDR Memory ECLK fMAX_SCLK_DDR3 fMAX_SCLK_DDR3L fMAX_SCLK_LPDDR2 fMAX_SCLK_LPDDR3 DDR Memory SCLK DDR3/DDR3L/LPDDR2/LPDDR3 WRITE (DQ Output Data are Centered to DQS) – Figure 3.11 tDQVBS_DDR3 tDQVBS_DDR3L tDQVBS_LPDDR2 tDQVBS_LPDDR3 Data Output Valid before DQS Output — — — — — — ns + 1/2 UI tDQVAS_DDR3 tDQVAS_DDR3L tDQVAS_LPDDR2 tDQVAS_LPDDR3 Data Output Valid after DQS Output — — — — — — ns + 1/2 UI fDATA_DDR3 fDATA_DDR3L fDATA_LPDDR2 fDATA_LPDDR3 DDR Memory Data Rate — — — — — — Mb/s fMAX_ECLK_DDR3 fMAX_ECLK_DDR3L fMAX_ECLK_LPDDR2 fMAX_ECLK_LPDDR3 DDR Memory ECLK fMAX_SCLK_DDR3 fMAX_SCLK_DDR3L fMAX_SCLK_LPDDR2 fMAX_SCLK_LPDDR3 DDR Memory SCLK Notes: 1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice Radiant software. 2. General I/O timing numbers are based on LVCMOS 1.8, 8 mA, Fast Slew Rate, 0 pf load. Generic DDR timing are numbers based on LVDS I/O. DDR3 timing numbers are based on SSTL15. LPDDR2 and LPDDR3 timing numbers are based on HSUL12. 3. Uses LVDS I/O standard for measurements. 4. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment. 5. All numbers are generated with the Lattice Radiant software.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 76 FPGA-DS-02102-0.80 Tx CLK (out) Tx DATA (out) 1 UI tDIA tDIB tDIA tDIB Figure 3.10. Transmit TX.CLK.Aligned Waveforms Clock In
108 MHz
Receiver – Shown for one LVDS Channel # of Bits Data In
756 Mb/s
Transmitter – Shown for one LVDS Channel Clock Out # of Bits Data Out For each Channel: 7-bit Output Words to FPGA Fabric Bit # 00 – 1 00 – 2 00 – 3 00 – 4 00 – 5 00 – 6 00 – 7 Bit # 10 – 8 11 – 9 12 – 10 13 – 11 14 – 12 15 – 13 16 – 14 Bit # 20 – 15 21 – 16 22 – 17 23 – 18 24 – 19 25 – 20 26 – 21 Bit # 30 – 22 31 – 23 32 – 24 33 – 25 34 – 26 35 – 27 36 – 28 Bit # 30 – 15 31 – 16 32 – 17 33 – 18 34 – 19 35 – 20 36 – 21 Bit # 40 – 22 41 – 23 42 – 24 43 – 25 44 – 26 45 – 27 46 – 28 Bit # 20 – 8 21 – 9 22 – 10 23 – 11 24 – 12 25 – 13 26 – 14 Bit # 10 – 1 11 – 2 12 – 3 13 – 4 14 – 5 15 – 6 16 – 7 For each Channel: 7-bit Output Words to FPGA Fabric Figure 3.11. DDRX71 Video Timing Waveforms
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 78 FPGA-DS-02102-0.80 3.18. MachXO5-NX sysCLOCK PLL Timing (VCC = 1.0 V) Over recommended operating conditions. Table 3.32. sysCLOCK PLL Timing (VCC = 1.0 V) Parameter Descriptions Conditions Min Typ. Max Units fIN Input Clock Frequency (CLKI, CLKFB) — — — — MHz fOUT Output Clock Frequency — — — — MHz fVCO PLL VCO Frequency — — — — MHz fPFD3 Phase Detector Input Frequency Without Fractional- N Enabled — — — MHz With Fractional-N Enabled — — — MHz AC Characteristics tDT Output Clock Duty Cycle — — — — % tPH4 Output Phase Accuracy — — — — % tOPJIT1 Output Clock Period Jitter fOUT ≥ 200 MHz — — — ps p-p fOUT < 200 MHz — — — UIPP Output Clock Cycle-to-Cycle Jitter fOUT ≥ 200 MHz — — — ps p-p fOUT < 200 MHz — — — UIPP Output Clock Phase Jitter fPFD ≥ 200 MHz — — — ps p-p fPFD < 200 MHz — — — UIPP Output Clock Period Jitter (Fractional-N) fOUT ≥ 200 MHz — — — ps p-p fOUT < 200 MHz — — — UIPP Output Clock Cycle-to-Cycle Jitter (Fractional-N) fOUT ≥ 200 MHz — — — ps p-p fOUT < 200 MHz — — — UIPP fBW4 PLL Loop Bandwidth — — — — MHz tLOCK2 PLL Lock-in Time — — — — ms tUNLOCK PLL Unlock Time (from RESET goes HIGH) — — — — ns tIPJIT Input Clock Period Jitter fPFD ≥ 20 MHz — — — ps p-p fPFD < 20 MHz — — — UIPP tHI Input Clock High Time 90% to 90% — — — ns tLO Input Clock Low Time 10% to 10% — — — ns tRST RST/ Pulse Width — — — — ms fSSC_MOD Spread Spectrum Clock Modulation Frequency — — — — kHz fSSC_MOD_AMP Spread Spectrum Clock Modulation Amplitude Range — — — — % fSSC_MOD_STEP Spread Spectrum Clock Modulation Amplitude Step Size — — — — % Notes: 1. Jitter sample is taken over 10,000 samples for Period jitter, and 1,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPFD > 10 MHz. For fPFD < 10 MHz, the jitter numbers may not be met in certain conditions.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 79 4. Result from Lattice Radiant software. 3.19. MachXO5-NX Internal Oscillators Characteristics Table 3.33. Internal Oscillators (VCC = 1.0 V) Symbol Parameter Description Min Typ Max Unit fCLKHF HFOSC CLKK Clock Frequency — — — MHz fCLKLF LFOSC CLKK Clock Frequency — — — kHz DCHCLKHF HFOSC Duty Cycle (Clock High Period) — — — % DCHCLKLF LFOSC Duty Cycle (Clock High Period) — — — % 3.20. MachXO5-NX Flash Download Time Table 3.34. Flash Download Time Symbol Parameter Device Typ. Units tREFRESH POR to Device I/O Active LFMXO5-25 — ms Notes: Assumes sysMEM EBR initialized to an all zero pattern if they are used. The Flash download time is measured starting from the maximum voltage of POR trip point. 3.21. MachXO5-NX User I2C Characteristics Table 3.35. User I2C Specifications (VCC = 1.0 V) Symbol Parameter
Description
STD Mode FAST Mode FAST Mode Plus2 Units Min Typ Max Min Typ Max Min Typ Max fscl SCL Clock TDELAY1 Optional delay Notes: 1. Refer to the I2C Specification for timing requirements. User design should set constraints in Lattice Design Software to meet this industrial I2C Specification. 2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I2C bus. Internal pull up may not be sufficient to support the maximum speed.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 80 FPGA-DS-02102-0.80 3.22. MachXO5-NX Analog-Digital Converter (ADC) Block Characteristics Table 3.36. ADC Specifications1 Symbol Description Condition Min Typ Max Unit VREFINT_ADC ADC Internal Reference Voltage — 1.142 1.2 1.262 V VREFEXT_ADC ADC External Reference Voltage — 1.0 — 1.8 V NRES_ADC ADC Resolution — — 12 — bits ENOBADC Effective Number of Bits — 9.9 11 — bits VSR_ADC ADC Input Range Bipolar Mode, Internal VREF VCM_ADC ― VREFINT_ADC/4 VCM_ADC VCM_ADC + VREFINT_ADC/ V Bipolar Mode, External VREF VCM_ADC ― VREFEXT_ADC/4 VREFEXT_ADC VCM_ADC + VREFEXT_ADC/ V Uni-polar Mode, Internal VREF 0 — VREFINT_ADC V Uni-polar Mode, External VREF 0 — VREFEXT_ADC V VCM_ADC ADC Input Common Mode Voltage (for fully differential signals) Internal VREF — VREFINT_ADC/2 — V External VREF — VREFEXT_ADC/2 — V fCLK_ADC ADC Clock Frequency — — 25 40 MHz DCCLK_ADC ADC Clock Duty Cycle — 48 50 52 % fINPUT_ADC ADC Input Frequency — — — 500 kHz FSADC ADC Sampling Rate — — 1 — MS/s NTRACK_ADC ADC Input Tracking Time — 4 — — cycles3 RIN_ADC ADC Input Equivalent Resistance
1 MS/s, Sampled @ 2 clock
cycles — 116 — KΩ tCAL_ADC ADC Calibration Time — — — 6500 cycles3 LOUTput_ADC ADC Conversion Time Includes minimum tracking time of four cycles 25 — — cycles3 DNLADC ADC Differential Nonlinearity — -1 — 1 LSB INLADC ADC Integral Nonlinearity — -22 — 2.21 LSB SFDRADC ADC Spurious Free Dynamic Range — 67.7 77 — dBc THDADC ADC Total Harmonic Distortion — — -76 -66.8 dB SNRADC ADC Signal to Noise Ratio — 61.9 68 — dB SNDRADC ADC Signal to Noise Plus Distortion Ratio — 61.7 67 — dB ERRGAIN_ADC ADC Gain Error — -0.5 — 0.5 % FSADC ERROFFSET_ADC ADC Offset Error — -2 — 2 LSB CIN_ADC ADC Input Equivalent Capacitance — — 2 — pF Notes: 1. ADC is available in select speed grades. See Ordering Information. 2. Not tested; guaranteed by design. 3. ADC Sample Clock cycles. See ADC User Guide for Nexus Platform (FPGA-TN-02129) for more details.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 81 3.23. MachXO5-NX Comparator Block Characteristics Table 3.37. Comparator Specifications Symbol Description Min Typ Max Unit fIN_COMP Comparator Input Frequency — — 10 MHz VIN_COMP Comparator Input Voltage 0 — VCCADC18 V VOFFSET_COMP Comparator Input Offset -23 — 24 mV VHYST_COMP Comparator Input Hysteresis 10 — 31 mV VLATENCY_COMP Comparator Latency — — 31 ns Note: Comparator is available in select speed grades. See Ordering Information. 3.24. MachXO5-NX Digital Temperature Readout Characteristics Digital temperature Readout (DTR) is implemented in one of the channels of ADC1. Table 3.38. DTR Specifications1,2 Symbol Description Condition Min Typ Max Unit DTRRANGE DTR Detect Temperature Range — –40 — 100 °C DTRACCURACY DTR Accuracy with external voltage1 reference range of 1.0 V to 1.8 V -13 ±4 13 °C DTRRESOLUTION DTR Resolution with external voltage reference -0.3 — 0.3 °C Notes: 1. External voltage reference (VREF) should be 0.1% accurate or better. DTR sensitivity to VREF is -4.1 °C per VREF per-cent (for example, if the VREF is 1 % low, then the DTR will read +4.1 °C high). 2. DTR is available in select speed grades. See Ordering Information. 3.25. MachXO5-NX Hardened SGMII Receiver Characteristics 3.25.1. SGMII Rx Specifications Over recommended operating conditions. Table 3.39. SGMII Rx Symbol Description Test Conditions Min Typ Max Unit fDATA SGMII Data Rate — — 1250 — MHz fREFCLK SGMII Reference Clock Frequency (Data Rate/10) — — 125 — MHz JTOL_Dj Jitter Tolerance, Deterministic Periodic jitter < 300 kHz — — 0.11 UI JTOL_Tj Jitter Tolerance, Total Periodic jitter < 300 kHz — — 0.31 UI Δf/f Data Rate and Reference Clock Accuracy — -300 — 300 ppm Note: 1. JTOT can meet the following jitter mask specification: 0 to 3.5 kHz: 10 UI; 3.5 to 700 kHz: log-log slope 10 UI to 0.05 UI; above 700 kHz: 0.05 UI.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 82 FPGA-DS-02102-0.80 3.26. MachXO5-NX sysCONFIG Port Timing Specifications Over recommended operating conditions. Table 3.40. MachXO5-NX sysCONFIG Port Timing Specifications Symbol Parameter Device Min Typ. Max Unit Slave SPI/I2C/I3C POR / REFRESH Timing tMSPI_INH Time during POR, from VCC, VCCAUX, VCCIO0 or VCCIO1 (whichever is the last) pass POR trip voltage, or REFRESH command executed, to pull PROGRAMN LOW to prevent entering MSPI mode — — — — µs tACT_PROGRAMN_H Minimum time driving PROGRAMN HIGH after last activation clock — — — — ns tCONFIG_CCLK Minimum time to start driving CCLK (SSPI) after PROGRAMN HIGH — — — — ns tCONFIG_SCL Minimum time to start driving SCL (I2C/I3C) after PROGRAMN HIGH — — — — ns PROGRAMN Configuration Timing tPROGRAMN PROGRAMN LOW pulse accepted — — — — ns tPROGRAMN_RJ PROGRAMN LOW pulse rejected — — — — ns tINIT_LOW PROGRAMN LOW to INITN LOW — — — — ns tINIT_HIGH PROGRAMN LOW to INITN HIGH — — — — µs — — — — µs tDONE_LOW PROGRAMN LOW to DONE LOW — — — — µs tDONE_HIGH PROGRAMN HIGH to DONE HIGH — — — — s tIODISS PROGRAMN LOW to I/O Disabled — — — — ns Slave SPI fCCLK CCLK input clock frequency — — — — MHz tCCLKH CCLK input clock pulse width HIGH — — — — ns tCCLKL CCLK input clock pulse width LOW — — — — ns tVMC_SLAVE Time from rising edge of INITN to Slave CCLK driven — — — — ns tVMC_MASTER CCLK input clock duty cycle — — — — % tSU_SSI SSI to CCLK setup time — — — — ns tHD_SSI SSI to CCLK hold time — — — — ns tCO_SSO CCLK falling edge to valid SSO output — — — — ns tEN_SSO CCLK falling edge to SSO output enabled — — — — ns tDIS_SSO CCLK falling edge to SSO output disabled — — — — ns tHIGH_SCSN SCSN HIGH time — — — — ns tSU_SCSN SCSN to CCLK setup time — — — — ns tHD_SCSN SCSN to CCLK hold time — — — — ns I2C/I3C fSCL_I2C SCL input clock frequency for I2C — — — — MHz fSCL_I3C SCL input clock frequency for I3C — — — — MHz tSCLH_I2C SCL input clock pulse width HIGH for I2C — — — — ns tSCLL_I2C SCL input clock pulse width LOW for I2C — — — — ns tSU_SDA_I2C SDA to SCL setup time for I2C — — — — ns tHD_SDA_I2C SDA to SCL hold time for I2C — — — — ns tSU_SDA_I3C SDA to SCL setup time for I3C — — — — ns tHD_SDA_I3C SDA to SCL hold time for I3C — — — — ns
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 83 Symbol Parameter Device Min Typ. Max Unit tCO_SDA SCL falling edge to valid SDA output — — — — ns tEN_SDA SCL falling edge to SDA output enabled — — — — ns tDIS_SDA SCL falling edge to SDA output disabled — — — — ns Wake-Up Timing tDONE_HIGH Last configuration clock cycle to DONE going HIGH — — — — µs tFIO_EN User I/O enabled in Fast I/O Mode — — — — M cycles — — — — M cycles tIOEN Config clock to user I/O enabled — — — — ns PROGRAMN Figure 3.14. Slave SPI/I2C/I3C POR/REFRESH Timing
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 86 FPGA-DS-02102-0.80 3.27. JTAG Port Timing Specifications Over recommended operating conditions. Table 3.41. JTAG Port Timing Specifications Symbol Parameter Min Typ. Max Units fMAX TCK clock frequency — — — MHz tBTCPH TCK clock pulse width high — — — ns tBTCPL TCK clock pulse width low — — — ns tBTS TCK TAP setup time — — — ns tBTH TCK TAP hold time — — — ns tBTRF TAP controller TDO rise/fall time* — — — mV/ns tBTCO TAP controller falling edge of clock to valid output — — — ns tBTCODIS TAP controller falling edge of clock to valid disable — — — ns tBTCOEN TAP controller falling edge of clock to valid enable — — — ns tBTCRS BSCAN test capture register setup time — — — ns tBTCRH BSCAN test capture register hold time — — — ns tBUTCO BSCAN test update register, falling edge of clock to valid output — — — ns tBTUODIS BSCAN test update register, falling edge of clock to valid disable — — — ns tBTUPOEN BSCAN test update register, falling edge of clock to valid enable — — — ns *Note: Based on default IO setting of slow slew rate. TMS TDI TCK TDO Data to be Captured from I/O Data to be driven out to I/O ataD dilaVataD dilaV ataD dilaVataD dilaV Data Captured tBTCPH tBTCPL tBTCOEN tBTCRS tBTUPOEN tBUTCO tBTUODIS tBTCRH tBTCO tBTCODIS tBTS tBTH tBTCP Figure 3.19. JTAG Port Timing Waveforms
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 88 FPGA-DS-02102-0.80 4. Pinout Information 4.1. Signal Descriptions Signal Name Bank Type Description Power and GND Vss — GND Ground for internal FPGA logic and I/O VCC — Power Power supply pins for core logic. VCC is connected to 1.0 V (nom.) supply voltage. Power On Reset (POR) monitors this supply voltage. VCCAUXA — Power Auxiliary power supply pin for internal analog circuitry. This supply is connected to 1.8 V (nom.) supply voltage. POR monitors this supply voltage. VCCAUX — Power Auxiliary power supply pin for I/O Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9. This supply is connected to 1.8 V (nom.) supply voltage, and is used for generating stable drive current for the I/O. VCCAUXHx — Power Auxiliary power supply pin for I/O Bank 5 and Bank 6. This supply is connected to 1.8 V (nom.) supply voltage, and is used for generating stable current for the differential input comparators. VCCIOx 0-9 Power Power supply pins for I/O bank x. VCCIO1 must be connected to (nom.) 3.3 V. For x = 0, 2, 3, 4, 7, 8 and 9 VCCIO can be connected to (nom.) 1.2 V, 1.5 For x = 5 and 6, VCCIO can be connected to (nom.) 1.0 V, 1.2 V, 1.35 V, 1.5 V, or 1.8 V. There are dedicated and shared configuration pins in banks 1 and 2. POR monitors these banks supply voltages. VCCADC18 — Power 1.8 V (nom.) power supply for the ADC block. Dedicated Pins Dedicated Configuration I/O Pin JTAG_EN 1 Input LVCMOS input pin. This input selects the JTAG shared GPIO to be used for JTAG 0 = GPIO 1 = JTAG Dedicated ADC I/O Pins ADC_REF[0, 1] — Input ADC reference voltage, for each of the 2 ADC converters. If not used, tie to ground. ADC_DP/N[0, 1] — Input Dedicated ADC input pairs, for each of the 2 ADC converters. If not used, tie to ground. Misc Pins NC — — No connect. RESERVED — — This pin is reserved and should not be connected to anything on the board. General Purpose I/O Pins
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 89 Signal Name Bank Type Description P[T/B/L/R] [Number]_[A/B] T = 0, 1 R = 2, 3, 4 B = 5, 6, 10, 11 L = 7, 8, 9 Input, Output, Bi-Dir Programmable User I/O: [T/B/L/R] indicates the package pin/ball is in T (Top), B (Bottom), L (Left), or R (Right) edge of the device. [Number] identifies the PIO [A/B] pair. [A/B] shows the package pin/ball is A or B signal in the pair. PIO A and PIO B are grouped as a pair. Each A/B pair in the bottom banks supports true differential input and output buffers. When configured as differential input, differential termination of 100 Ω can be selected. Each A/B pair in the top, left and right banks does not support true differential input or output buffer. It supports all single-ended inputs and outputs, and can be used for emulated differential output buffer. Some of these user-programmable I/O are used during configuration, depending on the configuration mode. You need to make appropriate connection on the board to isolate the 2 different functions before/after configuration. Some of these user-programmable I/O are shared with special function pins. These pins, when not used as special purpose pins, can be programmed as I/O for user logic. During configuration the user-programmable I/O are tri-stated with an internal weak pull-down resistor enabled. If any pin is not used (or not bonded to a package pin), it is tri-stated and default to have weak pull- down enabled after configuration. Shared Configuration Pins1, 2 1. These pins can be used for configuration during configuration mode. When configuration is completed, these pins can be used as GPIO, or shared function in GPIO. When these pins are used in dual function, you need to isolate the signal paths for the dual functions on the board. 2. The pins used are defined by the configuration modes detected. Slave SPI or I2C/I3C modes are detected during slave activation. Pins that are not used in the configuration mode selected are tri-stated during configuration, and can connect directly as GPIO in user’s function. PRxxx /SDA/USER_SDA 1 Input, Output, Bi-Dir Configuration: I2C/I3C Mode: SDA signal User Mode: PRxxx: GPIO User_SDA: SDA signal for I2C/I3C interface PRxxx /SCL/USER_SCL 1 Input, Output, Bi-Dir Configuration: I2C/I3C Mode: SCL signal User Mode: PRxxx: GPIO User_SDA: SCL signal for I2C/I3C interface PRxxx/TDO/SSO 1 Input, Output, Bi-Dir Configuration: Slave SPI Mode: Slave Serial Output User Mode: PRxxx: GPIO TDO: When JTAG_EN = 1, used as TDO signal for JTAG PRxxx/TDI/SSI 1 Input, Output, Bi-Dir Configuration: Slave SPI Mode: Slave Serial Input User Mode: PRxxx: GPIO TDI: When JTAG_EN = 1, used as TDI signal for JTAG
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 90 FPGA-DS-02102-0.80 Signal Name Bank Type Description PRxxx/TMS/SCSN 1 Input, Output, Bi-Dir Configuration: Slave SPI Mode: Slave Chip Select User Mode: PRxxx: GPIO TMS: When JTAG_EN = 1, used as TMS signal for JTAG PRxxx/TCK/SCLK 1 Input, Output, Bi-Dir Configuration: Slave SPI Mode: Slave Clock Input User Mode: PRxxx: GPIO TCK: When JTAG_EN = 1, used as TCK signal for JTAG PTxxx/MCSNO 0 Input, Output, Bi-Dir Configuration: Flow-through Daisy Chain Mode: Chip Select Output User Mode: PTxxx: GPIO PTxxx/PROGRAMN 0 Input, Output, Bi-Dir Configuration: PROGRAMN: Initiate configuration sequence when asserted LOW. User Mode: PTxxx: GPIO PTxxx/INITN 0 Input, Output, Bi-Dir Configuration: INITN: Open Drain I/O pin. This signal is driven to LOW when configuration sequence is started, to indicate the device is in initialization state. This signal is released after initialization is completed, and the configuration download can start. You can keep drive this signal LOW to delay configuration download to start. User Mode: PTxxx: GPIO PTxxx/DONE 0 Input, Output, Bi-Dir Configuration: DONE: Open Drain I/O pin. This signal is driven to LOW during configuration time. It is released to indicate the device has completed configuration. You can keep drive this signal LOW to delay the device to wake up from configuration. User Mode: PTxxx: GPIO Shared User GPIO Pins1, 2, 3, 4 1. Shared User GPIO pins are pins that can be used as GPIO, or functional pins that connect directly to specific functional blocks, when device enters into User Mode. 2. Declaring on assigning the pin as GPIO or specific functional pin is done by configuration bitstream, except JTAG pins. 3. JTAG pins are controlled by JTAG_EN signal. When JTAG_EN = 1, the pins are used for JTAG interface. When JTAG = 0, the pins are used as GPIO or specific functional pin defined by configuration bitstream. 4. Refer to package pin file. Shared JTAG Pins PRxxx/TDO/ yyyy 1 Input, Output, Bi-Dir User Mode: PRxxx: GPIO TDO: When JTAG_EN = 1, used as TDO signal for JTAG yyyy: Other possible selectable specific functional PRxxx/TDI/yyyy 1 Input, Output, Bi-Dir User Mode: PRxxx: GPIO TDI: When JTAG_EN = 1, used as TDI signal for JTAG yyyy: Other possible selectable specific functional
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 91 Signal Name Bank Type Description PRxxx/TMS/ yyyy 1 Input, Output, Bi-Dir User Mode: PRxxx: GPIO TMS: When JTAG_EN = 1, used as TMS signal for JTAG yyyy: Other possible selectable specific functional PRxxx/TCK/ yyyy 1 Input, Output, Bi-Dir User Mode: PRxxx: GPIO TCK: When JTAG_EN = 1, used as TCK signal for JTAG Yyyy: Other possible selectable specific functional Shared CLOCK Pins 1 1. Some PCLK pins can also be used as GPLL reference clock input pin. Refer to sysCLOCK PLL/DLL Design and Usage Guide for Nexus Platform (FPGA-TN-02095). PBxxx/PCLK[T,C][5,6]_[0- 3]/yyyy 5,6 Input, Output, Bi-Dir User Mode: PBxxx: GPIO PCLK: Primary Clock or GPLL Refclk signal [T,C] = True/Complement when using differential signaling [5,6] = Bank [0-3] Up to 4 signals in the bank yyyy: Other possible selectable specific functional PTxxx/PCLKT[0,1]_[0-1]/yyyy 0, 1 Input, Output, Bi-Dir User Mode: PTxxx: GPIO PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended) [0-1] Up to 2 signals in the bank yyyy: Other possible selectable specific functional PRxxx/PCLKT[2,3,4]_[0- 2]/yyyy 2, 3, 4 Input, Output, Bi-Dir User Mode: PRxxx: GPIO PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended) [0-2] Up to 3 signals in the bank yyyy: Other possible selectable specific functional PLxxx/PCLKT[7,8,9]_[0- 2]/yyyy 7, 8, 9 Input, Output, Bi-Dir User Mode: PLxxx: GPIO PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended) [0-2] Up to 3 signals in the bank yyyy: Other possible selectable specific functional PBxxx/LRC_GPLL[T,C]_IN/yyyy 5 Input, Output, Bi-Dir User Mode: PBxxx: GPIO LRC_GPLL: Lower Right GPLL Refclk signal (PLLCK) [T,C] = True/Complement when using differential signaling yyyy: Other possible selectable specific functional PLxxx/ULC_GPLLT_IN/yyyy 9 Input, Output, Bi-Dir User Mode: PLxxx: GPIO ULC_GPLL: Upper Left GPLL Refclk signal (Only Single Ended) (PLLCK) yyyy: Other possible selectable specific functional Shared VREF Pins PBxxx/VREF[5,6]_[1-2]/yyyy 5, 6 Input, Output, Bi-Dir User Mode: PBxxx: GPIO VREF: Reference Voltage for DDR memory function [5,6] = Bank [1-2] Up to VREFs for each bank yyyy: Other possible selectable specific functional Shared ADC Pins
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 92 FPGA-DS-02102-0.80 Signal Name Bank Type Description PBxxx/ADC_C[P,N]nn/yyyy 5, 6 Input, Output, Bi-Dir User Mode: PBxxx: GPIO ADC_C: ADC Channel Inputs [P,N] = Positive or Negative Input nn = ADC Channel number (0 – 15) yyyy: Other possible selectable specific functional Shared Comparator Pins PBxxx/COMP[1-3][P,N]/yyyy 5, 6 Input, Output, Bi-Dir User Mode: PBxxx: GPIO COMP: Differential Comparator Input [P,N] = Positive or Negative Input [1-3] = Input to Comparators 1-3 yyyy: Other possible selectable specific functional Shared SGMII Pins PBxxx/SGMII_RX[P,N][0- 1]/yyyy
6 Input,
Output, Bi-Dir User Mode: PBxxx: GPIO SGMII_RX: Differential SGMII RX Inputs [P,N] = Positive or Negative Input [0-1] = Input to SGMII RX0 or RX1 yyyy: Other possible selectable specific functional Note: Not all signals are available as external pins in all packages. Refer to the Pinout List file for various package details.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 93 4.2. Pin Information Summary 4.2.1. MachXO5-NX Family Pin Information Summary LFMXO5-25
256 BBG 400 BBG
General Purpose Inputs/Outputs per Bank Bank 0 24 40 Bank 1 26 36 Bank 2 23 31 Bank 3 16 32 Bank 4 12 24 Bank 5 20 24 Bank 6 20 24 Bank 7 12 24 Bank 8 16 32 Bank 9 24 32 Total Single-Ended User I/O 193 299 Differential Input/ Output Pairs Bank 0 12 20 Bank 1 13 18 Bank 2 11 15 Bank 3 8 16 Bank 4 6 12 Bank 5 10 12 Bank 6 10 12 Bank 7 6 12 Bank 8 8 16 Bank 9 12 16 Power Pins VCC, VCCECLK 4 6 VCCAUXA 2 2 VCCAUX 2 3 VCCAUXHx 2 2 VCCIO Bank 0 2 — Bank 1 2 — Bank 2 2 — Bank 3 1 — Bank 4 1 — Bank 5 2 — Bank 6 2 — Bank 7 1 — Bank 8 1 — Bank 9 2 — VCCADC18 1 1 Total Power Pins 27 36 GND Pins Vss 22 30 VSSADC 1 1 Total GND Pins 23 31 Dedicated Pins Dedicated ADC Channels (pairs) 2 2 Dedicated ADC Reference Voltage Pins 2 2 Dedicated Misc Pins JTAGEN 1 1
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 94 FPGA-DS-02102-0.80 Pin Information Summary LFMXO5-25 Total Dedicated Pins 13 34 Shared Pins Shared Configuration Pins Bank 0 0 0 Bank 1 4 4 Bank 2 6 6 Bank 3 0 0 Bank 4 0 0 Bank 5 0 0 Bank 6 0 0 Bank 7 0 0 Bank 8 0 0 Bank 9 0 0 Shared JTAG Pins Bank 0 0 0 Bank 1 0 0 Bank 2 4 4 Bank 3 0 0 Bank 4 0 0 Bank 5 0 0 Bank 6 0 0 Bank 7 0 0 Bank 8 0 0 Bank 9 0 0 Shared PCLK Pins Bank 0 2 2 Bank 1 2 2 Bank 2 3 3 Bank 3 2 2 Bank 4 2 2 Bank 5 8 8 Bank 6 8 8 Bank 7 2 2 Bank 8 2 2 Bank 9 0 3 Shared GPLL Pins Bank 0 0 0 Bank 1 0 0 Bank 2 0 0 Bank 3 0 0 Bank 4 0 0 Bank 5 2 2 Bank 6 0 0 Bank 7 0 0 Bank 8 0 0 Bank 9 1 1 Shared VREF Pins Bank 0 0 0 Bank 1 0 0 Bank 2 0 0 Bank 3 0 0 Bank 4 0 0 Bank 5 2 2 Bank 6 2 2 Bank 7 0 0
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 95 Pin Information Summary LFMXO5-25 Shared ADC Channels (pairs) Bank 0 0 0 Bank 1 0 0 Bank 2 0 0 Bank 3 0 0 Bank 4 0 0 Bank 5 5 7 Bank 6 8 9 Bank 7 0 0 Bank 8 0 0 Bank 9 0 0 Shared Comparator Channels (pairs) Bank 0 0 0 Bank 1 0 0 Bank 2 0 0 Bank 3 0 0 Bank 4 0 0 Bank 5 3 3 Bank 6 3 3 Bank 7 0 0 Bank 8 0 0 Bank 9 0 0 Shared SGMII Channels (pairs) Bank 0 0 0 Bank 1 0 0 Bank 2 0 0 Bank 3 0 0 Bank 4 0 0 Bank 5 0 0 Bank 6 2 2 Bank 7 0 0 Bank 8 0 0 Bank 9 0 0
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 96 FPGA-DS-02102-0.80 5. Ordering Information Lattice provides a wide variety of services for its products including custom marking, factory programming, known good die, and application specific testing. Contact your local sales representatives for more details. 5.1. MachXO5-NX Part Number Description Logic Capacity 25 = 25k Logic Cells Package BBG256 = 256-pin caBGA BBG400 = 400-pin caBGA LFMXO5 Grade C = Commercial I = Industrial - 25 - X XXXX X Speed (same number for HP and LP)* 7 = Slowest 9 = Fastest Device Family MachXO5-NX FPGA *Note: Input Comparator, ADC, EBR ECC, and DTR are only available in -8 (-C/I) and -9 (-C/I) speed and grade.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 97 5.2. Ordering Part Numbers MachXO5-NX devices have either of the top-side markings as shown in the examples below. LFMXO5-25 8BBG400C MachXO5 - NX Barcode Lot ID COO MachXO5 - NX Barcode Lot ID COO Figure 5.1. Top Marking Diagram 5.2.1. Commercial Part Number Speed Package Pins Temp. Logic Cells (k) LFMXO5-25-7BBG256C –7 Lead free caBGA 256 Commercial 25 LFMXO5-25-8BBG256C –8 Lead free caBGA 256 Commercial 25 LFMXO5-25-9BBG256C –9 Lead free caBGA 256 Commercial 25 LFMXO5-25-7BBG400C –7 Lead free caBGA 400 Commercial 25 LFMXO5-25-8BBG400C –8 Lead free caBGA 400 Commercial 25 LFMXO5-25-9BBG400C –9 Lead free caBGA 400 Commercial 25 5.2.2. Industrial Part Number Speed Package Pins Temp. Logic Cells (k) LFMXO5-25-7BBG256I –7 Lead free caBGA 256 Industrial 25 LFMXO5-25-8BBG256I –8 Lead free caBGA 256 Industrial 25 LFMXO5-25-9BBG256I –9 Lead free caBGA 256 Industrial 25 LFMXO5-25-7BBG400I –7 Lead free caBGA 400 Industrial 25 LFMXO5-25-8BBG400I –8 Lead free caBGA 400 Industrial 25 LFMXO5-25-9BBG400I –9 Lead free caBGA 400 Industrial 25
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 98 FPGA-DS-02102-0.80 Supplemental Information For Further Information A variety of technical notes for the MachXO5-NX family are available. sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02028) Thermal Management (FPGA-TN-02044) sysI/O Usage Guide for Nexus Platform (FPGA-TN-02067) Power Management and Calculation for Certus-NX, CertusPro-NX and MachXO5-NX Devices (FPGA-TN-02257) Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform (FPGA -TN-02076) Using TraceID (FPGA-TN-02084) Memory Usage Guide for Nexus Platform (FPGA-TN-02094) sysCLOCK PLL Design and Usage Guide for Nexus Platform (FPGA-TN-02095) sysDSP Usage Guide for Nexus Platform (FPGA-TN-02096) MachXO5-NX High-Speed I/O Interface (FPGA-TN-02286) MachXO5-NX Programming and Configuration UG (FPGA-TN-02271) ADC Usage Guides for Nexus Platform (FPGA-TN-02129) I2C Hardened IP Usage Guide for Nexus Platform (FPGA-TN-02142) Multi-Boot Usage Guide for Nexus Platform (FPGA-TN-02145) MachXO5-NX Hardware Checklist (FPGA-TN-02274) Single Event Upset (SEU) Report for Nexus Platform (FPGA-TN-02174) Lattice Memory Mapped Interface and Lattice Interrupt Interface User Guide (FPGA -UG-02039) For further information on interface standards refer to the following websites: JEDEC Standards (LVTTL, LVCMOS, SSTL) – www.jedec.org
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 99
Revision History
Revision 0.80, May 2022 Section Change Summary All Globally changed Control Jedi-D6 to MachXO5-NX. General Description Newly changed to Dual ADC – 1 MSPS, 12-bit SAR with Simultaneous Sampling. Newly added note. Updated UFM value in Table 1.1. MachXO5-NX Commercial/Industrial Family Selection Guide. Architecture In the sysMEM Memory section: Changed to EBR also provides a build in ECC engine in select speed grades. Updated Figure 2.25. DQS Control and Delay Block (DQSBUF). Globally updated Table 2.9. DQSBUF Port List Description. In the Analog Interface section: Changed to In select speed grades, the MachXO5-NX family provides an analog interface…. In the Device Configuration section: Changed the Master SPI booting sequence to self download mode. Changed to In self download mode, the FPGA boots from an external SPI boots from on-chip flash. In the User Flash Memory (UFM) section: Updated the non-volatile storage data to 15,360 kb. Updated all the values in Table 2.14. MachXO5-NX UFM Size. In the Pin Migration section: Changed the section title from Density Shifting to Pin Migration. DC and Switching Characteristics for Commercial and Industrial Removed Bank 10 and Bank 11 from Table 3.1. Absolute Maximum Ratings and Table 3.2. Recommended Operating Conditions. Updated Note 1 contents of Table 3.5. On-Chip Termination Options for Input Modes. General update to Table 3.6. Hot Socketing Specifications for GPIO. – Wide Range (Over Recommended Operating Conditions) and Table 3.8. DC Electrical Characteristics – High Speed (Over Recommended Operating Conditions). Updated Note format in Table 3.9. Capacitors – Wide Range (Over Recommended Operating Conditions) and Table 3.10. Capacitors – High Performance (Over Recommended Operating Conditions). General update to Table 3.13. sysI/O Recommended Operating Conditions, Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O (Over Recommended Operating Conditions), and Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O (Over Recommended Operating Conditions)3. In the sysI/O Differential DC Electrical Characteristics section: General update to the LVDS, SubLVDSE/SubLVDSEH (Output Only) sections; General update to Table 3.17. LVDS DC Electrical Characteristics (Over Recommended Operating Conditions)1, Table 3.18. LVDS25E DC Conditions, Table 3.19. SubLVDS Input DC Electrical Characteristics (Over Recommended Operating Conditions), Table 3.20. SubLVDS Output DC Electrical Characteristics (Over Recommended Operating Conditions), Table 3.21. SLVS Input DC Characteristics (Over Recommended Operating Conditions), Table 3.22. SLVS Output DC Characteristics (Over Recommended Operating Conditions), Table 3.23. Soft D-PHY Input Timing and Levels,
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 100 FPGA-DS-02102-0.80 Section Change Summary Table 3.24. Soft D-PHY Output Timing and Levels, Table 3.25. Soft D-PHY Clock Signal Specification, Table 3.26. Soft D-PHY Data-Clock Timing Specifications, Table 3.26. Soft D-PHY Data-Clock Timing Specifications, Table 3.27. MachXO5-NX Maximum I/O Buffer Speed1, 2, 3, 4, 7, Table 3.28. Pin-to-Pin Performance, Table 3.36. ADC Specifications1, Table 3.37. Comparator Specifications, Table 3.38. DTR Specifications1,2, Table 3.39. SGMII Rx, Table 3.40. MachXO5-NX sysCONFIG Port Timing Specifications, Removed the original Figure 3.14. Master SPI PRO/REFRESH Timing, Figure 3.16. Master SPI PROGRAMN Timing, Figure 3.20. Master SPI Wake-Up Timing, Pinout Information Updated the Bank and description for VCCAUX and VCCIOx in In the Signal Descriptions section
Ordering Information
Newly added note to the MachXO5-NX Part Number Description section. Updated the top marking diagram in the Ordering Part Numbers section. Supplemental Information Updated document list. Revision 0.72, December 2021 Section Change Summary General Description Removed 52k logic cells support and related contents. In the Features section: changed the programmable sysI/O (High Performance and Wide Range I/O) range to “200 to 300”; changed the small footprint package option to “14 mm × 14 mm to 17 mm × 17 mm”; changed to “up to 1.4 Mb sysMEM Embedded Block RAM (EBR)” in Flexible memory resources; changed to “80 kbit distributed RAM” in Flexible memory resources. Architecture Removed the original Figure 2.2 Simplified Block Diagram, Control Jedi-D6-55 Device (Top Level) from the Overview section. Pinout Information Removed all LFMXO5-55 information from the Pin Information Summary section. Removed 55k logic cells capacity from the MachXO5-NX Part Number Description section. Removed 484 package from the MachXO5-NX Part Number Description section. Revision 0.71, October 2021 Section Change Summary General Description Changed Configuration to Non-volatile Configuration in the Features section. Architecture Added description regarding DSP blocks and sysMEM EBR blocks for Jedi-D6 25 device to the Overview section. Updated Figure 2.1. Simplified Block Diagram, MachXO5-25 Device (Top Level) to show non-volatile configuration and security, and on-chip user flash. Updated description regarding image configuration in the User Flash Memory (UFM) section. Pinout Information Added “if not used, tie to ground” to the description for Dedicated ADC I/O Pins, both ADC_REF and ADC_DP/N, in the Signal Descriptions section. DC and Switching Characteristics for Commercial and Industrial Removed the hyperlink of the D6-Control Product Family Qualification Summary in the ESD Performance section.
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-0.80 101 Revision 0.70, October 2021 Section Change Summary All Initial Advance release
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