LC4128ZE5MN64C

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Technical content

Features

= 260MHz maximum operating frequency PD = 4.4ns propagation delay

• Up to four global clock pins with programmable clock polarity control
• Up to 80 PTs per output Ease of Design
• Flexible CPLD macrocells with individual clock, reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-Fit TM and refit
• Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders Ultra Low Power
• Standby current as low as 10µA typical
• 1.8V core; low dynamic power
• Operational down to 1.6V V CC
• Superior solution for power sensitive consumer

applications

• Per pin pull-up, pull-down or bus keeper control Power Guard with multiple enable signals* Broad Device Offering
• 32 to 256 macrocells
• Multiple temperature range support – Commercial: 0 to 90°C junction (T j – Industrial: -40 to 105°C junction (T j
• Space-saving packages Easy System Integration
• Operation with 3.3V, 2.5V, 1.8V or 1.5V LVCMOS I/O
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
• Hot-socketing support
• Open-drain output option
• Programmable output slew rate
• 3.3V PCI compatible
• I/O pins with fast setup path Input hysteresis*
• 1.8V core power supply
• IEEE 1149.1 boundary scan testable
• IEEE 1532 ISC compliant
• 1.8V In-System Programmable (ISP™) using Boundary Scan Test Access Port (TAP)
• Pb-free package options (only) On-chip user oscillator and timer* *New enhanced features over original ispMACH 4000Z

Table 1. ispMACH 4000ZE Family Selection Guide

tion by preventing internal logic toggling due to unnecessary I/O pin activity. ity, routing, pin-out retention and density migration. balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters. scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power. which contain multiple I/O cells. This architecture is shown in Figure 1. Figure 1. Functional Block Diagram

of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces. ciated I/O cells in the I/O block. pled from macrocells through the ORP . Figure 2 illustrates the GLB. Figure 2. Generic Logic Block Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.

36 Inputs

16 Macrocells

16 MC Feedback Signals

36 Inputs,

83 Product Terms

with the cluster. Table 2 shows the available functions for each of the five product terms in the cluster. Table 2. Individual PT Steering accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created. Table 3. Available Clusters for Each Macrocell

• Block CLK2
• Block CLK3
• PT Clock
• PT Clock Inverted
• Shared PT Clock
• Ground Clock Enable Multiplexer Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol- lowing four sources:
• PT Initialization/CE
• PT Initialization/CE Inverted
• Shared PT Clock
• Logic High Initialization Control The ispMACH 4000ZE family architecture accommodates both block-level and macrocell-level set and reset capa- bility. There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macro- cell level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, pro- viding flexibility. Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on power- up. To guarantee initialization values, the V CC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed. GLB Clock Generator Each ispMACH 4000ZE device has up to four clock pins that are also routed to the GRP to be used as inputs. These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock sig- nals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations of the true and complement edges of the global clock signals.

Figure 6. GLB Clock Generator

Table 6. GLB/MC/ORP Combinations for ispMACH 4128ZE Table 7. GLB/MC/ORP Combinations for ispMACH 4032ZE and 4064ZE The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell. and bus maintenance circuitry. Figure 8 details the I/O cell.

Figure 8. I/O Cell

• LVTTL • LVCMOS 1.8
• LVCMOS 3.3 • LVCMOS 1.5
• LVCMOS 2.5 • 3.3V PCI Compatible All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, pull-up resistor or pull-down resistor selectable on a “per-pin” basis. A fourth option is to provide none of these. The default in both hardware and software is such that when the device is erased or if the user does not specify, the input structure is configured to be a Pull-down Resistor. Each ispMACH 4000ZE device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The ispMACH 4000ZE family has an always on, 200mV typical hysteresis for each input operational at 3.3V and 2.5V. This provides improved noise immunity for slow transitioning signals. Power Guard Power Guard allows easier achievement of standby current in the system. As shown in Figure 9, this feature con- sists of an enabling multiplexer between an I/O pin and input buffer, and its associated circuitry inside the device. If the enable signal (E) is held low, all inputs (D) can be optionally isolated (guarded), such that, if any of these were toggled, it would not cause any toggle on internal pins (Q), thus, a toggling I/O pin will not cause any internal dynamic power consumption. To Macrocell To GRP VCCO GOE 0 GOE 1 GOE 2 GOE 3 VCC From ORP From ORP Block Input Enable (BIE) (From Block PT) Power Guard Disable Fuse (PGDF) Power Guard I/O Bus Maintenance VCCO

available in each block is shown in the Ordering Information section of this data sheet. Table 8. Number of BIE Signals Available in ispMACH 4000ZE DevicesPower Guard for Dedicated Inputs the BIE of the logic blocks shown in Tables 9 and 10. Table 10. Dedicated Inputs to BIE Association For more information on the Power Guard function refer to TN1174, Advanced Features of the ispMACH 4000ZE. (GOE) PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be inverted. show a graphical representation of the global OE generation. cell device (with 16 blocks), each block's BIE signal is driven by block-level OE PT from each block. Table 9. Dedicated Clock Inputs to BIE Association

drive the optional OSCTIMER inputs TIMERRES and DYNOSCDIS. Figure 15. OSCTIMER Integration With CPLD Fabric Table 12 shows how these two MCs are designated in each of the ispMACH4000ZE device. (A) A simple 5MHz oscillator. (B) An oscillator with dynamic disable. (D) Oscillator with two outputs (5MHz and 5KHz).(C) A simple 5Hz oscillator.

Table 12. OSC and TIMER MC Designation changes, the ispMACH 4000ZE family is able to achieve the industry’s lowest static power. LVCMOS interface that corresponds to the power supply voltage. can generate the ATE or test vectors necessary for a third-party test system. defined interface. All ispMACH 4000ZE devices are also compliant with the IEEE 1532 standard.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet mated test equipment. This equipment can then be used to program ispMACH 4000ZE devices during the testing of a circuit board. User Electronic Signature The User Electronic Signature (UES) allows the designer to include identification bits or serial numbers inside the device, stored in E 2CMOS memory. The ispMACH 4000ZE device contains 32 UES bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control codes. Security Bit A programmable security bit is provided on the ispMACH 4000ZE devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device. Hot Socketing The ispMACH 4000ZE devices are well-suited for applications that require hot socketing capability. Hot socketing a device requires that the device, during power-up and down, can tolerate active signals on the I/Os and inputs with- out being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The ispMACH 4000ZE devices provide this capability for input voltages in the range 0V to 3.0V. Density Migration The ispMACH 4000ZE family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar- geted for a high density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet Absolute Maximum Ratings1, 2, 3 Junction Temperature (T j) with Power Applied . . .-55 to 150°C 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Undershoot of -2V and overshoot of (V IH (MAX) + 2V), up to a total pin voltage of 6V is permitted for a duration of <20ns. 5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed. Recommended Operating Conditions Erase Reprogram Specifications Hot Socketing Characteristics1,2,3 Symbol Parameter Min. Max. Units VCC Supply Voltage Standard Voltage Operation 1.7 1.9 V Extended Voltage Operation 1.6 1 1.9 V Tj Junction Temperature (Commercial) 0 90 °C Junction Temperature (Industrial) -40 105 °C 1. Devices operating at 1.6V can expect performance degradation up to 35%. Parameter Min. Max. Units Erase/Reprogram Cycle 1,000 — Cycles Note: Valid over commercial temperature range. Symbol Parameter Condition Min. Typ. Max. Units IDK Input or I/O Leakage Current 0 ≤ VIN ≤ 3.0V, Tj = 105°C — ±30 ±150 µA 0 ≤ VIN ≤ 3.0V, Tj = 130°C — ±30 ±200 µA 1. Insensitive to sequence of V CC or VCCO. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO) ≤ 3.6V. 2. 0 < V CC < VCC (MAX), 0 < VCCO < VCCO (MAX). 3. I DK is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet I/O Recommended Operating Conditions Over Recommended Operating Conditions Standard VCCO (V)1 Min. Max. LVTTL 3.0 3.6 LVCMOS 3.3 3.0 3.6 Extended LVCMOS 3.3 2.7 3.6 LVCMOS 2.5 2.3 2.7 LVCMOS 1.8 1.65 1.95 LVCMOS 1.5 1.4 1.6 PCI 3.3 3.0 3.6 1. Typical values for VCCO are the average of the min. and max. values. Symbol Parameter Condition Min. Typ. Max. Units IIL, IIH 1, 2 Input Leakage Current 0 ≤ VIN < VCCO — 0.5 1 µA IIH 1 Input High Leakage Current V CCO < VIN ≤ 5.5V — — 10 µA IPU I/O Weak Pull-up Resistor Current 0 ≤ VIN ≤ 0.7VCCO -20 — -150 µA IPD I/O Weak Pull-down Resistor Current V IL (MAX) ≤ VIN ≤ VIH (MAX) 30 — 150 µA IBHLS Bus Hold Low Sustaining Current V IN = VIL (MAX) 30 — — µA IBHHS Bus Hold High Sustaining Current V IN = 0.7 VCCO -20 — — µA IBHLO Bus Hold Low Overdrive Current 0V ≤ VIN ≤ VBHT — — 150 µA IBHHO Bus Hold High Overdrive Current V BHT ≤ VIN ≤ VCCO — — -150 µA VBHT Bus Hold Trip Points — V CCO * 0.35 — V CCO * 0.65 V 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. I t is not measured with the output driver active. Bus maintenance circuits are disabled. 2. I IH excursions of up to 1.5µA maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of the device’s I/O pins. 3. Measured TA = 25°C, f = 1.0MHz.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet Supply Current Symbol Parameter Condition Min. Typ. Max. Units ispMACH 4032ZE ICC1, 2, 3, 5, 6 Operating Power Supply Current Vcc = 1.8V, TA = 25°C — 50 — µA Vcc = 1.9V, TA = 0 to 70°C — 58 — µA Vcc = 1.9V, TA = -40 to 85°C — 60 — µA ICC4, 5, 6 Standby Power Supply Current Vcc = 1.8V, TA = 25°C — 10 — µA Vcc = 1.9V, TA = 0 to 70°C — 13 25 µA Vcc = 1.9V, TA = -40 to 85°C — 15 40 µA ispMACH 4064ZE ICC1, 2, 3, 5, 6 Operating Power Supply Current Vcc = 1.8V, TA = 25°C — 80 — µA Vcc = 1.9V, TA = 0 to 70°C — 89 — µA Vcc = 1.9V, TA = -40 to 85°C — 92 — µA ICC4, 5, 6 Standby Power Supply Current Vcc = 1.8V, TA = 25°C — 11 — µA Vcc = 1.9V, TA = 0 to 70°C — 15 30 µA Vcc = 1.9V, TA = -40 to 85°C — 18 50 µA ispMACH 4128ZE ICC1, 2, 3, 5, 6 Operating Power Supply Current Vcc = 1.8V, TA = 25°C — 168 — µA Vcc = 1.9V, TA = 0 to 70°C — 190 — µA Vcc = 1.9V, TA = -40 to 85°C — 195 — µA ICC4, 5, 6 Standby Power Supply Current Vcc = 1.8V, TA = 25°C — 12 — µA Vcc = 1.9V, TA = 0 to 70°C — 16 40 µA Vcc = 1.9V, TA = -40 to 85°C — 19 60 µA ispMACH 4256ZE ICC1, 2, 3, 5, 6 Operating Power Supply Current Vcc = 1.8V, TA = 25°C — 341 — µA Vcc = 1.9V, TA = 0 to 70°C — 361 — µA Vcc = 1.9V, TA = -40 to 85°C — 372 — µA ICC4, 5, 6 Standby Power Supply Current Vcc = 1.8V, TA = 25°C — 13 — µA Vcc = 1.9V, TA = 0 to 70°C — 32 65 µA Vcc = 1.9V, TA = -40 to 85°C — 43 100 µA 1. Frequency = 1.0 MHz. 2. Device configured with 16-bit counters. 3. I CC varies with specific device configuration and operating frequency. 4. V CCO = 3.6V, VIN = 0V or VCCO, bus maintenance turned off. VIN above VCCO will add transient current above the specified standby ICC. 5. Includes V CCO current without output loading. 6. This operating supply current is with the internal oscillator disabled. Enabling the internal oscillator adds approximately 15µA typical current plus additional current from any logic it drives.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet I/O DC Electrical Characteristics Over Recommended Operating Conditions Standard VIL VIH VOL Max (V) VOH Min (V) IOL (mA) IOH (mA)Min (V) Max (V) Min (V) Max (V) 0.20 V CCO - 0.20 0.1 -0.1 0.20 V CCO - 0.20 0.1 -0.1 0.20 V CCO - 0.20 0.1 -0.1 0.20 V CCO - 0.20 0.1 -0.1 0.20 V CCO - 0.20 0.1 -0.1 1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. 2. For 1.5V inputs, there may be an additional DC current drawn from VCC, if the ispMACH 4000ZE VCC and the VCC of the driving device (VCCd-d; that determines steady state VIH) are in the extreme range of their specifications. Typically, DC current drawn from VCC will be 2µA per input. VO Output Voltage (V) 2.01.51.00.5 Typical I/O Output Current (mA) 1.8V VCCO IOH IOL

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet ispMACH 4000ZE External Switching Characteristics Over Recommended Operating Conditions Parameter Description 1, 2 LC4032ZE LC4064ZE All Devices Units -4 -4 -5 -7 tPD 20-PT combinatorial propagation delay — 4.4 — 4.7 — 5.8 — 7.5 ns tS GLB register setup time before clock 2.2 — 2.5 — 2.9 — 4.5 — ns tST GLB register setup time before clock with T -type register 2.4 — 2.7 — 3.1 — 4.7 — ns tSIR GLB register setup time before clock, input register path 1.0 — 1.1 — 1.3 — 1.4 — ns tSIRZ GLB register setup time before clock with zero tH GLB register hold time after clock 0.0 — 0.0 — 0.0 — 0.0 — ns tHT GLB register hold time after clock with T -type register 0.0 — 0.0 — 0.0 — 0.0 — ns tHIR GLB register hold time after clock, input register path 1.0 — 1.0 — 1.3 — 1.3 — ns tHIRZ GLB register hold time after clock, input register path with zero hold 0.0 — 0.0 — 0.0 — 0.0 — ns tCO GLB register clock-to-output delay — 3.0 — 3.2 — 3.8 — 4.5 ns tR External reset pin to output delay — 5.0 — 6.0 — 7.5 — 9.0 ns tRW External reset pulse duration 1.5 — 1.7 — 2.0 — 4.0 — ns tPTOE/DIS Input to output local product term output enable/disable — 7.0 — 8.0 — 8.2 — 9.0 ns tGPTOE/DIS Input to output global product term output enable/disable — 6.5 — 7.0 — 10.0 — 10.5 ns tGOE/DIS Global OE input to output enable/disable — 4.5 — 4.5 — 5.5 — 7.0 ns tCW Global clock width, high or low 1.0 — 1.5 — 1.8 — 3.3 — ns tGW Global gate width low (for low transparent) or high (for high transparent) 1.0 — 1.5 — 1.8 — 3.3 — ns tWIR Input register clock width, high or low 1.0 — 1.5 — 1.8 — 3.3 — ns fMAX (Int.)3 Clock frequency with internal feedback 260 — 241 — 200 — 172 — MHz fMAX (Ext.) clock frequency with external feedback, [1 / (tS + tCO)] 192 — 175 — 149 — 111 — MHz 1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. 2. Measured using standard switching GRP loading of 1 and 1 output switching. 3. Standard 16-bit counter using GRP feedback. Timing v.0.8

and usage, please refer to technical note TN1168, ispMACH 4000ZE Timing Model Design and Usage Guidelines. Figure 16. ispMACH 4000ZE Timing Model Note: Italicized items are optional delay adders.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet ispMACH 4000ZE Internal Timing Parameters Over Recommended Operating Conditions Parameter Description LC4032ZE LC4064ZE Units -4 -4 Min. Max. Min. Max. In/Out Delays t IN Input Buffer Delay — 0.85 — 0.90 ns tGCLK_IN Global Clock Input Buffer Delay — 1.60 — 1.60 ns tGOE Global OE Pin Delay — 2.25 — 2.25 ns tBUF Delay through Output Buffer — 0.75 — 0.90 ns tEN Output Enable Time — 2.25 — 2.25 ns tDIS Output Disable Time — 1.35 — 1.35 ns tPGSU Input Power Guard Setup Time — 3.30 — 3.55 ns tPGH Input Power Guard Hold Time — 0.00 — 0.00 ns tPGPW Input Power Guard BIE Minimum Pulse Width — 5.00 — 5.00 ns tPGRT Input Power Guard Recovery Time Following BIE Dissertation — 5.00 — 5.00 ns Routing Delays tROUTE Delay through GRP — 1.60 — 1.70 ns tPDi Macrocell Propagation Delay — 0.25 — 0.25 ns tMCELL Macrocell Delay — 0.65 — 0.65 ns tINREG Input Buffer to Macrocell Register Delay — 0.90 — 1.00 ns tFBK Internal Feedback Delay — 0.55 — 0.55 ns tORP Output Routing Pool Delay — 0.30 — 0.30 ns Register/Latch Delays tS D-Register Setup Time (Global Clock) 0.70 — 0.85 — ns tS_PT D-Register Setup Time (Product Term Clock) 1.25 — 1.85 — ns tH D-Register Hold Time 1.50 — 1.65 — ns tST T -Register Setup Time (Global Clock) 0.90 — 1.05 — ns tST_PT T -register Setup Time (Product Term Clock) 1.45 — 1.65 — ns tHT T -Resister Hold Time 1.50 — 1.65 — ns tSIR D-Input Register Setup Time (Global Clock) 0.85 — 0.80 — ns tSIR_PT D-Input Register Setup Time (Product Term Clock) 1.45 — 1.45 — ns tHIR D-Input Register Hold Time (Global Clock) 1.15 — 1.30 — ns tHIR_PT D-Input Register Hold Time (Product Term Clock) 0.90 — 1.10 — ns tCOi Register Clock to Output/Feedback MUX Time — 0.35 — 0.40 ns tCES Clock Enable Setup Time 1.00 — 2.00 — ns tCEH Clock Enable Hold Time 0.00 — 0.00 — ns tSL Latch Setup Time (Global Clock) 0.70 — 0.95 — ns tSL_PT Latch Setup Time (Product Term Clock) 1.45 — 1.85 — ns tHL Latch Hold Time 1.40 — 1.80 — ns tGOi Latch Gate to Output/Feedback MUX Time — 0.40 — 0.35 ns tPDLi Propagation Delay through Transparent Latch to Output/ Feedback MUX — 0.30 — 0.25 ns tSRi Asynchronous Reset or Set to Output/Feedback MUX Delay — 0.30 — 0.30 ns

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet tSRR Asynchronous Reset or Set Recovery Delay — 2.00 — 1.70 ns Control Delays t BCLK GLB PT Clock Delay — 1.20 — 1.30 ns tPTCLK Macrocell PT Clock Delay — 1.40 — 1.50 ns tBSR Block PT Set/Reset Delay — 1.10 — 1.85 ns tPTSR Macrocell PT Set/Reset Delay — 1.20 — 1.90 ns tBIE Power Guard Block Input Enable Delay — 1.60 — 1.70 ns tPTOE Macrocell PT OE Delay — 2.30 — 3.15 ns tGPTOE Global PT OE Delay — 1.80 — 2.15 ns Internal Oscillator t OSCSU Oscillator DYNOSCDIS Setup Time 5.00 — 5.00 — ns tOSCH Oscillator DYNOSCDIS Hold Time 5.00 — 5.00 — ns tOSCEN Oscillator OSCOUT Enable Time (To Stable) — 5.00 — 5.00 ns tOSCOD Oscillator Output Delay — 4.00 — 4.00 ns tOSCNOM Oscillator OSCOUT Nominal Frequency 5.00 5.00 MHz tOSCvar Oscillator Variation of Nominal Frequency — 30 — 30 % tTMRCO20 Oscillator TIMEROUT Clock (Negative Edge) to Out (20-Bit Divider) — 12.50 — 12.50 ns tTMRCO10 Oscillator TIMEROUT Clock (Negative Edge) to Out (10-Bit Divider) — 7.50 — 7.50 ns tTMRCO7 Oscillator TIMEROUT Clock (Negative Edge) to Out (7-Bit Divider) — 6.00 — 6.00 ns tTMRRSTO Oscillator TIMEROUT Reset to Out (Going Low) — 5.00 — 5.00 ns tTMRRR Oscillator TIMEROUT Asynchronous Reset Recovery Delay — 4.00 — 4.00 ns tTMRRSTPW Oscillator TIMEROUT Reset Minimum Pulse Width 3.00 — 3.00 — ns Optional Delay Adjusters Base Parameter t INDIO Input Register Delay t INREG — 1.00 — 1.00 ns tEXP Product Term Expander Delay t MCELL — 0.40 — 0.40 ns tBLA Additional Block Loading Adders t ROUTE — 0.04 — 0.05 ns tIOI Input Buffer Delays LVTTL_in Using LVTTL standard t IN, tGCLK_IN, tGOE — 0.60 — 0.60 ns LVCMOS15_in Using LVCMOS 1.5 Standard t IN, tGCLK_IN, tGOE — 0.20 — 0.20 ns LVCMOS18_in Using LVCMOS 1.8 Standard t IN, tGCLK_IN, tGOE — 0.00 — 0.00 ns LVCMOS25_in Using LVCMOS 2.5 Standard with Hysteresis tIN, tGCLK_IN, tGOE — 0.80 — 0.80 ns LVCMOS33_in Using LVCMOS 3.3 Standard with Hysteresis tIN, tGCLK_IN, tGOE — 0.80 — 0.80 ns PCI_in Using PCI Compatible Input with Hysteresis tIN, tGCLK_IN, tGOE — 0.80 — 0.80 ns tIOO Output Buffer Delays LVTTL_out Output Configured as TTL Buffer t EN, tDIS, tBUF — 0.20 — 0.20 ns LVCMOS15_out Output Configured as 1.5V Buffer t EN, tDIS, tBUF — 0.20 — 0.20 ns ispMACH 4000ZE Internal Timing Parameters (Cont.) Over Recommended Operating Conditions Parameter Description LC4032ZE LC4064ZE Units -4 -4 Min. Max. Min. Max.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet LVCMOS18_out Output Configured as 1.8V Buffer t EN, tDIS, tBUF — 0.00 — 0.00 ns LVCMOS25_out Output Configured as 2.5V Buffer t EN, tDIS, tBUF — 0.10 — 0.10 ns LVCMOS33_out Output Configured as 3.3V Buffer t EN, tDIS, tBUF — 0.20 — 0.20 ns PCI_out Output Configured as PCI Compati- ble Buffer tEN, tDIS, tBUF — 0.20 — 0.20 ns Slow Slew Output Configured for Slow Slew Rate tEN, tBUF — 1.00 — 1.00 ns Note: Internal Timing Parameters are not tested and are for reference only. Refer to the timing model in this data sheet for further details. Timing v.0.8 ispMACH 4000ZE Internal Timing Parameters (Cont.) Over Recommended Operating Conditions Parameter Description LC4032ZE LC4064ZE Units -4 -4 Min. Max. Min. Max.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet ispMACH 4000ZE Internal Timing Parameters (Cont.) Over Recommended Operating Conditions Parameter Description All Devices Units -5 -7 Min. Max. Min. Max. In/Out Delays t IN Input Buffer Delay — 1.05 — 1.90 ns tGCLK_IN Global Clock Input Buffer Delay — 1.95 — 2.15 ns tGOE Global OE Pin Delay — 3.00 — 4.30 ns tBUF Delay through Output Buffer — 1.10 — 1.30 ns tEN Output Enable Time — 2.50 — 2.70 ns tDIS Output Disable Time — 2.50 — 2.70 ns tPGSU Input Power Guard Setup Time — 4.30 — 5.60 ns tPGH Input Power Guard Hold Time — 0.00 — 0.00 ns tPGPW Input Power Guard BIE Minimum Pulse Width — 6.00 — 8.00 ns tPGRT Input Power Guard Recovery Time Following BIE Dis- sertation — 5.00 — 7.00 ns Routing Delays tROUTE Delay through GRP — 2.25 — 2.50 ns tPDi Macrocell Propagation Delay — 0.45 — 0.50 ns tMCELL Macrocell Delay — 0.65 — 1.00 ns tINREG Input Buffer to Macrocell Register Delay — 1.00 — 1.00 ns tFBK Internal Feedback Delay — 0.75 — 0.30 ns tORP Output Routing Pool Delay — 0.30 — 0.30 ns Register/Latch Delays tS D-Register Setup Time (Global Clock) 0.90 — 1.25 — ns tS_PT D-Register Setup Time (Product Term Clock) 2.00 — 2.35 — ns tH D-Register Hold Time 2.00 — 3.25 — ns tST T -Register Setup Time (Global Clock) 1.10 — 1.45 — ns tST_PT T -register Setup Time (Product Term Clock) 2.20 — 2.65 — ns tHT T -Resister Hold Time 2.00 — 3.25 — ns tSIR D-Input Register Setup Time (Global Clock) 1.20 — 0.65 — ns tSIR_PT D-Input Register Setup Time (Product Term Clock) 1.45 — 1.45 — ns tHIR D-Input Register Hold Time (Global Clock) 1.40 — 2.05 — ns tHIR_PT D-Input Register Hold Time (Product Term Clock) 1.10 — 1.20 — ns tCOi Register Clock to Output/Feedback MUX Time — 0.45 — 0.75 ns tCES Clock Enable Setup Time 2.00 — 2.00 — ns tCEH Clock Enable Hold Time 0.00 — 0.00 — ns tSL Latch Setup Time (Global Clock) 0.90 — 1.55 — ns tSL_PT Latch Setup Time (Product Term Clock) 2.00 — 2.05 — ns tHL Latch Hold Time 2.00 — 1.17 — ns tGOi Latch Gate to Output/Feedback MUX Time — 0.35 — 0.33 ns tPDLi Propagation Delay through Transparent Latch to Output/ Feedback MUX — 0.25 — 0.25 ns tSRi Asynchronous Reset or Set to Output/Feedback MUX Delay — 0.95 — 0.28 ns

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet tSRR Asynchronous Reset or Set Recovery Delay — 1.80 — 1.67 ns Control Delays t BCLK GLB PT Clock Delay — 1.45 — 0.95 ns tPTCLK Macrocell PT Clock Delay — 1.45 — 1.15 ns tBSR Block PT Set/Reset Delay — 1.85 — 1.83 ns tPTSR Macrocell PT Set/Reset Delay — 1.85 — 2.72 ns tBIE Power Guard Block Input Enable Delay — 1.75 — 1.95 ns tPTOE Macrocell PT OE Delay — 2.40 — 1.90 ns tGPTOE Global PT OE Delay — 4.20 — 3.40 ns Internal Oscillator t OSCSU Oscillator DYNOSCDIS Setup Time 5.00 — 5.00 — ns tOSCH Oscillator DYNOSCDIS Hold Time 5.00 — 5.00 — ns tOSCEN Oscillator OSCOUT Enable Time (To Stable) — 5.00 — 5.00 ns tOSCOD Oscillator Output Delay — 4.00 — 4.00 ns tOSCNOM Oscillator OSCOUT Nominal Frequency 5.00 5.00 MHz tOSCvar Oscillator Variation of Nominal Frequency — 30 — 30 % tTMRCO20 Oscillator TIMEROUT Clock (Negative Edge) to Out (20-Bit Divider) — 12.50 — 14.50 ns tTMRCO10 Oscillator TIMEROUT Clock (Negative Edge) to Out (10-Bit Divider) — 7.50 — 9.50 ns tTMRCO7 Oscillator TIMEROUT Clock (Negative Edge) to Out (7-Bit Divider) — 6.00 — 8.00 ns tTMRRSTO Oscillator TIMEROUT Reset to Out (Going Low) — 5.00 — 7.00 ns tTMRRR Oscillator TIMEROUT Asynchronous Reset Recovery Delay — 4.00 — 6.00 ns tTMRRSTPW Oscillator TIMEROUT Reset Minimum Pulse Width 3.00 — 5.00 — ns Optional Delay Adjusters Base Parameter t INDIO Input Register Delay t INREG — 1.60 — 2.60 ns tEXP Product Term Expander Delay t MCELL — 0.45 — 0.50 ns tBLA Additional Block Loading Adders t ROUTE — 0.05 — 0.05 ns tIOI Input Buffer Delays LVTTL_in Using LVTTL standard t IN, tGCLK_IN, tGOE — 0.60 — 0.60 ns LVCMOS15_in Using LVCMOS 1.5 standard t IN, tGCLK_IN, tGOE — 0.20 — 0.20 ns LVCMOS18_in Using LVCMOS 1.8 standard t IN, tGCLK_IN, tGOE — 0.00 — 0.00 ns LVCMOS25_in Using LVCMOS 2.5 standard with Hysteresis tIN, tGCLK_IN, tGOE — 0.80 — 0.80 ns LVCMOS33_in Using LVCMOS 3.3 standard with Hysteresis tIN, tGCLK_IN, tGOE — 0.80 — 0.80 ns PCI_in Using PCI compatible input with Hysteresis tIN, tGCLK_IN, tGOE — 0.80 — 0.80 ns tIOO Output Buffer Delays LVTTL_out Output configured as TTL buffer t EN, tDIS, tBUF — 0.20 — 0.20 ns ispMACH 4000ZE Internal Timing Parameters (Cont.) Over Recommended Operating Conditions Parameter Description All Devices Units -5 -7 Min. Max. Min. Max.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet LVCMOS15_out Output configured as 1.5V buffer t EN, tDIS, tBUF — 0.20 — 0.20 ns LVCMOS18_out Output configured as 1.8V buffer t EN, tDIS, tBUF — 0.00 — 0.00 ns LVCMOS25_out Output configured as 2.5V buffer t EN, tDIS, tBUF — 0.10 — 0.10 ns LVCMOS33_out Output configured as 3.3V buffer t EN, tDIS, tBUF — 0.20 — 0.20 ns PCI_out Output configured as PCI compati- ble buffer tEN, tDIS, tBUF — 0.20 — 0.20 ns Slow Slew Output configured for slow slew rate t EN, tBUF — 1.00 — 1.00 ns Note: Internal Timing Parameters are not tested and are for reference only. Refer to the timing model in this data sheet for further details. Timing v.0.8 ispMACH 4000ZE Internal Timing Parameters (Cont.) Over Recommended Operating Conditions Parameter Description All Devices Units -5 -7 Min. Max. Min. Max.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet Boundary Scan Waveforms and Timing Specifications Symbol Parameter Min. Max. Units tBTCP TCK [BSCAN test] clock cycle 40 — ns tBTCH TCK [BSCAN test] pulse width high 20 — ns tBTCL TCK [BSCAN test] pulse width low 20 — ns tBTSU TCK [BSCAN test] setup time 8 — ns tBTH TCK [BSCAN test] hold time 10 — ns tBRF TCK [BSCAN test] rise and fall time 50 — mV/ns tBTCO TAP controller falling edge of clock to valid output — 10 ns tBTOZ TAP controller falling edge of clock to data output disable — 10 ns tBTVO TAP controller falling edge of clock to data output enable — 10 ns tBTCPSU BSCAN test Capture register setup time 8 — ns tBTCPH BSCAN test Capture register hold time 10 — ns tBTUCO BSCAN test Update reg, falling edge of clock to valid output — 25 ns tBTUOZ BSCAN test Update reg, falling edge of clock to output disable — 25 ns tBTUOV BSCAN test Update reg, falling edge of clock to output enable — 25 ns

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet Power Consumption Power Estimation Coefficients1 Device A B ispMACH 4032ZE 0.010 0.009 ispMACH 4064ZE 0.011 0.009 ispMACH 4128ZE 0.012 0.009 ispMACH 4256ZE 0.013 0.009 1. For further information about the use of these coefficients, refer to Technical Note TN1175, Power Estimation in ispMACH 4000ZE Devices. 4032ZE 4064ZE 4128ZE 4256ZE ispMACH 4000ZE Typical ICC vs. Frequency 0 50 100 150 200 250 300 Frequency (MHz) Icc (mA)

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet Signal Descriptions ORP Reference Table Signal Names Description TMS Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control the state machine. TCK Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the state machine. TDI Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data. TDO Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out. GOE0/IO, GOE1/IO These pins are configured to be either Global Output Enable Input or as general I/O pins. GND Ground NC Not Connected V CC The power supply pins for logic core and JTAG port. CLK0/I, CLK1/I, CLK2/I, CLK3/I These pins are configured to be either CLK input or as an input. V CCO0, VCCO1 The power supply pins for each I/O bank. yzz Input/Output1 – These are the general purpose I/O used by the logic array. y is GLB reference (alpha) and z is macrocell reference (numeric). z: 0-15. ispMACH 4032ZE y: A-B ispMACH 4064ZE y: A-D ispMACH 4128ZE y: A-H ispMACH 4256ZE y: A-P 1. In some packages, certain I/Os are only available for use as inputs. See the signal connections table for details. 4032ZE 4064ZE 4128ZE 4256ZE Number of I/Os 32 32 48 64 64 96 64 96 108 Number of GLBs 244488 1 6 1 6 1 6 Number of I/Os per GLB 16 8 Mixture of 9, 10, 14, 15 16 8 12 4 6 Mixture of 6, 7, 8 Reference ORP Table (I/Os per GLB) 16 8 9, 10, 14, 15 16 8 12 4 6 6, 7, 8

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet ispMACH 4000ZE Power Supply and NC Connections1 Signal 48 TQFP 2 64 csBGA3, 4 100 TQFP2 VCC 12, 36 E4, D5 25, 40, 75, 90 VCCO0 VCCO (Bank 0) 6 4032ZE: E3 4064ZE: E3, F4 13, 33, 95 VCCO1 VCCO (Bank 1) 30 4032ZE: D6 4064ZE: D6, C6 45, 63, 83 GND 13, 37 D4, E5 1, 26, 51, 76 GND (Bank 0) 5 D4, E5 7, 18, 32, 96 GND (Bank 1) 29 D4, E5 46, 57, 68, 82 N C ——— 1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with the bank shown. 2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and nu merical order ascending horizontally. 4. All bonded grounds are connected to the following two balls, D4 and E5.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet ispMACH 4000ZE Power Supply and NC Connections1 (Cont.) Signal 144 csBGA 3 144 TQFP2 VCC H5, H8, E8, E5 36, 57, 108, 129 VCCO0 VCCO (Bank 0) E4, F4, G4, J5, D5 3, 19, 34, 47, 136 VCCO1 VCCO (Bank 1) J8, H9, G9, F9, D8 64, 75, 91, 106, 119 GND F6, G6, G7, F7 1, 37, 73, 109 GND (Bank 0) G5, H4, H6, E6, F5 10, 18 4, 27, 46, 127, 137 GND (Bank 1) H7, J9, G8, F8, E7 55, 65, 82, 90 4, 99, 118 NC 4064ZE: E4, B2, B1, D2, D3, E1, H1, H3, H2, L1, G4, M1, K3, M2, M4, L5, H7, L8, M8, L10, K9, M11, H9, L12, L11, J12, J11, H10, D10, F10, D12, B12, F9, A12, C10, B10, A9, B8, E6, B5, A5, C4, B3, A2 4128ZE: D2, D3, H2, M1, K3, M11, J12, J11, D12, A12, C10, A2 4128ZE: 17, 20, 38, 45, 72, 89, 92, 110, 117, 144 4256ZE: 18, 90 1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with the bank shown. 2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and nu merical order ascending horizontally. 4. For the LC4256ZE, pins 18 and 90 are no connects.

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet ispMACH 4032ZE and 4064ZE Logic Signal Connections: 48 TQFP Pin Number Bank Number ispMACH 4032ZE ispMACH 4064ZE GLB/MC/Pad GLB/MC/Pad 1 - TDI TDI 2 0 A5 A8 3 0 A6 A10 4 0 A7 A11 5 0 GND (Bank 0) GND (Bank 0) 6 0 VCCO (Bank 0) VCCO (Bank 0) 7 0 A8 B15 8 0 A9 B12 9 0 A10 B10 10 0 A11 B8 11 - TCK TCK 12 - VCC VCC 13 - GND GND 14 0 A12 B6 15 0 A13 B4 16 0 A14 B2 17 0 A15 B0 18 0 CLK1/I CLK1/I 19 1 CLK2/I CLK2/I 20 1 B0 C0 21 1 B1 C1 22 1 B2 C2 23 1 B3 C4 24 1 B4 C6 25 - TMS TMS 26 1 B5 C8 27 1 B6 C10 28 1 B7 C11 29 1 GND (Bank 1) GND (Bank 1) 30 1 VCCO (Bank 1) VCCO (Bank 1) 31 1 B8 D15 32 1 B9 D12 33 1 B10 D10 34 1 B11 D8 35 - TDO TDO 36 - VCC VCC 37 - GND GND 38 1 B12 D6 39 1 B13 D4 40 1 B14 D2 41 1 B15/GOE1 D0/GOE1 42 1 CLK3/I CLK3/I

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 43 0 CLK0/I CLK0/I 44 0 A0/GOE0 A0/GOE0 45 0 A1 A1 46 0 A2 A2 47 0 A3 A4 48 0 A4 A6 ispMACH 4032ZE and 4064ZE Logic Signal Connections: 48 TQFP (Cont.) Pin Number Bank Number ispMACH 4032ZE ispMACH 4064ZE GLB/MC/Pad GLB/MC/Pad

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet ispMACH 4032ZE and 4064ZE Logic Signal Connections: 64 csBGA Ball Number Bank Number ispMACH 4032ZE ispMACH 4064ZE GLB/MC/Pad GLB/MC/Pad B2 - TDI TDI B 10A 5 A 8 C2 0 A6 A10 C1 0 A7 A11 GND* 0 GND (Bank 0) GND (Bank 0) C3 0 NC A12 E3 0 VCCO (Bank 0) VCCO (Bank 0) D1 0 A8 B15 D2 0 NC B14 E1 0 A9 B13 D3 0 A10 B12 F1 0 A11 B11 E2 0 NC B10 G1 0 NC B9 F2 0 NC B8 H1 - TCK TCK E4 - VCC VCC GND* - GND GND G2 0 A12 B6 H2 0 NC B5 H3 0 A13 B4 GND* 0 NC GND (Bank 0) F4 0 NC VCCO (Bank 0) G3 0 A14 B3 F3 0 NC B2 H4 0 A15 B0 G4 0 CLK1/I CLK1/I H5 1 CLK2/I CLK2/I F5 1 B0 C0 G5 1 B1 C1 G6 1 B2 C2 H6 1 B3 C4 F6 1 B4 C5 H7 1 NC C6 H8 - TMS TMS G7 1 B5 C8 F7 1 B6 C10 G8 1 B7 C11 GND* 1 GND (Bank 0) GND (Bank 1) F8 1 NC C12 D6 1 VCCO (Bank 1) VCCO (Bank 1) E8 1 B8 D15

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet E7 1 NC D14 E6 1 B9 D13 D7 1 B10 D12 D8 1 NC D11 C5 1 NC D10 C7 1 B11 D9 C8 1 NC D8 B8 - TDO TDO D5 - VCC VCC GND* - GND GND A8 1 B12 D7 A7 1 NC D6 B7 1 NC D5 A6 1 B13 D4 GND* 1 NC GND (Bank 1) C6 1 NC VCCO (Bank 1) B6 1 B14 D3 A5 1 NC D2 B5 1 B15/GOE1 D0/GOE1 A4 1 CLK3/I CLK3/I C4 0 CLK0/I CLK0/I B4 0 A0/GOE0 A0/GOE0 B 30A 1 A 1 A 30A 2 A 2 A 20A 3 A 4 A 10A 4 A 6 * All bonded grounds are connected to the following two balls, D4 and E5. ispMACH 4032ZE and 4064ZE Logic Signal Connections: 64 csBGA (Cont.) Ball Number Bank Number ispMACH 4032ZE ispMACH 4064ZE GLB/MC/Pad GLB/MC/Pad

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections:

100 TQFP

LC4064ZE LC4128ZE LC4256ZE GLB/MC/Pad GLB/MC/Pad GLB/MC/Pad 1 - GND GND GND 2 - TDI TDI TDI 3 0 A8 B0 C12 4 0 A9 B2 C10 5 0 A10 B4 C6 6 0 A11 B6 C2 7 0 GND (Bank 0) GND (Bank 0) GND (Bank 0) 8 0 A12 B8 D12 9 0 A13 B10 D10 10 0 A14 B12 D6 11 0 A15 B13 D4 12* 0 I I I 13 0 VCCO (Bank 0) VCCO (Bank 0) VCCO (Bank 0) 14 0 B15 C14 E4 15 0 B14 C12 E6 16 0 B13 C10 E10 17 0 B12 C8 E12 18 0 GND (Bank 0) GND (Bank 0) GND (Bank 0) 19 0 B11 C6 F2 20 0 B10 C5 F6 21 0 B9 C4 F10 22 0 B8 C2 F12 23* 0 I I I 24 - TCK TCK TCK 25 - VCC VCC VCC 26 - GND GND GND 27* 0 I I I 28 0 B7 D13 G12 29 0 B6 D12 G10 30 0 B5 D10 G6 31 0 B4 D8 G2 32 0 GND (Bank 0) GND (Bank 0) GND (Bank 0) 33 0 VCCO (Bank 0) VCCO (Bank 0) VCCO (Bank 0) 34 0 B3 D6 H12 35 0 B2 D4 H10 36 0 B1 D2 H6 37 0 B0 D0 H2 38 0 CLK1/I CLK1/I CLK1/I 39 1 CLK2/I CLK2/I CLK2/I 40 - VCC VCC VCC 41 1 C0 E0 I2

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 42 1 C1 E2 I6 43 1 C2 E4 I10 44 1 C3 E6 I12 45 1 VCCO (Bank 1) VCCO (Bank 1) VCCO (Bank 1) 46 1 GND (Bank 1) GND (Bank 1) GND (Bank 1) 47 1 C4 E8 J2 48 1 C5 E10 J6 49 1 C6 E12 J10 50 1 C7 E14 J12 51 - GND GND GND 52 - TMS TMS TMS 53 1 C8 F0 K12 54 1 C9 F2 K10 55 1 C10 F4 K6 56 1 C11 F6 K2 57 1 GND (Bank 1) GND (Bank 1) GND (Bank 1) 58 1 C12 F8 L12 59 1 C13 F10 L10 60 1 C14 F12 L6 61 1 C15 F13 L4 62* 1 I I I 63 1 VCCO (Bank 1) VCCO (Bank 1) VCCO (Bank 1) 64 1 D15 G14 M4 65 1 D14 G12 M6 66 1 D13 G10 M10 67 1 D12 G8 M12 68 1 GND (Bank 1) GND (Bank 1) GND (Bank 1) 69 1 D11 G6 N2 70 1 D10 G5 N6 71 1 D9 G4 N10 72 1 D8 G2 N12 73* 1 I I I 74 - TDO TDO TDO 75 - VCC VCC VCC 76 - GND GND GND 77* 1 I I I 78 1 D7 H13 O12 79 1 D6 H12 O10 80 1 D5 H10 O6 81 1 D4 H8 O2 82 1 GND (Bank 1) GND (Bank 1) GND (Bank 1) ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 100 TQFP (Cont.) Pin Number Bank Number LC4064ZE LC4128ZE LC4256ZE GLB/MC/Pad GLB/MC/Pad GLB/MC/Pad

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 83 1 VCCO (Bank 1) VCCO (Bank 1) VCCO (Bank 1) 84 1 D3 H6 P12 85 1 D2 H4 P10 86 1 D1 H2 P6 87 1 D0/GOE1 H0/GOE1 P2/GOE1 88 1 CLK3/I CLK3/I CLK3/I 89 0 CLK0/I CLK0/I CLK0/I 90 - VCC VCC VCC 91 0 A0/GOE0 A0/GOE0 A2/GOE0 9 2 0 A 1A 2A 6 93 0 A2 A4 A10 94 0 A3 A6 A12 95 0 VCCO (Bank 0) VCCO (Bank 0) VCCO (Bank 0) 96 0 GND (Bank 0) GND (Bank 0) GND (Bank 0) 9 7 0 A 4A 8B 2 98 0 A5 A10 B6 99 0 A6 A12 B10 100 0 A7 A14 B12 * This pin is input only. ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 100 TQFP (Cont.) Pin Number Bank Number LC4064ZE LC4128ZE LC4256ZE GLB/MC/Pad GLB/MC/Pad GLB/MC/Pad

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 144 csBGA Ball Number Bank Number LC4064ZE LC4128ZE LC4256ZE GLB/MC/Pad GLB/MC/Pad GLB/MC/Pad F6 - GND GND GND A1 - TDI TDI TDI E4 0 NC Ball VCCO (Bank 0) VCCO (Bank 0) B2 0 NC Ball B0 C12 B1 0 NC Ball B1 C10 C3 0 A8 B2 C8 C2 0 A9 B4 C6 C1 0 A10 B5 C4 D1 0 A11 B6 C2 G5 0 GND (Bank 0) GND (Bank 0) GND (Bank 0) D2 0 NC Ball NC Ball D14 D3 0 NC Ball NC Ball D12 E1 0 NC Ball B8 D10 E2 0 A12 B9 D8 F2 0 A13 B10 D6 D4 0 A14 B12 D4 F1 0 A15 B13 D2 F3* 0 I B14 D0 F4 0 VCCO (Bank 0) VCCO (Bank 0) VCCO (Bank 0) G1 0 B15 C14 E0 E3 0 B14 C13 E2 G2 0 B13 C12 E4 G3 0 B12 C10 E6 H1 0 NC Ball C9 E8 H3 0 NC Ball C8 E10 H2 0 NC Ball NC Ball E12 H4 0 GND (Bank 0) GND (Bank 0) GND (Bank 0) J1 0 B11 C6 F2 J3 0 B10 C5 F4 J2 0 B9 C4 F6 K1 0 B8 C2 F8 K2* 0 I C1 F10 L1 0 NC Ball C0 F12 G4 0 NC Ball VCCO (Bank 0) VCCO (Bank 0) L2 - TCK TCK TCK H5 - VCC VCC VCC G6 - GND GND GND M1 0 NC Ball NC Ball G14 K3 0 NC Ball NC Ball G12 M2 0 NC Ball D14 G10 L3* 0 I D13 G8

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet J4 0 B7 D12 G6 K4 0 B6 D10 G4 M3 0 B5 D9 G2 L4 0 B4 D8 G0 H6 0 GND (Bank 0) GND (Bank 0) GND (Bank 0) J5 0 VCCO (Bank 0) VCCO (Bank 0) VCCO (Bank 0) M4 0 NC Ball D6 H12 L5 0 NC Ball D5 H10 K5 0 B3 D4 H8 J6 0 B2 D2 H6 M5 0 B1 D1 H4 K6 0 B0 D0 H2 L6 0 CLK1/I CLK1/I CLK1/I H7 1 NC Ball GND (Bank 1) GND (Bank 1) M6 1 CLK2/I CLK2/I CLK2/I H8 - VCC VCC VCC K7 1 C0 E0 I2 M7 1 C1 E1 I4 L7 1 C2 E2 I6 J7 1 C3 E4 I8 L8 1 NC Ball E5 I10 M8 1 NC Ball E6 I12 J8 1 VCCO (Bank 1) VCCO (Bank 1) VCCO (Bank 1) J9 1 GND (Bank 1) GND (Bank 1) GND (Bank 1) M9 1 C4 E8 J2 L9 1 C5 E9 J4 K8 1 C6 E10 J6 M10 1 C7 E12 J8 L10 1 NC Ball E13 J10 K9 1 NC Ball E14 J12 M11 1 NC Ball NC Ball J14 G7 - GND GND GND M12 - TMS TMS TMS H9 1 NC Ball VCCO (Bank 1) VCCO (Bank 1) L12 1 NC Ball F0 K12 L11 1 NC Ball F1 K10 K10 1 C8 F2 K8 K12 1 C9 F4 K6 J10 1 C10 F5 K4 K11 1 C11 F6 K2 G8 1 GND (Bank 1) GND (Bank 1) GND (Bank 1) ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 144 csBGA (Cont.) Ball Number Bank Number LC4064ZE LC4128ZE LC4256ZE GLB/MC/Pad GLB/MC/Pad GLB/MC/Pad

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet J12 1 NC Ball NC Ball L14 J11 1 NC Ball NC Ball L12 H10 1 NC Ball F8 L10 H12 1 C12 F9 L8 G11 1 C13 F10 L6 H11 1 C14 F12 L4 G12 1 C15 F13 L2 G10* 1 I F14 L0 G9 1 VCCO (Bank 1) VCCO (Bank 1) VCCO (Bank 1) F12 1 D15 G14 M0 F11 1 D14 G13 M2 E11 1 D13 G12 M4 E12 1 D12 G10 M6 D10 1 NC Ball G9 M8 F10 1 NC Ball G8 M10 D12 1 NC Ball NC Ball M12 F8 1 GND (Bank 1) GND (Bank 1) GND (Bank 1) E10 1 D11 G6 N2 D11 1 D10 G5 N4 E 9 1 D 9G 4N 6 C 1 2 1 D 8G 2N 8 C11* 1 I G1 N10 B12 1 NC Ball G0 N12 F9 1 NC Ball VCCO (Bank 1) VCCO (Bank 1) B11 - TDO TDO TDO E8 - VCC VCC VCC F7 - GND GND GND A12 1 NC Ball NC Ball O14 C10 1 NC Ball NC Ball O12 B10 1 NC Ball H14 O10 A11* 1 I H13 O8 D9 1 D7 H12 O6 B9 1 D6 H10 O4 C9 1 D5 H9 O2 A10 1 D4 H8 O0 E7 1 GND (Bank 1) GND (Bank 1) GND (Bank 1) D8 1 VCCO (Bank 1) VCCO (Bank 1) VCCO (Bank 1) A9 1 NC Ball H6 P12 B8 1 NC Ball H5 P10 C8 1 D3 H4 P8 A8 1 D2 H2 P6 ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 144 csBGA (Cont.) Ball Number Bank Number LC4064ZE LC4128ZE LC4256ZE GLB/MC/Pad GLB/MC/Pad GLB/MC/Pad

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet D7 1 D1 H1 P4 B7 1 D0/GOE1 H0/GOE1 P2/GOE1 C7 1 CLK3/I CLK3/I CLK3/I E6 0 NC Ball GND (Bank 0) GND (Bank 0) A7 0 CLK0/I CLK0/I CLK0/I E5 - VCC VCC VCC D6 0 A0/GOE0 A0/GOE0 A2/GOE0 B 6 0 A 1A 1A 4 A 6 0 A 2A 2A 6 C 6 0 A 3A 4A 8 B5 0 NC Ball A5 A10 A5 0 NC Ball A6 A12 D5 0 VCCO (Bank 0) VCCO (Bank 0) VCCO (Bank 0) F5 0 GND (Bank 0) GND (Bank 0) GND (Bank 0) A 4 0 A 4A 8B 2 B 4 0 A 5A 9B 4 C5 0 A6 A10 B6 A3 0 A7 A12 B8 C4 0 NC Ball A13 B10 B3 0 NC Ball A14 B12 A2 0 NC Ball NC Ball B14 * This pin is input only for the LC4064ZE. ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 144 csBGA (Cont.) Ball Number Bank Number LC4064ZE LC4128ZE LC4256ZE GLB/MC/Pad GLB/MC/Pad GLB/MC/Pad

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP Pin Number Bank Number LC4128ZE LC4256ZE GLB/MC/Pad GLB/MC/Pad 1 - GND GND 2 - TDI TDI 3 0 VCCO (Bank 0) VCCO (Bank 0) 4 0 B0 C12 5 0 B1 C10 6 0 B2 C8 7 0 B4 C6 8 0 B5 C4 9 0 B6 C2 10 0 GND (Bank 0) GND (Bank 0) 11 0 B8 D14 12 0 B9 D12 13 0 B10 D10 14 0 B12 D8 15 0 B13 D6 16 0 B14 D4 17* 0 NC I 18 0 GND (Bank 0) NC 19 0 VCCO (Bank 0) VCCO (Bank 0) 20* 0 NC I 21 0 C14 E2 22 0 C13 E4 23 0 C12 E6 24 0 C10 E8 25 0 C9 E10 26 0 C8 E12 27 0 GND (Bank 0) GND (Bank 0) 28 0 C6 F2 29 0 C5 F4 30 0 C4 F6 31 0 C2 F8 32 0 C1 F10 33 0 C0 F12 34 0 VCCO (Bank 0) VCCO (Bank 0) 35 - TCK TCK 36 - VCC VCC 37 - GND GND 38* 0 NC I 39 0 D14 G12 40 0 D13 G10 41 0 D12 G8 42 0 D10 G6

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 43 0 D9 G4 44 0 D8 G2 45* 0 NC I 46 0 GND (Bank 0) GND (Bank 0) 47 0 VCCO (Bank 0) VCCO (Bank 0) 48 0 D6 H12 49 0 D5 H10 50 0 D4 H8 51 0 D2 H6 52 0 D1 H4 53 0 D0 H2 54 0 CLK1/I CLK1/I 55 1 GND (Bank 1) GND (Bank 1) 56 1 CLK2/I CLK2/I 57 - VCC VCC 58 1 E0 I2 59 1 E1 I4 60 1 E2 I6 61 1 E4 I8 62 1 E5 I10 63 1 E6 I12 64 1 VCCO (Bank 1) VCCO (Bank 1) 65 1 GND (Bank 1) GND (Bank 1) 66 1 E8 J2 67 1 E9 J4 68 1 E10 J6 69 1 E12 J8 70 1 E13 J10 71 1 E14 J12 72* 1 NC I 73 - GND GND 74 - TMS TMS 75 1 VCCO (Bank 1) VCCO (Bank 1) 76 1 F0 K12 77 1 F1 K10 78 1 F2 K8 79 1 F4 K6 80 1 F5 K4 81 1 F6 K2 82 1 GND (Bank 1) GND (Bank 1) 83 1 F8 L14 84 1 F9 L12 85 1 F10 L10 ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.) Pin Number Bank Number LC4128ZE LC4256ZE GLB/MC/Pad GLB/MC/Pad

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 86 1 F12 L8 87 1 F13 L6 88 1 F14 L4 89* 1 NC I 90 1 GND (Bank 1) NC 91 1 VCCO (Bank 1) VCCO (Bank 1) 92* 1 NC I 93 1 G14 M2 94 1 G13 M4 95 1 G12 M6 96 1 G10 M8 97 1 G9 M10 98 1 G8 M12 99 1 GND (Bank 1) GND (Bank 1) 100 1 G6 N2 101 1 G5 N4 102 1 G4 N6 103 1 G2 N8 104 1 G1 N10 105 1 G0 N12 106 1 VCCO (Bank 1) VCCO (Bank 1) 107 - TDO TDO 108 - VCC VCC 109 - GND GND 110* 1 NC I 111 1 H14 O12 112 1 H13 O10 113 1 H12 O8 114 1 H10 O6 115 1 H9 O4 116 1 H8 O2 117* 1 NC I 118 1 GND (Bank 1) GND (Bank 1) 119 1 VCCO (Bank 1) VCCO (Bank 1) 120 1 H6 P12 121 1 H5 P10 122 1 H4 P8 123 1 H2 P6 124 1 H1 P4 125 1 H0/GOE1 P2/GOE1 126 1 CLK3/I CLK3/I 127 0 GND (Bank 0) GND (Bank 0) 128 0 CLK0/I CLK0/I ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.) Pin Number Bank Number LC4128ZE LC4256ZE GLB/MC/Pad GLB/MC/Pad

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 129 - VCC VCC 130 0 A0/GOE0 A2/GOE0 131 0 A1 A4 132 0 A2 A6 133 0 A4 A8 134 0 A5 A10 135 0 A6 A12 136 0 VCCO (Bank 0) VCCO (Bank 0) 137 0 GND (Bank 0) GND (Bank 0) 138 0 A8 B2 139 0 A9 B4 140 0 A10 B6 141 0 A12 B8 142 0 A13 B10 143 0 A14 B12 144* 0 NC I * This pin is input only for the LC4256ZE. ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.) Pin Number Bank Number LC4128ZE LC4256ZE GLB/MC/Pad GLB/MC/Pad

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet Lead-Free Packaging Commercial Devices Device Part Number Macrocells Voltage t PD Package Pin/Ball Count I/O Grade LC4032ZE LC4032ZE-4TN48C 32 1.8 4.4 Lead-Free TQFP 48 32 C LC4032ZE-5TN48C 32 1.8 5.8 Lead-Free TQFP 48 32 C LC4032ZE-7TN48C 32 1.8 7.5 Lead-Free TQFP 48 32 C LC4032ZE-4MN64C 32 1.8 4.4 Lead-Free csBGA 64 32 C LC4032ZE-5MN64C 32 1.8 5.8 Lead-Free csBGA 64 32 C LC4032ZE-7MN64C 32 1.8 7.5 Lead-Free csBGA 64 32 C LC4046ZE LC4064ZE-4TN48C 64 1.8 4.7 Lead-Free TQFP 48 32 C LC4064ZE-5TN48C 64 1.8 5.8 Lead-Free TQFP 48 32 C LC4064ZE-7TN48C 64 1.8 7.5 Lead-Free TQFP 48 32 C LC4064ZE-4TN100C 64 1.8 4.7 Lead-Free TQFP 100 64 C LC4064ZE-5TN100C 64 1.8 5.8 Lead-Free TQFP 100 64 C LC4064ZE-7TN100C 64 1.8 7.5 Lead-Free TQFP 100 64 C LC4064ZE-4MN64C 64 1.8 4.7 Lead-Free csBGA 64 48 C LC4064ZE-5MN64C 64 1.8 5.8 Lead-Free csBGA 64 48 C LC4064ZE-7MN64C 64 1.8 7.5 Lead-Free csBGA 64 48 C LC4064ZE-4MN144C 64 1.8 4.7 Lead-Free csBGA 144 64 C LC4064ZE-5MN144C 64 1.8 5.8 Lead-Free csBGA 144 64 C LC4064ZE-7MN144C 64 1.8 7.5 Lead-Free csBGA 144 64 C LC4128ZE LC4128ZE-5TN100C 128 1.8 5.8 Lead-Free TQFP 100 64 C LC4128ZE-7TN100C 128 1.8 7.5 Lead-Free TQFP 100 64 C LC4128ZE-5TN144C 128 1.8 5.8 Lead-Free TQFP 144 96 C LC4128ZE-7TN144C 128 1.8 7.5 Lead-Free TQFP 144 96 C LC4128ZE-5MN144C 128 1.8 5.8 Lead-Free csBGA 144 96 C LC4128ZE-7MN144C 128 1.8 7.5 Lead-Free csBGA 144 96 C LC4256ZE LC4256ZE-5TN100C 256 1.8 5.8 Lead-Free TQFP 100 64 C LC4256ZE-7TN100C 256 1.8 7.5 Lead-Free TQFP 100 64 C LC4256ZE-5TN144C 256 1.8 5.8 Lead-Free TQFP 144 96 C LC4256ZE-7TN144C 256 1.8 7.5 Lead-Free TQFP 144 96 C LC4256ZE-5MN144C 256 1.8 5.8 Lead-Free csBGA 144 108 C LC4256ZE-7MN144C 256 1.8 7.5 Lead-Free csBGA 144 108 C

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet Industrial For Further Information In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH 4000ZE family:

• TN1168 – ispMACH 4000ZE Timing Model Design and Usage Guidelines
• TN1174 – Advanced Features of the ispMACH 4000ZE
• TN1175 – Power Estimation and Management for ispMACH 4000ZE Devices Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www .latticesemi.com Device Part Number Macrocells Voltage t PD Package Pin/Ball Count I/O Grade LC4032ZE LC4032ZE-5TN48I 32 1.8 5.8 Lead-Free TQFP 48 32 I LC4032ZE-7TN48I 32 1.8 7.5 Lead-Free TQFP 48 32 I LC4032ZE-5MN64I 32 1.8 5.8 Lead-Free csBGA 64 32 I LC4032ZE-7MN64I 32 1.8 7.5 Lead-Free csBGA 64 32 I LC4064ZE LC4064ZE-5TN48I 64 1.8 5.8 Lead-Free TQFP 48 32 I LC4064ZE-7TN48I 64 1.8 7.5 Lead-Free TQFP 48 32 I LC4064ZE-5TN100I 64 1.8 5.8 Lead-Free TQFP 100 64 I LC4064ZE-7TN100I 64 1.8 7.5 Lead-Free TQFP 100 64 I LC4064ZE-5MN64I 64 1.8 5.8 Lead-Free csBGA 64 48 I LC4064ZE-7MN64I 64 1.8 7.5 Lead-Free csBGA 64 48 I LC4064ZE-5MN144I 64 1.8 5.8 Lead-Free csBGA 144 64 I LC4064ZE-7MN144I 64 1.8 7.5 Lead-Free csBGA 144 64 I LC4128ZE LC4128ZE-7TN100I 128 1.8 7.5 Lead-Free TQFP 100 64 I LC4128ZE-7TN144I 128 1.8 7.5 Lead-Free TQFP 144 96 I LC4128ZE-7MN144I 128 1.8 7.5 Lead-Free csBGA 144 96 I LC4256ZE LC4256ZE-7TN100I 256 1.8 7.5 Lead-Free TQFP 100 64 I LC4256ZE-7TN144I 256 1.8 7.5 Lead-Free TQFP 144 96 I LC4256ZE-7MN144I 256 1.8 7.5 Lead-Free csBGA 144 108 I

Lattice Semiconductor ispMACH 4000ZE Family Data Sheet

Revision History

Date Version Change Summary April 2008 01.0 Initial release. July 2008 01.1 Updated Features bullets. Updated typical Hysteresis voltage. Updated Power Guard for Dedicated Inputs section. Updated DC Electrical Characteristics table. Updated Supply Current table. Updated I/O DC Electrical Characteristics table and note 2. Updated ispMACH 4000ZE Timing Model. Added new parameters for the Internal Oscillator. Updated ORP Reference table. Updated Power Supply and NC Connections table. Updated 100 TQFP Logic Signal Connections table with LC4128ZE and 4256ZE. Updated 144 csBGA Logic Signal Connections table with LC4128ZE and 4256ZE. Added 144 TQFP Logic Signal Connections table. August 2008 01.2 Data sheet status changed from advance to final. Updated Supply Current table. Updated External Switching Characteristics. Updated Internal Timing Parameters. Updated Power Consumption graph and Power Estimation Coefficients table. Updated Ordering Information mark format example.