IMP805LESA

IMP690A IMP | Alldatasheet

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Technical content

Applications

u Embedded control systems u Battery–operated systems u Intelligent instruments u Wireless communication systems u PDAs and handheld equipment u mP/mC power supply monitoring u Design improvement over Maxim MAX690A/692A/802L/802M/805L — 70% lower current than Maxim: 100mA maximum — RESET Operation to 1.1V u Two precision supply-voltage monitor options — 4.65V (IMP690A/802L/805L) — 4.40V (IMP692A/802M) u Battery-backup power switch on-chip u Watchdog timer: 1.6 second timeout u Power failure/low battery detection u Short-circuit protection and thermal limiting u Small 8-pin SO package u No external components u Specified over full temperature range Block Diagrams GND Unregulated DC Regulated +5V VOUT VCC WDI3.6V Lithium Battery 0.1µF PFO V BATT PFI R 1 R 2 RESET RESET VCC GND GND VCC CMOS RAM NMI I/O LINE BUS 690A_01.eps IMP690A IMP690AIMP690A , 692A, 692A , 802L/M, 805L, 802L/M, 805L POWER MANAGEMENT µµP PP Poowwer Suppler Supply Supery Supervisorvisor witwith Batth Batterery Bacy Backup Switckup Switchh The IMP690A/IMP692A/IMP802L/IMP802M/IMP805L simplify power supply monitoring and control in microprocessor systems. Each circuit implements four functions: Reset control, watchdog monitoring, battery- backup switching and power-failure monitoring. In addition to microprocessor reset under powerup and power-down conditions, these devices provide battery-backup switching to maintain control in power- loss and brown-out situations. Additional monitoring capabilities can provide an early warning of unregulated power-supply loss before the voltage regulator drops out. The important features of these four functions are: a) 1.6 second watchdog timer to keep microprocessor responsive b) 4.40V or 4.65V V CC threshold for microprocessor reset at power-up and power-down c) SPDT (single-pole, double-throw) PMOS switch connects backup power to RAM if VCC fails d) 1.25V threshold detector for power loss or general purpose voltage monitoring While these features are pin–compatible with the industry standard power–supply supervisors offered by Maxim, the IMP devices are supe- rior replacements and can reduce power requirements by 70 percent when compared to Maxim MAX690/MAX692A/MAX802L/MAX802M/ MAX805L devices. Short-circuit and thermal protection have also been added. The IMP690A/IMP802L/IMP805L generate a reset pulse when the supply voltage drops below 4.65V , and the IMP692A/IMP802M generate a reset below 4.40V . The IMP802L/IMP802M have power–fail accuracy to ±2%. The IMP805L is the same as the IMP690A except that RESET is provided instead of‘‘‘‘‘‘‘RESET. IMP , Inc. San Jose, CA 408-432-9100/www.impweb.com + + VCC VOUT PFI WDI GND VBATT

4 PFO

IMP690A, IMP692A, IMP802L, IMP802M, IMP805L RESET (RESET) ( ) IMP805L Battery-Switchover Circuit Reset Generator Watchdog Timer3.5V 1.25V 1.25V 0.8V 690A_03.eps Typical Application

Ordering Information

IMP690AIMP690A , 692A, 692A , 802L, 802M, 805L, 802L, 802M, 805L 4PFI 3GND 2VCC 1VOUT

5 PFO

6 WDI

7 RESET (RESET)

8 VBA TT

690A_02.eps IMP690A IMP692A IMP802L IMP802M IMP805L ( ) IMP805L Plastic/CerDip/SO Part Number Reset Threshold (V) Temperature Range Pins-Package IMP690A IMP690ACP A 4.5 to 4.75 0°C to +70°C 8-Plastic DIP IMP690ACSA 4.5 to 4.75 0°C to +70°C 8-SO IMP690AC/D 4.5 to 4.75 25°C DICE IMP690AEP A –40°C to +85°C 8-Plastic DIP IMP690AESA 4.5 to 4.75 –40°C to +85°C 8-SO IMP690AMJA 4.5 to 4.75 Contact Factory 8-CerDIP IMP692A IMP692ACP A 4.25 to 4.50 0°C to +70°C 8-Plastic DIP IMP692ACSA 4.25 to 4.50 0°C to +70°C 8-SO IMP692AC/D 4.25 to 4.50 25°C DICE IMP692AEP A 4.25 to 4.50 –40°C to +85°C 8-Plastic DIP IMP692AESA 4.25 to 4.50 –40°C to +85°C 8-SO IMP692AMJA 4.25 to 4.50 Contact Factory 8-CerDIP IMP802L IMP802LCP A 4.5 to 4.75 0°C to +70°C 8-Plastic DIP IMP802LCSA 4.5 to 4.75 0°C to +70°C 8-SO IMP802LEP A 4.5 to 4.75 –40°C to +85°C 8-Plastic DIP IMP802LESA 4.5 to 4.75 –40°C to +85°C 8-SO IMP802M IMP802MCP A 4.25 to 4.50 0°C to +70°C 8-Plastic DIP IMP802MCSA 4.25 to 4.50 0°C to +70°C 8-SO IMP802MEP A 4.25 to 4.50 –40°C to +85°C 8-Plastic DIP IMP802MESA 4.25 to 4.50 –40°C to +85°C 8-SO IMP805L IMP805LCP A 4.5 to 4.75 0°C to +70°C 8-Plastic DIP IMP805LCSA 4.5 to 4.75 0°C to +70°C 8-SO IMP805LC/D 4.5 to 4.75 25°C DICE IMP805LEP A 4.5 to 4.75 –40°C to +85°C 8-Plastic DIP IMP805LESA 4.5 to 4.75 –40°C to +85°C 8-SO IMP805LMJA 4.5 to 4.75 Contact Factory 8-CerDIP

IMP690AIMP690A , 692A, 692A , 802L, 802M, 805L, 802L, 802M, 805L Absolute Maximum Ratings Pin Description Pin Terminal Voltage with Respect to Ground Output Current: Continuous Power Dissipation Plastic DIP (derate 9mW/°C above 70°C) . . . 800mW Operating Temperature Range (C Devices) . . . . 0°C to 70°C Operating Temperature Range (E Devices) . . . . –40°C to 85°C * The input voltage limits on PFI and WDI may be exceeded if the current is limited to less than 10mA These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for pr olonged time periods may affect device reliability. Pin Number IMP690A/IMP692A IMP802L/IMP802M IMP805L Name Function 1 1 VOUT Voltage supply for RAM. When VCC is above the reset threshold, VOUT connects to VCC through a P-channel MOS device. If VCC falls below the reset threshold, this output will be connected to the backup supply at V BATT (or VCC , whichever is higher) through the MOS switch to provide continuous power to the CMOS RAM. 2 2 VCC +5V power supply input 3 3 GND Ground 4 4 PFI Power failure monitor input. PFI is connected to the internal power fail comparator which is referenced to 1.25V. The power fail output (PFO) is active LOW but remains HIGH if PFI is above 1.25V. If this feature is unused, the PFI pin should be connected to GND or VOUT . 5 5 ‘‘‘‘PFO Power-fail output. ‘‘‘‘PFO is active LOW whenever the PFI pin is less than 1.25V. 6 6 WDI W atchdog input. The WDI input monitors microprocessor activity. An internal timer is reset with each transition of the WDI input. If WDI is held HIGH or LOW for longer than the watchdog timeout period, typically 1.6 seconds, RESET(or‘‘‘‘‘‘RESET) is asserted for the reset pulse width time, tRS , of 140ms, minimum. 7 –––– ‘‘‘‘‘‘‘RESET Active-LOW reset output. When triggered by VCC falling below the reset threshold or by watchdog timer timeout, RESET(or‘‘‘‘‘‘RESET) pulses low for the reset pulse width, tRS , typically 200ms. It will remain low if VCC is below the reset threshold (4.65V in the IMP690A/IMP802Land 4.4V in the IMP692A/IMP802L) and remains low for 200ms after VCC rise above the reset threshold. –––– 7 RESET Active-HIGH reset output. The inverse of‘‘‘‘‘‘RESET . 8 8 VBATT Auxiliary power or backup-battery input. VBATT should be connected to GND if the function is not used. This input has about 40m V of hysteresis to prevent rapid toggling between VCC and VBATT.

IMP690AIMP690A , 692A, 692A , 802L, 802M, 805L, 802L, 802M, 805L

Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Units VCC , VBATT Voltage Range IMP69_AC, IMP802_C 1.1 5.5 V (Note 1) IMP805LC 1.1 5.5 IMP69_AE, IMP80_ _E 1.1 5.5 Supply Current Excluding IOUT IS IMP69_AC, IMP802_C 35 100 mA IMP69_AE, IMP802_E, IMP805LE 35 100 ISUPPL Y in Battery-Backup Mode VCC = 0V, VBATT = 2.8V TA = 25°C 1.0 mA (Excluding IOUT ) TA = TMIN to TMAX 5.0 VBATT Standby Current 5.5V > VCC > VBATT – 0.2V TA = 25°C –0.1 0.02 mA (Note 2) TA = TMIN to TMAX –1.0 0.02 VOUT Output IOUT = 5mA VC C – 0.025 VCC – 0.010 V IOUT = 50mA VC C – 0.25 VCC – 0.10 VOUT in Battery-Backup Mode IOUT = 250mA, VCC < VBATT – 0.2V VBATT – 0.1 VBATT – 0.001 V Battery Switch Threshold, VCC < VR T Power-up 20 mV VCC to VBATT Power-down –20 Battery Switchover Hysteresis 40 mV Reset Threshold VR T IMP690A/802L/805L 4.50 4.65 4.75 V IMP692A, IMP802M 4.25 4.40 4.50 IMP802L, TA = 25°C, VCC falling 4.55 4.70 IMP802M, TA = 25°C, VCC falling 4.30 4.45 Reset Threshold Hysteresis 40 mV Reset Pulse Width tRS 140 200 280 ms Reset Output Voltage ISOURCE = 800µA VCC – 1.5 V ISINK = 3.2mA 0.4 IMP69_AC, IMP802_C, VCC = 1.0V, ISINK = 50mA 0.3 IMP69_AE, IMP802_E, VCC = 1.2V, ISINK = 100mA 0.3 IMP805LC, ISOURCE = 4mA, VCC = 1.1V 0.8 IMP805LE, ISOURCE = 4mA, VCC = 1.2V 0.9 IMP805L, ISOURCE = 800mA VCC – 1.5 IMP805L, ISINK = 3.2mA 0.4 W atchdog Timeout tWD 1.00 1.60 2.25 sec WDI Pulse Width tWP VIL= 0.4V, VIH = 0.8VCC 50 ns WDI Input Current WDI = VCC 50 150 mA WDI = 0V –150 –50 WDI Input Threshold VCC = 5V, Logic LOW 0.8 V (Note 3) VCC = 5V, Logic HIGH 3.5 PFI Input Threshold IMP69_A, IMP805L, VCC = 5V 1.20 1.25 1.30 V IMP802_C/E, VCC = 5V 1.225 1.250 1.275 PFI Input Current –25 0.01 25 nA PFO Output Voltage ISOURCE = 800µA VC C – 1.5 V ISINK = 3.2mA 0.4 Unless otherwise noted VCC = 4.75V to 5.5V for the IMP690A/IMP802L/IMP805L and VCC = 4.5V to 5.5V for the IMP692A/IMP802M; VBATT = 2.8V; and TA = TMIN to TMAX. Notes: 1. If VCC or VBATT is 0V, the other must be greater than 2.0V. 2. Battery charging-current is “–”. Battery discharge-current is “+”. 3. WDI is guaranteed to be in an intermediate level state if WDI is floating and VCC is within the operating voltage range. WDI input impedance is 50kW . WDI is biased to 0.3VCC.

IMP690AIMP690A , 692A, 692A , 802L, 802M, 805L, 802L, 802M, 805L

Application Information

It is important to initialize a micr oprocessor to a known state in response to specific events that could create code execution errors and “lock-up”. The reset output of these supervisory circuits send a r eset pulse to the micr oprocessor in r esponse to power -up, power-down/power-loss or a watchdog time-out. The reset pulse width, tRS, is typically ar ound 200ms and is LOW for the IMP690A, IMP692A, IMP802 and HIGH for the IMP805L. Power-up reset occurs when a rising VCC reaches the reset thresh- old, VRT, for cing a r eset condition in which the r eset output is asserted in the appr opriate logic state for the duration of tRS. Figure 2 shows the reset pin timing. Power-loss or “brown-out” reset occurs when VCC dips below the reset threshold resulting in a reset assertion for the duration of tRS. The reset signal r emains asserted as long as VCC is between VRT and 1.1V, the lowest VCC for which these devices can pr ovide a guaranteed logic-low output. To ensure logic inputs connected to the IMP690A/692A/802 RESET pin ar e in a known state when VCC is under 1.1V, a 100kW pull-down resistor at RESET is needed: the logic-high IMP805L will need a pull-up resistor to VCC. A Watchdog time-out reset occurs when a logic “1” or logic “0” is continuously applied to the WDI pin for mor e than 1.6 seconds. After the duration of the r eset interval, the watchdog timer starts a new 1.6 second timing interval; the microprocessor must service the watchdog input by changing states or by floating the WDI pin before this interval is finished. If the WDI pin is held either HIGH or LOW, a reset pulse will be triggered every 1.8 seconds (the 1.6 second timing interval plus the reset pulse width t RS). Microprocessor Interface. The IMP690 has logic- LOW RESET output while the IMP805 has an inverted logic-HIGH RESET output. Microprocessors with bi- directional reset pins (69HC1 1 for example) can pose a pr oblem when the supervisory circuit and the microprocessor output pins attempt to go to opposite logic states. The pr oblem can be resolved by placing a 4.7k W resistor between the RESET output and the microprocessor reset pin. This is shown in Figure 3. Since the series resistor limits drive capabilities, the reset signal to other devices should be buffered. + + VCC VOUT PFI WDI GND VBA TT IMP690A, IMP692A, IMP802L, IMP802M, IMP805L RESET (RESET) ( ) IMP805L Battery-Switchover Circuit Reset Generator W atchdog Timer3.5V 1.25V 1.25V 0.8V 690A_03.eps Figure 1. Block Diagram Figure 2. Timing Diagram Figure 3. Interfacing with bi-directional microprocessor

IMP690AIMP690A , 692A, 692A , 802L, 802M, 805L, 802L, 802M, 805L Package Dimensions E D eA eB C 0°–15° A e b2 b L A1 Plastic DIP (8-Pin)a.eps Plastic DIP (8-Pin) L 0°– 8° C HE e D B A1 A SO (8-Pin).eps Inches Millimeters Min Max Min Max Plastic DIP (8-Pin)* A2 0.115 0.195 2.92 4.95 b 0.014 0.022 0.36 0.56 b2 0.045 0.070 1.14 1.78 b3 0.030 0.045 0.80 1.14 D 0.355 0.400 9.02 10.16 E 0.300 0.325 7.62 8.26 E1 0.240 0.280 6.10 7.11 L 0.115 0.150 2.92 3.81 CerDIP (8-Pin) A1 0.015 0.070 0.38 1.78 b 0.014 0.023 0.36 0.58 b2 0.038 0.065 0.97 1.65 C 0.008 0.015 0.20 0.38 E 0.290 0.320 7.37 8.13 E1 0.220 0.310 5.59 7.87 e 0.100 2.54 L 0.125 0.200 3.18 5.08 SO (8-Pin)** A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 e 0.050 1.27 E 0.150 0.157 3.80 4.00 H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 D 0.189 0.197 4.80 5.00 SO (8-Pin) * JEDEC Drawing MS-001BA ** JEDEC Drawing MS-012AA E D C 0°–15° A e b2 b L A1 Ceramic DIP (8-Pin)a.eps CerDIP (8-Pin)

IMP690AIMP690A , 692A, 692A , 802L, 802M, 805L, 802L, 802M, 805L IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Tel: 800-438-3722 Fax: 408-434-0335 Fax-on-Demand: 1-800-249-1614 (USA) Fax-on-Demand: 1-303-575-6156 (International) e-mail: info@impinc.com http://www.impweb.com The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners. © 1998 IMP, Inc. Printed in USA Preliminary Part No.: IMP690A Document Number: IMP690A -2-9/98