IMP813LCUA

IMP705 IMP | Alldatasheet

Document overview

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Technical content

© 1999 IMP , Inc. 408-432-9100/www.impweb.com 1

Applications

N Computers and embedded controllers N Battery-operated systems N Intelligent instruments N Wireless communication systems N PDAs and handheld equipmentBlock Diagrams IMP705/6/7/8, 8IMP705/6/7/8, 8 113L3L POWER MANAGEMENT RESET RESET VCC 0.25mA RESET Generator 4.65V (IMP707) 4.40V (IMP708) VCC + – MR IMP707 IMP708 PFO GND 1.25V – +PFI 705_02.eps 1.25V – MR WDI IMP705 IMP706 IMP813L WDO RESET (RESET) (IMP813L) PFO GND VCC 0.25mA RESET Generator 4.65V (IMP705/813L) 4.40V (IMP706) VCC + – PFI Timebase Watchdog Timer Transition Detector 705_01.eps LoLoww-P-Poowwer er µµP SuperP Supervisor Cirvisor Circuitscuits – W– Watcatchdog timerhdog timer – Br– Br oownout detwnout det ectionection – P– Poowwer suppler suppl y monity monit oror The IMP705/706/707 /708 and IMP813L CMOS supervisor circuits monitor power-supply and battery voltage level, and µP/µC operation. Compared to pin-compatible devices offered by Maxim Integrated Products, IMP devices feature 60 percent lower maximum supply current. The family offers several functional options. Each device generates a reset signal during power-up, power-down and during brownout conditions. A reset is generated when the supply drops below 4.65V (IMP705/707 /813L) or 4.40V (IMP706/708). For 3V power supply applications, refer to the IMP705P/R/S/T data sheet. In addition, the IMP705/706/813L feature a 1.6 second watchdog timer. The IMP707 /708 have both active-HIGH and active-LOW reset outputs but no watchdog function. The IMP813L has the same pin-out and functions as the IMP705 but has an active-HIGH reset output. A versatile power-fail circuit has a 1.25V threshold, useful in checking battery levels and non-5V supplies. All devices have a manual reset (MR) input. The watchdog timer output will trigger a reset if connected to MR. All devices are available in 8-pin DIP , SO and MicroSO packages. Key Features N Improved replacements for the Maxim MAX705/6/7/8, MAX813L – 140µA maximum supply current – 60% improvement N Precision power supply monitor – 4.65V threshold (IMP705/707 /813L) – 4.40V threshold (IMP706/8) N Debounced manual reset input N Voltage monitor – 1.25V threshold – Battery monitor/Auxiliary supply monitor N Watchdog timer (IMP705/706/813L) N 200ms reset pulse width N Active HIGH reset output (IMP707 /708/813L) N MicroSO package

2 408-432-9100/www.impweb.com © 1999 IMP , Inc. IMP705/6/7/8, 8IMP705/6/7/8, 8 113L3L

Ordering Information

RESET (RESET) WDI PFO IMP705 IMP706 (IMP813L) IMP705 IMP706 (IMP813L) RESET (RESET) WDO MR V CC WDI PFO PFI GND 705_03.eps DIP/SO MicroSO Part Number Reset Threshold (V) Temperature Range Pins-Package IMP705 Active LOW Reset, Watchdog Output and Manual RESET IMP705CPA 4.65 0 °C to +70°C 8-Plastic DIP IMP705CSA 4.65 0 °C to +70°C 8-SO IMP705CUA 4.65 0 °C to +70°C 8-MicroSO IMP705C/D 4.65 25 °C Dice IMP705EPA 4.65 –40°C to +85°C 8-Plastic DIP IMP705ESA 4.65 –40°C to +85°C 8-SO IMP706ESA 4.40 –40°C to +85°C 8-SO IMP706 Active LOW Reset, Watchdog Output and Manual RESET IMP706CPA 4.40 0 °C to +70°C 8-Plastic DIP IMP706CSA 4.40 0 °C to +70°C 8-SO IMP706CUA 4.40 0 °C to +70°C 8-MicroSO IMP706C/D 4.40 25 °C Dice IMP706EPA 4.40 –40°C to +85°C 8-Plastic DIP IMP706ESA 4.40 –40°C to +85°C 8-SO IMP707 Active LOW & HIGH Reset with Manual RESET IMP707CPA 4.65 0 °C to +70°C 8-Plastic DIP IMP707CSA 4.65 0 °C to +70°C 8-SO IMP707CUA 4.65 0 °C to +70°C 8-MicroSO IMP707C/D 4.65 25 °C Dice IMP707EPA 4.65 –40°C to +85°C 8-Plastic DIP IMP707ESA 4.65 –40°C to +85°C 8-SO IMP708 Active LOW & HIGH Reset with Manual RESET IMP708CPA 4.40 0 °C to +70°C 8-Plastic DIP IMP708CSA 4.40 0 °C to +70°C 8-SO IMP708CUA 4.40 0 °C to +70°C 8-MicroSO IMP708C/D 4.40 25 °C Dice IMP708EPA 4.40 –40°C to +85°C 8-Plastic DIP IMP708ESA 4.40 –40°C to +85°C 8-SO IMP813L Active HIGH Reset, Watchdog Output and Manual RESET IMP813LCPA 4.65 0 °C to +70°C 8-Plastic DIP IMP813LCSA 4.65 0 °C to +70°C 8-SO IMP813LCUA 4.65 0 °C to +70°C 8-MicroSO IMP813LC/D 4.65 25 °C Dice IMP813LEPA 4.65 –40°C to +85°C 8-Plastic DIP IMP813LESA 4.65 –40°C to +85°C 8-SO

© 1999 IMP , Inc. 408-432-9100/www.impweb.com 3 IMP705/6/7/8, 8IMP705/6/7/8, 8 113L3L

Electrical Characteristics

Pin Terminal Voltage with Respect to Ground Rate of Rise at V (Derate 9 mW/°C above 70°C) (Derate 5.9 mW/°C above 70°C) (Derate 4.1 mW/°C above 70°C) Operating Temperature Range Note: 1. The input voltage limits on PFI and MR can be exceeded if the input current is less than 10mA. These are stress ratings only and functional operation is not implied. Parameter Symbol Conditions Min Typ Max Units Operating Voltage Range V CC IMP705/6/7/8C 1.2 5.5 V IMP813L 1.1 5.5 IMP705/6/7/8E, IMP813lE 1.2 5.5 Supply Current I CC IMP705C/706C/813LC 75 140 µA IMP705E, IMP706E, IMP813LE 75 140 IMP707C, IMP708C 50 140 IMP707E, IMP708E 50 140 RESET Threshold V RT IMP705, IMP707, IMP813L, Note 2 4.50 4.65 4.75 V IMP706, IMP708, Note 2 4.25 4.40 4.50 RESET Threshold Hysteresis Note 2 40 mV RESET Pulse Width t RS Note 2 140 200 280 ms MR Pulse Width t MR 0.15 µs MR to RESET Out Delay t MD Note 2 0.25 µs MR Input Threshold V IH 2.0 V VIL 0.8 MR Pull-up Current MR = 0V 100 250 600 µA RESET Output Voltage I SOURCE = 800µAV CC - 1.5V V ISINK = 3.2mA 0.4 IMP705/6/7/8, VCC = 1.2V, ISINK = 100µA 0.3 RESET Output Voltage IMP707/708/813L, I SOURCE = 800µAV CC - 1.5V V IMP707/708, ISINK = 1.2mA 0.4 IMP813L, ISINK = 3.2mA 0.4 IMP813L, VCC =1.2V, ISOURCE = 4µA 0.9 Watchdog Timeout Period t WD IMP705/706/813L 1.00 1.60 2.25 s WDI Pulse Width t WP VIL = 0.4V, VIH = 0.8VCC 50 ns WDI Input Threshold V IH IMP705/706/813L, VCC = 5V 3.5 V VIL 0.8 WDI Input Current IMP705/706/813L, WDI = V CC 50 150 µA IMP705/706/813L, WDI = 0V –150 – 50 WDO Output Voltage IMP705/706/813L, I SOURCE = 800µAV CC - 1.5V V IMP705/706/813L, ISINK = 1.2mA 0.4 PFI Input Threshold V CC = 5V 1.2 1.25 1.3 V PFI Input Current – 25 0.01 25 nA PFO Output Voltage I SOURCE = 800µAV CC - 1.5V V ISINK = 3.2mA 0.4 operating temperature range. Notes: 2. RESET (IMP705/6/7/8), RESET (IMP707/8, IMP813L)

4 408-432-9100/www.impweb.com © 1999 IMP , Inc. IMP705/6/7/8, 8IMP705/6/7/8, 8 113L3L Pin Descriptions Feature Summary Pin Number IMP705/706 IMP707/708 IMP813L DIP/SO MicroSO DIP/SO MicroSO DIP/SO MicroSO Name Function Manual RESET input. The active LOW input triggers a reset 1 3 1 3 1 3 MR pulse. A 250 µA pull-up current allows the pin to be driven by TTL / CMOS logic or shorted to ground with a switch. 242424 V CC +5V power supply input. 3 5 3 5 3 5 GND Ground reference for all signals. Power-fail voltage monitor input. With PFI less than 4 6 4 6 4 6 PFI 1.25V, PFO goes low. Connect PFI to ground or V CC when not used. 5 7 5 7 5 7 PFO Power-fail output. The output is active LOW and sinks current when PFI is less than 1.25V. Watchdog input. WDI controls the internal watchdog timer. A HIGH or LOW signal for 1.6sec at WDI allows the internal timer to run-out, setting WDO LOW. 68 —— 6 8 WDI The watchdog function is disabled by floating WDI or by connecting WDI to a high-impedance three-state buffer. The internal watchdog timer clears when: RESET is asserted; WDI is three-stated; or WDI sees a rising or falling edge. —— 6 —— — NC Not connected. Active-LOW reset output. Pulses LOW for 200ms when triggered, and stays low whenever VCC is below the reset threshold (IMP705: 4.65V, IMP705J: 4.00V, 7171 —— RESET IMP706: 4.40V). RESET remains LOW for 200ms after VCC rises above the RESET threshold or MR goes from LOW to HIGH. A watchdog timeout will not trigger RESET unless WDO is connected to MR. Watchdog output. WDO pulls LOW when the 1.6 sec internal watchdog timer times-out and does not go HIGH until the watchdog is cleared. In addition, when 82 —— 8 2 WDO V CC is below the reset threshold, WDO remains low. Unlike RESET, WDO does not have a minimum pulse width and as soon as V CC exceeds the reset threshold, WDO goes HIGH with no delay. —— 8 2 7 1 RESET Active-HIGH reset output . RESET is the inverse of RESET. The IMP813L has only a RESET output. IMP705 IMP706 IMP707 IMP708 IMP813L Power-fail detector I I III Brownout detection I I III Manual RESET input I I III Power-up/down RESET I I III Watchdog timer II I Active-HIGH RESET output III Active-LOW RESET output III I

known state or return the system to a known state. high approximately 200ms after crossing the threshold. initiated reset, the pulse will continue for a minimum of 140ms. and uncommitted output (PFO) and noninverting input (PFI). falls, PFI is reduced causing the PFO output to transit LOW. down in a controlled manner. Figure 1. WDI Three-state operation Figure 2. Watchdog Timing mechanical pushbutton switches. used when an active-HIGH RESET is required. state. WDO will remain LOW until activity is detected at WDI. counting, if WDI is floated or connected to a three-stated circuit. watchdog timer and initiate a new countdown sequence.

6 408-432-9100/www.impweb.com © 1999 IMP , Inc. IMP705/6/7/8, 8IMP705/6/7/8, 8 113L3L

Application Information

VCC < 1.1V GND RESET 100k/K57 705_06.eps VCC Ensuring That RESET is Valid Down to VCC = 0V When V CC falls below 1.1V , the IMP705-708 RESET output no longer pulls down; it becomes indeterminate. To avoid the possi- bility that stray charges build up and force RESET to the wrong state, a pull-down resistor should be connected to the RESET pin, thus draining such charges to ground and holding RESET low. The resistor value is not critical. A 100k Ω resistor will pull RESET to ground without loading it. Bi-directional Reset Pin Interfacing The IMP705/6/7/8 can interface with µP/µC bi-directional reset pins by connecting a 4.7k Ω resistor in series with the RESET output and the µP/µC bi-directional RESET pin. Power Supply IMP70x VCC GND GND RESET 4.7kΩ 705_08.eps Bi-directional I/O Pin (Example: 68HC11) BUF Buffered RESET µC or µP RESET Input Figure 3. Ensuring That RESET is Valid Down to VCC = 0V Figure 3. Bi-directional Reset Pin Interfacing

© 1999 IMP , Inc. 408-432-9100/www.impweb.com 7 IMP705/6/7/8, 8IMP705/6/7/8, 8 113L3L Monitoring Voltages Other Than VCC The IMP705-708 can monitor voltages other than V CC using the Power Fail circuitry. If a resistive divider is connected from the voltage to be monitored to the Power Fail input, PFI, the PFO (output) will go LOW if the divider voltage goes below its 1.25V reference. Should hysteresis be desired, connect a resistor (equal to approximately 10 times the sum of the two resistors in the divider) between the PFI and PFO pins. A capacitor between PFI and GND will reduce circuit sensitivity to input high-frequency noise. If it is desired to assert a RESET in addition to the PFO flag, this may be achieved by connecting the PFO output to MR. Monitoring a Negative Voltage The Power-Fail circuitry can also monitor a negative supply rail. When the negative rail is OK, PFO will be LOW, and when the negative rail is failing (not negative enough), PFO goes HIGH (the opposite of when positive voltages are monitored). To trigger a reset, these outputs need to be inverted: adding the resistors and transistor as shown achieves this. The RESET output will then have the same sense as for positive voltages: good = HIGH, bad = LOW. It should be noted that this circuit’s accuracy depends on the V CC line, the PFI threshold tolerance, and the resistors. IMP70x VCC = 5V VIN = 12V GND VCC RESET To Processor 12V Threshold ~10.87V PFO MR PFI 1M/K57 130k/K57 705_07.eps IMP70x +5V Negative Input Voltage GND VCC RESET PFO MR PFI RP RN 705_09.eps 5 1 25 1 25− = −.. RP V RN TRIP Figure 4. Monitoring Voltages Other Than VCC Figure 5. Monitoring a Negative Voltage

IMP705/6/7/8, 8IMP705/6/7/8, 8 113L3L 8 408-432-9100/www.impweb.com © 1999 IMP , Inc. E D eA eB C 0°–15° A e b2 b L A1 Plastic DIP (8-Pin)a.eps Plastic DIP (8-Pin)* L 0°– 8° C HE e D B A1 A SO (8-Pin).eps Inches Millimeters Min Max Min Max Plastic DIP (8-Pin) A2 0.115 0.195 2.92 4.95 b 0.014 0.022 0.36 0.56 b2 0.045 0.070 1.14 1.78 b3 0.030 0.045 0.80 1.14 D 0.355 0.400 9.02 10.16 E 0.300 0.325 7.62 8.26 E1 0.240 0.280 6.10 7.11 L 0.115 0.150 2.92 3.81 MicroSO (8-Pin) A1 0.0020 0.0059 0.050 0.15 A2 0.0295 0.0374 0.75 0.95 b 0.0098 0.0157 0.25 0.40 C 0.0051 0.0091 0.13 0.23 D 0.1142 0.1220 2.90 3.10 e 0.0256 BSC 0.65 BSC E 0.193 BSC 4.90 BSC E1 0.1142 0.1220 2.90 3.10 L 0.0157 0.0276 0.40 0.70 a0 ° 6° 0° 6° SO (8-Pin) A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 e 0.050 1.27 E 0.150 0.157 3.80 4.00 H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 D 0.189 0.197 4.80 5.00 SO (8-Pin)* MicroSO (8-Pin) e b D E1 E a L C D 0.10mm 0.004in A MicroSO (8-Pin).eps * JEDEC Drawing MS-001BA JEDEC Drawing MO-187AA * JEDEC Drawing MS-012AA Package Dimensions

IMP705/6/7/8, 8IMP705/6/7/8, 8 113L3L IMP , Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Tel: 800-438-3722 Fax: 408-434-0335 e-mail: info@impinc.com http://www.impweb.com The IMP logo is a registered trademark of IMP , Inc. All other company and product names are trademarks of their respective owners. © 1999 IMP, Inc. Printed in USA Publication #: 1017 Revision: A Issue Date: 08/17/99 Type: Preliminary