C1210 IMP | Alldatasheet
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Technical content
47© IMP, Inc. Process C1210 CMOS 1.2µ m Zero Threshold Devices N-Channel Transistor Symbol Minimum Typical Maximum Unit Comments Threshold Voltage VT N 0.55 0.75 0.95 V 100x1.2 µm Body Factor γN 0.34 V 1/2 100x1.2µm Conduction Factor βN 64 75 86 µA/V2 100x100µm Effective Channel Length LeffN 0.8 1.0 1.2 µm 100x1.2 µm Width Encroachment ΔW N 0.6 µm Per side Punch Through Voltage BVDSS N 9V Poly Field Threshold VoltageVTF P(N) 10 V P-Channel Transistor Symbol Minimum Typical Maximum Unit Comments Threshold Voltage VT P –0.7 –0.9 –1.1 V 100x1.2 µm Body Factor γP 0.38 V 1/2 100x1.2µm Conduction Factor βP 21 25 29 µA/V2 100x100µm Effective Channel Length LeffP 0.9 1.1 1.3 µm 100x1.2 µm Width Encroachment ΔW P 0.8 µm Per side Punch Through Voltage BVDSS P –9.0 V Poly Field Threshold VoltageVTF P(P) –10.0 V Zero Vt N-Channel Transis. Symbol Minimum Typical Maximum Unit Comments Threshold Voltage VT ZLN 0.00 0.15 0.30 V 100x100 µm Body Factor γZLN 0.348 V 1/2 100x100µm Conduction Factor βZLN 75 90 105 µA/V2 100x100µm Saturation Current I DSATZN 28 34 40 mA 100x1.5 µm Zero Vt P-Channel Transis. Symbol Minimum Typical Maximum Unit Comments Threshold Voltage VT ZLP –0.3 –0.1 0.1 V 100x100 µm Body Factor γZLP 0.36 V 1/2 100x100µm Conduction Factor βZLP 21 26 31 µA/V2 100x100µm Saturation Current I DSATZP –11 –15 –19 mA 100x1.5 µm
Electrical Characteristics
T=25oC Unless otherwise noted ISO 9001 Registered
48 C1210-4-98
Diffusion & Thin Films Symbol Minimum Typical Maximum Unit Comments Well (field) Sheet ResistanceρN-well(f) 0.6 1.0 1.3 K Ω /o n-well N+ Sheet Resistance ρN+ 20 35 50 Ω /o N+ Junction Depth x jN+ 0.35 µm P+ Sheet Resistance ρP+ 50 75 100 Ω /o P+ Junction Depth x jP+ 0.35 µm Gate Oxide Thickness T GOX 24 nm Field Oxide Thickness T FIELD 800 nm Gate Poly Sheet ResistanceρPOL Y2 15 22 30 Ω /o Bottom Poly Sheet Res. ρPOL Y1 35 Ω /o Metal-1 Sheet Resistance ρM1 50 m Ω /o Metal-2 Sheet Resistance ρM2 30 m Ω /o Passivation Thickness T PASS 200+900 nm oxide+nit. Capacitance Symbol Minimum Typical Maximum Unit Comments Gate Oxide C OX 1.28 1.38 1.58 fF/ µm 2 Metal-1 to Poly-1 C M1P 0.057 fF/ µm 2 Metal-1 to Silicon C M1S fF/µm 2 Metal-2 to Metal-1 C MM 0.035 fF/ µm 2 Poly-1 to Poly-2 C P1P2 0.69 0.86 1.03 fF/ µm 2
49© IMP, Inc. Process C1210 Starting Material EPI P <100> N+/P+ Width/Space 2.5/ 2.0 µm Starting Mat. Resistivity 7 - 8.5 Ω -cm N+ To P+ Space 9.0 µm Typ. Operating Voltage 5V Contact To Poly Space 1.5 µm Well Type N-well Contact Overlap Of Diffusion 1.0 µm Metal Layers 2 Contact Overlap Of Poly 1.0 µm Poly Layers 2 Metal-1 Overlap Of Contact 1.0 µm Contact Size 1.5x1.5 µm Metal-1 Overlap Of Via 1.0 µm Via Size 1.5x1.5 µm Metal-2 Overlap Of Via 1.0 µm Metal-1 Width/Space 2.5 / 1.5µm Minimum Pad Opening 65x65 µm Metal-2 Width/Space 2.5 / 1.5µm Minimum Pad-to-Pad Spacing 5.0 µm Gate Poly Width/Space 1.5 / 2.0µm Minimum Pad Pitch 80.0 µm Special Feature of C1210 Process: This process offers zero threshold n- and p-channel transistors in addition to normal threshold transistors of CMOS 1.2µm technology. Physical Characteristics Metal 2 Metal 1 SIO2 VIA Metal 1 LTO n+ n+ p n+ p+ p Field Oxide N-well contact Source Poly gate N-well Drain Contact Drain LDD Poly gate Sidewall spacer Source p– substrate contact Channel stop Sidewall spacer Bottom poly Contact Poly gate p+ substrate p–epi p+ p+ LTO 5.5 VGS = 4.0V VGS = 3.0V VGS = 2.0V VGS = 1.0V VGS = 0V ID vs VD, W/L = 20/1.2 .00 012345 Drain Current ID (mA) 0.55 mA /div Drain Voltage (v) VDS n-ch Transistor IV characteristics of a 20/1.2 device -3.0 VGS = –5.0V VGS = –4.0V VGS = –3.0V VGS = –2.0V VGS = –1.0V VGS = 0.0V ID vs VD, W/L = 20/1.2 .00 Drain Current ID (mA) 0.3 mA /div Drain Voltage (v) VDS p-ch Transistor IV characteristics of a 20/1.2 device Cross-Sectional view of the LVMOS process