IMP706TESA | DigiCamel IC Datasheet

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Document overview

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PDF pages: 8

Technical content

Applications

N Computers and controllers N CTI applications N Embedded controllers N Battery operated systems N Intelligent instruments N Wireless communication systems N PDAs and handheld equipment N Lower power, pin compatible replacements for Maxim MAX706P/R/S/T, MAX708R/S/T – 30% lower supply current:140µA vs. 200µA N Precision power supply monitor – 2.63V threshold (IMP706P/R, IMP708R) – 2.93V threshold (IMP706S, IMP708S) – 3.08V threshold (IMP706T, IMP708T) – New 4.00V threshold (IMP706J, IMP708J) N Debounced manual reset input N Auxiliary voltage monitor comparator – 1.25V threshold – Battery monitor/auxiliary supply monitor N Watchdog timer (IMP706P/R/S/T/J) – Watchdog can be disabled by floating WDI N 200ms reset time delay N Three reset signal options – Active HIGH: IMP706P – Active LOW: IMP706R/S/T/J – Active HIGH & LOW outputs: IMP708R/S/T/J N DIP, SO and MicroSO packages N Guaranteed RESET assertion to V CC = 1.1V Block Diagrams IMP706P/R/S/T/J, IMP708R/S/T/JIMP706P/R/S/T/J, IMP708R/S/T/J POWER MANAGEMENT 3/3.3/4.0V 3/3.3/4.0V µµP SuperP Supervisor Cirvisor Circuitscuits – Lo– Low supplw suppl y cury cur rrentent – W– Watcatchdog timerhdog timer – Br– Broownout detwnout det ectionection The IMP706P/R/S/T/J and IMP708R/S/T/J CMOS supervisor circuits monitor power-supply and battery voltage level, and µP/µC operation. A reset is generated when the supply drops below 2.63V (IMP706P/R, IMP708R), 2.93V (IMP706S, IMP708S), 3.08V (IMP706T, IMP708T) or 4.00 (IMP706J, IMP708J). The family offers several functional options. Each device generates a reset signal during power-up, power-down and during brownout conditions. In addition, the IMP706P/R/S/T/J feature a 1.6 second watchdog timer. The watchdog timer output will trigger a reset if connected to MR. Unlike competitive devices, floating the WDI input pin disables the watchdog timer. The IMP708R/S/T/J have both active-HIGH and active-LOW reset out- puts but no watchdog function. The IMP706P has the same pin-out and functions as the IMP706R but has an active-HIGH reset output. A versatile power-fail circuit, useful in checking battery levels and non-5V supplies, has a 1.25V threshold. All devices have a manual reset input. All devices are available in 8-pin DIP , SO and the compact MicroSO packages. The MicroSO package requires 50% less PC board area than the conventional SO package. RESET RESET VCC RESET Generator 2.63V (IMP708R) 2.93V (IMP708S) 3.08V (IMP708T) 4.00V (IMP708J) VCC + – MR IMP708R/S/T/J PFO GND 1.25V – +PFI 706P_02.eps 20kΩ 1.25V – MR WDI IMP706P/R/S/T/J WDO RESET (RESET) IMP706P PFO GND VCC 20kΩ RESET Generator 2.63V (IMP706P/R) 2.93V (IMP706S) 3.08V (IMP706T) 4.00V (IMP706J) VCC + – PFI Timebase Watchdog Timer Transition Detector 706P_01.eps

Ordering Information

IMP706P/R/S/T/J, IMP708R/S/T/JIMP706P/R/S/T/J, IMP708R/S/T/J IMP708R/S/T/J MR VCC GND PFI RESET RESET NC PFO IMP706P MR VCC GND PFI WDO RESET WDI PFO IMP706R/S/T/J MR VCC GND PFI WDO RESET WDI PFO IMP706P IMP706R/S/T/J (RESET) RESET (IMP706P) WDO MR VCC WDI PFO PFI GND IMP708R/S/T/J RESET RESET MR VCC NC PFO PFI GND 706P_03.eps DIP/SO MicroSO Operating Part Number Package Temperature Range Reset Threshold Reset Polarity Watchdog Timer IMP706PCPA 8-Plastic DIP 0 °C to +70°C 2.63 HIGH YES IMP706PCSA 8-SO 0 °C to +70°C 2.63 HIGH YES IMP706PCUA 8-MicroSO 0 °C to +70°C 2.63 HIGH YES IMP706PEPA 8-Plastic DIP –40°C to +85°C 2.63 HIGH YES IMP706PESA 8-SO –40°C to +85°C 2.63 HIGH YES IMP706RCPA 8-Plastic DIP 0 °C to +70°C 2.63 LOW YES IMP706RCSA 8-SO 0 °C to +70°C 2.63 LOW YES IMP706RCUA 8-MicroSO 0 °C to +70°C 2.63 LOW YES IMP706REPA 8-Plastic DIP –40°C to +85°C 2.63 LOW YES IMP706RESA 8-SO –40°C to +85°C 2.63 LOW YES IMP706SCPA 8-Plastic DIP 0 °C to +70°C 2.93 LOW YES IMP706SCSA 8-SO 0 °C to +70°C 2.93 LOW YES IMP706SCUA 8-MicroSO 0 °C to +70°C 2.93 LOW YES IMP706SEPA 8-Plastic DIP –40°C to +85°C 2.93 LOW YES IMP706SESA 8-SO –40°C to +85°C 2.93 LOW YES IMP706TCPA 8-Plastic DIP 0 °C to +70°C 3.08 LOW YES IMP706TCSA 8-SO 0 °C to +70°C 3.08 LOW YES IMP706TCUA 8-MicroSO 0 °C to +70°C 3.08 LOW YES IMP706TEPA 8-Plastic DIP –40°C to +85°C 3.08 LOW YES IMP706TESA 8-SO –40°C to +85°C 3.08 LOW YES IMP706JCPA 8-Plastic DIP 0 °C to +70°C 4.00 LOW YES IMP706JCSA 8-SO 0 °C to +70°C 4.00 LOW YES IMP706JCUA 8-MicroSO 0 °C to +70°C 4.00 LOW YES IMP706JEPA 8-Plastic DIP –40°C to +85°C 4.00 LOW YES IMP706JESA 8-SO –40°C to +85°C 4.00 LOW YES IMP708RCPA 8-Plastic DIP 0 °C to +70°C 2.63 Dual: HIGH & LOW NO IMP708RCSA 8-SO 0 °C to +70°C 2.63 Dual: HIGH & LOW NO IMP708RCUA 8-MicroSO 0 °C to +70°C 2.63 Dual: HIGH & LOW NO IMP708REPA 8-Plastic DIP –40°C to +85°C 2.63 Dual: HIGH & LOW NO IMP708RESA 8-SO –40°C to +85°C 2.63 Dual: HIGH & LOW NO IMP708SCPA 8-Plastic DIP 0 °C to +70°C 2.93 Dual: HIGH & LOW NO IMP708SCSA 8-SO 0 °C to +70°C 2.93 Dual: HIGH & LOW NO IMP708SCUA 8-MicroSO 0 °C to +70°C 2.93 Dual: HIGH & LOW NO IMP708SEPA 8-Plastic DIP –40°C to +85°C 2.93 Dual: HIGH & LOW NO IMP708SESA 8-SO –40°C to +85°C 2.93 Dual: HIGH & LOW NO IMP708TCPA 8-Plastic DIP 0 °C to +70°C 3.08 Dual: HIGH & LOW NO IMP708TCSA 8-SO 0 °C to +70°C 3.08 Dual: HIGH & LOW NO IMP708TCUA 8-MicroSO 0 °C to +70°C 3.08 Dual: HIGH & LOW NO IMP708TEPA 8-Plastic DIP –40°C to +85°C 3.08 Dual: HIGH & LOW NO IMP708TESA 8-SO –40°C to +85°C 3.08 Dual: HIGH & LOW NO IMP708JCPA 8-Plastic DIP 0 °C to +70°C 4.00 Dual: HIGH & LOW NO IMP708JCSA 8-SO 0 °C to +70°C 4.00 Dual: HIGH & LOW NO IMP708JCUA 8-MicroSO 0 °C to +70°C 4.00 Dual: HIGH & LOW NO IMP708JEPA 8-Plastic DIP –40°C to +85°C 4.00 Dual: HIGH & LOW NO IMP708JESA 8-SO –40°C to +85°C 4.00 Dual: HIGH & LOW NO

Pin Terminal Voltage with Respect to Ground Rate of Rise at V (Derate 9mW/°C above 70°C) (Derate 5.9mW/°C above 70°C) (Derate 4.1mW/°C above 70°C) Operating Temperature Range These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged time periods may affect device reliability. © 1999 IMP , Inc. 408-432-9100/www.impweb.com 3 IMP706P/R/S/T/J, IMP708R/S/T/JIMP706P/R/S/T/J, IMP708R/S/T/J Absolute Maximum Ratings

Electrical Characteristics

Unless otherwise noted, specifications are over the operating temperature range and V CC supply voltages are 2.7V to 5.5V (IMP706P , retemaraPl obmySs noitidnoCn iMp yTx aMs tinU egatloVgnitarepO egnaR V CC Cx807PMI,Cx607PMI Ex807PMI,Ex607PMI 1.1 2.1 5.5 5.5 V tnerruCylppuS V CC V6.3< I CC V=RM,Ex607PMI,Cx607PMI CC gnitaolFIDW,5 70 41 µA V=RM,Ex807PMI,Cx807PMI CC gnitaolFIDW,0 50 41 tnerruCylppuS V CC V5.5< I CC V=RM,Ex607PMI,Cx607PMI CC gnitaolFIDW,5 70 41 µA V=RM,Ex807PMI,Cx807PMI CC gnitaolFIDW,0 50 41 dlohserhTTESERV TR secivedRdnaP secivedS secivedT secivedJ 55.2 58.2 00.3 98.3 36.2 39.2 80.3 00.4 07.2 00.3 51.3 01.4 V dlohserhTTESER siseretsyH 04V m htdiWesluPTESERt SR V CC ,)secivedR/P,8/607PMI(V3= V CC )secivedT/S,8/607PMI(V3.3= V CC )secivedJ,8/607PMI(V4.4= 0410 020 82s m V CC V5=0 02 htdiWesluPRMt RM V<V5.4 CC V5.5<0 51s n V<V6.3 CC )secivedJ8/607PMI(V5.4< V )XAM(TSR V< CC )secivedT/S/R/P8/607PMI(V6.3< 005 yaleDtuOTESERotRMt DM V<V6.3 CC )secivedJ8/607PMI(V5.4< V )XAM(TSR V< CC )secivedT/S/R/P8/607PMI(V6.3< 057s n V<V5.4 CC V5.5<0 52 dlohserhTtupnIRMV HI V )XAM(TSR V< CC V5.4<V 7.0 CC V V LI V )XAM(TSR V< CC V5.4<6 .0 V HI V<V5.4 CC V5.5<0 .2 V LI V<V5.4 CC V5.5<8 .0 rotsiseRpu-lluPRMR P 010 20 4k Ω egatloVtuptuOTESER )secivedJ/T/S/RllA( V HO I ECRUOS 008= µ V<V5.4,A CC V5.5<V CC V5.1– V V LO I KNIS V<V5.4,Am2.3= CC V5.5<4 .0 V HO I ECRUOS 005= µ V,A )XAM(TSR V< CC V5.4<V 8.0 CC V LO I KNIS V,Am2.1= )XAM(TSR V< CC V5.4<3 .0 V LO I KNIS 05= µ V,A CC )secivedCx807PMI,Cx607PMI(V1.1=3 .0 I KNIS 001= µ V,A CC )secivedEx807PMI,Ex607PMI(V2.1=3 .0

IMP706P/R/S/T/J, IMP708R/S/T/JIMP706P/R/S/T/J, IMP708R/S/T/J 4 408-432-9100/www.impweb.com © 1999 IMP , Inc. Unless otherwise noted, specifications are over the operating temperature range and V CC supply voltages are 2.7V to 5.5V (IMP706P , Electrical Characteristics (cont.) retemaraPl obmySs noitidnoCn iMp yTx aMs tinU egatloVtuptuOTESER P607PMI V HO I ECRUOS 008= µ V<V5.4,A CC V5.5<V CC V5.1– V V LO I KNIS V<V5.4,Am2.3= CC V5.5< 4.0 V HO I ECRUOS 005= µ V,A )XAM(TSR V< CC V6.3<V 8.0 CC V LO I KNIS V,Am2.1= )XAM(TSR V< CC V6.3<3 .0 ,egatloVtuptuOTESER J/T/S/R807PMI V HO I ECRUOS 008= µ V<V5.4,A CC V5.5<V CC V5.1– V V LO I KNIS V<V5.4,Am2.3= CC V5.5< 4.0 V HO I ECRUOS 005= µ V,A )XAM(TSR V< CC V5.4<V 8.0 CC V LO I KNIS V,Am2.1= )XAM(TSR V< CC V5.4<3 .0 doirePtuoemiTgodhctaWt DW V CC )secivedR/P,607PMI(V3= V CC )secivedT/S,607PMI(V3.3= V CC )secivedJ,607PMI(V4.4= 0.16 .15 2.2s htdiWesluPIDWt PW V LI V,V4.0= HI V8.0= CC V, )XAM(TSR V< CC V5.4<0 01s n htdiWesluPIDWt PW V LI V,V4.0= HI V8.0= CC V<V5.4, CC V5.5<0 5s n dlohserhTtupnIIDWV HI V CC V5=5 .3V V LI 8.0 V HI V )XAM(TSR V< CC V5.4< V7.0 CC V LI 6.0 tnerruCtupnIIDW V=IDW CC ylnO607PMI, 050 51 µA tnerruCtupnIIDW ylnO607PMI,V0=IDW 051– 05– µA egatloVtuptuOODW V HO I ECRUOS 008= µ V<V5.4,A CC V5.5<V CC V5.1– V V LO I KNIS V<V5.4,Am2.1= CC V5.5<4 .0 V HO I ECRUOS 005= µ V,A )XAM(TSR V< CC V5.4< V8.0 CC V LO I KNIS 005= µ V,A )XAM(TSR V< CC V5.4<3 .0 dlohserhTtupnIIFPV secivedR/ProF.gnillafIFP CC T/SroF.V3= Vsecived CC VsecivedJroF.V3.3= CC .V4.4= 2.15 2.13 .1V tnerruCtupnIIFP 52– 10.05 2A n egatloVtuptuOOFPV HO I ECRUOS 008= µ V<V5.4,A CC V5.5< V CC V5.1– V V LO I KNIS V<V5.4,Am2.3= CC V5.5<4 .0 V HO I ECRUOS 005= µ V,A )XAM(SR V< CC V5.4<V 8.0 CC V LO I KNIS V,Am2.1= )XAM(SR V< CC V5.4<3 .0

IMP706P IMP706R/S/T/J IMP708R/S/T/J DIP/SO MicroSO DIP/SO MicroSO DIP/SO MicroSO Name Function Manual reset input. The active LOW input triggers a reset pulse. It is pulled HIGH by a 20k Ω pull-up 1 3 1 3 1 3 MR resistor. It is compatible with TTL/CMOS signals when VCC = 5V. It can be shorted to ground through a mechanical switch. Leave floating or connect to VCC if the function is not used. 242424 V CC Monitored power supply input. 3 5 3 5 3 5 GND Ground Power-fail input voltage monitor. With PFI less than 4 6 4 6 4 6 PFI 1.25V, PFO goes LOW. Connect PFI to ground when not used. Power-fail output. The output is active LOW and 5 7 5 7 5 7 PFO sinks current when PFI is less than 1.25V. If not used, leave the pin unconnected. Watchdog input. WDI controls the internal watchdog timer. A HIGH or LOW signal for 1.6 sec at WDI allows the internal timer to run-out, setting WDO low. 6868 —— WDI A rising or falling edge must occur at WDI within 1.6 seconds or WDO goes LOW. The watchdog function is disabled by floating WDI. The internal watchdog timer clears when: RESET is asserted; WDI is three-stated; or WDI sees a rising or falling edge. ———— 6 8 NC Not connected. Active-LOW reset output. Pulses LOW for 200ms when triggered, and stays LOW whenever V CC is —— 7 1 7 1 RESET below the reset threshold. RESET remains LOW for 200ms after VCC rises above the RESET threshold or MR goes from HIGH to LOW. A watchdog timeout will not trigger RESET unless WDO is connected to MR. Watchdog output. WDO goes LOW when the 1.6 second internal watchdog timer times-out and does not go HIGH until a transition occurs at WDI. In 8282 —— WDO addition, when V CC falls below the reset threshold, WDO goes LOW. Unlike RESET, WDO does not have a minimum pulse width and as soon as V CC exceeds the reset threshold, WDO becomes HIGH with no delay. 71 —— 8 2 RESET Active-HIGH reset output. RESET is the inverse of RESET. IMP706P/R/S/T/J, IMP708R/S/T/JIMP706P/R/S/T/J, IMP708R/S/T/J Pin Descriptions Feature Summary © 1999 IMP , Inc. 408-432-9100/www.impweb.com 5 IMP706P IMP706R IMP706S IMP706T IMP706J IMP708R IMP708S IMP708T IMP708J Power-fail detector IIIIII III Brownout detection IIIIII III Debounced manual RESET input IIIIII III Power-up/down RESET IIIIII III Watchdog timer IIIII Active-HIGH RESET I Active-LOW RESET IIII Active-LOW and HIGH RESETs II II

The RESET/RESET signals are designed to start or return a µP/µC to a known state. With V CC above 1.2V , RESET and RESET are guaranteed to be asserted. During a power-up sequence, the reset outputs remain asserted until the supply rises above the threshold level. The resets are deasserted approximately 200ms after crossing the threshold. In a brownout situation where V CC falls below the threshold level, the reset outputs are asserted. If a brownout occurs during an already initiated reset period, the reset period will extend for an additional reset period of 200ms. The IMP708 devices have dual reset outputs, one active LOW and one active HIGH. The IMP706P has a single active HIGH reset and the IMP706/R/S/T/J devices have an active LOW reset output. IMP Part RESET Polarity Threshold Watchdog Timer IMP706P HIGH 2.63V Yes IMP706R LOW 2.63V Yes IMP706S LOW 2.93V Yes IMP706T LOW 3.08V Yes IMP706J LOW 4.00V Yes IMP708R Both: HIGH & LOW 2.63V No IMP708S Both: HIGH & LOW 2.93V No IMP708T Both: HIGH & LOW 3.08V No IMP708J Both: HIGH & LOW 4.00V No Manual Reset (MR) The active-LOW manual reset input is pulled high by an internal 20kΩ pull-up resistor and can be driven low by CMOS/TTL logic or a mechanical switch to ground. An external debounce circuit is unnecessary since the 140ms minimum reset time will debounce mechanical pushbutton switches. The minimum MR input pulse IMP706P/R/S/T/J, IMP708R/S/T/JIMP706P/R/S/T/J, IMP708R/S/T/J 6 408-432-9100/www.impweb.com © 1999 IMP , Inc. VCC vRT WDO RESET MR tMD tRStRS tMR MR externally set low 706P_05.eps Watchdog Timing WDI Three-state operation tWD tWP tWD tWD 0V RESET triggered by MR WDI WDO RESET 706P_04.eps width is 0.5 µs with a 3V V CC input and 0.15 µs with a 5V V CC input. If not used, tie MR to V CC or leave floating. By connecting the watchdog output (WDO) and MR, a watchdog timeout forces a RESET to be generated. Watchdog Timer A watchdog timer available on the IMP706P/R/S/T/J monitors µP/µC activity. If activity is not detected within 1.6 seconds on the Watchdog Input (WDI), the internal timer puts the Watchdog Output (WDO) into a LOW state. WDO will remain LOW until activity is detected at WDI. The watchdog function is disabled, meaning it is cleared and not counting, if WDI is floated or connected to a three-stated circuit. The watchdog timer is also disabled if RESET is asserted. When RESET becomes inactive and the WDI input sees a high or low transition as short as 100ns (V CC = 2.7V)/50ns (V CC = 4.5V), the watchdog timer will begin a 1.6 second countdown. Additional transitions at WDI will reset the watchdog timer and initiate a new countdown sequence. WDO will also become LOW and remain so, whenever the supply voltage, V CC, falls below the device threshold level. WDO goes HIGH as soon as VCC transitions above the threshold. There is no minimum pulse width for WDO as there is for the RESET outputs. If WDI is float- ed, WDO essentially acts as a low supply voltage output indicator. Power-failure detection with auxiliary comparator All devices have an auxiliary comparator with 1.25V trip point. The output, PFO, is active LOW and the noninverting input is PFI. This comparator can be used as a supply voltage monitor with an external resistor voltage divider. As the monitored voltage level falls, PFI is reduced causing the PFO output to go LOW. Normally PFO interrupts the processor so the system can be shut down in a controlled manner. Detail Descriptions

Ensuring That RESET is Valid Down to VCC = 0V When V CC falls below 1.2V , the IMP706R/S/T/J and IMP708R/S/T/J RESET reset outputs no longer pull down; it becomes indeterminate. To avoid the possibility that stray charges could build up and force RESET to the wrong state, a pull-down resistor should be connected to the RESET pin, thus draining such charges to ground. The resistor value is not critical. A 100kΩ resis- tor will pull RESET to ground without loading it. Monitoring Voltages Other Than VCC The IMP706/708 can monitor voltages other than V CC using the Power Fail circuitry. If a resistive divider is connected from the voltage to be monitored to the PFI input, the PFO (output) will go LOW if the divider voltage goes below its 1.25V reference. Should hysteresis be desired, connect a resistor (equal to approximately 10 times the sum of the two resistors in the divider) between the PFI and PFO pins. A capacitor between PFI and GND will reduce circuit sensitivity to input high frequency noise. If it is desired to assert a reset in addition to the PFO flag, this may be achieved by connecting the PFO output to MR. IMP706P/R/S/T/J, IMP708R/S/T/JIMP706P/R/S/T/J, IMP708R/S/T/J © 1999 IMP , Inc. 408-432-9100/www.impweb.com 7 Bi-directional Reset Pin Interfacing The IMP706/8 can interface with µP/µC bi-directional reset pins by connecting a 4.7k Ω resistor in series with the RESET output and the µP/µC bi-directional reset pin. Supply Voltage IMP70x VCC GND GND RESET 4.7k/K57 706P_06.eps Bi-directional I/O Pin (Example: 68HC11) BUF Buffered RESET /K6D C or /K6D P RESET Input

Application Information

e b D E1 E a L C D 0.10mm 0.004in A MicroSO (8-Pin).eps MicroSO (8-Pin) Package Dimensions sehcnIs retemilliM niMx aMn iMx aM *)niP-8(OSorciM 1A0 200.09 500.00 50.05 1.0 2A5 920.04 730.05 7.05 9.0 b8 900.07 510.05 2.00 4.0 C1 500.01 900.03 1.03 2.0 D2 411.00 221.00 9.20 1.3 eC SB6520.0C SB56.0 EC SB391.0C SB09.4 1E2 411.00 221.00 9.20 1.3 L7 510.06 720.00 4.00 7.0 a °0 °6 °0 °6 3ta.a20t_P607 * JEDEC Drawing MO-187AA

IMP706P/R/S/T/J, IMP708R/S/T/JIMP706P/R/S/T/J, IMP708R/S/T/J IMP , Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Tel: 800-438-3722 Fax: 408-434-0335 e-mail: info@impinc.com http://www.impweb.com The IMP logo is a registered trademark of IMP , Inc. All other company and product names are trademarks of their respective owners. © 1999 IMP, Inc. Printed in USA Publication #: 1020 Revision: B Issue Date: 12/15/99 Type: Preliminary E D eA eB C 0°–15° A e b2 b L A1 Plastic DIP (8-Pin)a.eps Plastic DIP (8-Pin) L 0°– 8° C HE e D B A1 A SO (8-Pin).eps SO (8-Pin) sehcnIs retemilliM niMx aMn iMx aM )niP-8(OS A3 50.09 60.05 3.15 7.1 1A4 00.00 10.00 1.05 2.0 B3 10.00 20.03 3.01 5.0 C7 00.00 10.09 1.05 2.0 e0 50.07 2.1 E0 51.07 51.00 8.30 0.4 H8 22.04 42.00 8.50 2.6 L6 10.00 50.00 4.07 2.1 D9 81.07 91.00 8.40 0.2 *)niP-8(PIDcitsalP 2A5 11.05 91.02 9.25 9.4 b4 10.02 20.06 3.06 5.0 2b5 40.00 70.04 1.18 7.1 3b0 30.05 40.00 8.04 1.1 D5 53.00 04.02 0.96 1.01 E0 03.05 23.02 6.76 2.8 1E0 42.00 82.00 1.61 1.7 L5 11.00 51.02 9.21 8.3 3ta.b20t_P607 JEDEC Drawing MS-112AA * JEDEC Drawing MS-001BA Package Dimensions

Product Information

IMP706TESA specifications and overview.

Summary

3/3.3/4.0V 關P SUPERVISOR CIRCUITS

Description

3/3.3/4.0V 關P SUPERVISOR CIRCUITS

Source title IMP706TESA Datasheet(PDF) - IMP, Inc

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