IMP6303

IMP6303 IMP | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 8

Technical content

© 2001 IMP , Inc. 408-432-9100/www.impweb.com 1 IMP6303IMP6303 POWER MANAGEMENT Key Features

Applications

N Battery operated systems N Intelligent instruments N Wireless communication systems N PDAs and handheld equipment N Monitor 4.0V supply N 140ms min. reset pulse width N Active-low reset valid with 1.1V supply N Small 3-pin SOT-23 package N Small 3-pin TO-92 package N Small 5-pin SOT-23-5 package N No external components N Specified over full temperature range — –40°C to 105°C Block Diagrams IMP6303 VCC VCC VCC GND GND RESET (RESET) 6303_01.eps µP RESET Input The IMP6303 is a 4.0V power supply supervisor circuits optimized for low- power microprocessor (µP), microcontroller (µC) and digital systems. A reset signal is issued if the power supply voltage drops below a preset reset threshold and is asserted for at least 140ms after the supply has risen above the reset threshold. The IMP6303 has an active-low RESET output that is guaranteed to be in the correct state for V CC down to 1.1V . The reset comparator is designed to ignore fast transients on VCC. Low supply current makes the IMP6303 ideal for use in portable and battery operated equipment. The IMP6303 is available in a compact 3-pin SOT23, TO-92 and 5 pin SOT23-5 packages.

2 408-432-9100/www.impweb.com © 2001 IMP , Inc. Ὂ7S

Ordering Information

(RESET) RESET 6303_02.eps SOT-23 6303_06.eps 123 VCC GND IMP6303 RESET (RESET) TO-92 IMP6303 NC NC

1 VCC5

6303_07.eps RESET (RESET) SOT-23-5 Package Marking2 Part Number1 Reset Threshold (V) Temperature Range Pin-Package (XX Lot Code) IMP6303 Active LOW Reset IMP6303JEUR-T 4.00 –40°C to +105°C 3-SOT23 CWXX Notes: 1. Tape and Reel packaging is indicated by the -T designation. 2. Devices may also be marked with full part number: 6303L, 6303M etc. XX refers to lot.

Related Products

Max. Supply Current 15µA 15µA 15µA Package Pins 3 3 5 Package Type SOT-23 TO-92 SOT-23-5 Active-LOW RESET output II I

© 2001 IMP , Inc. Microprocessor Supervisor 3 Parameter Symbol Conditions Min Typ Max Units Input Voltage (VCC) Range V CC TA = 0°C to 70°C 1.1 5.5 V TA = –40°C to 105°C 1.2 5.5 Supply Current I CC TA = –40°C to 85°C V CC < 4.0V 9 15 µA Reset Threshold V TH TA = 25°C 3.93 4.00 4.06 TA = –40°C to 85°C 3.89 4.10 TA = 85°C to 105°C 3.80 4.20 Reset Threshold Stability 30 ppm/°C VCC to Reset Delay V CC = VTH to VTH - 100mV 20 µs Reset Active Timeout Period V OL TA = –40°C to 85°C 140 240 560 ms TA = 85°C to 105°C 100 840 Low RESET Output Voltage V OL VCC = VTH min., ISINK = 1.2mA 0.3 V VCC = VTH min., ISINK = 3.2mA 0.4 VCC > 1.1V, ISINK = 50µA 0.3 High RESET Output Voltage V OH VCC > VTH max., ISOURCE = 500µA 0.8V CC V VCC > VTH max., ISOURCE = 800µA V CC -1.5 Absolute Maximum Ratings Pin Terminal Voltage with Respect to Ground Rate of Rise at V (Derate 4mW/°C above 70 °C)

Electrical Characteristics

These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged time periods may affect device reliability Unless otherwise noted VCC is over the full voltage range, T A = –40°C to 105°C. Typical values at TA = 25°C, VCC = 5V for L/M/J devices. Notes: 1. Production testing done at TA = 25°C. Over-temperature specifications guaranteed by design only. 2. RESET output is active LOW for the IMP6303.

240ms typical reset timeout period (140ms minimum) after V CC exceeds the threshold. VCC Power supply input voltage. CC has risen above the threshold. Figure 1. Reset Timing Diagram

6 408-432-9100/www.impweb.com © 2001 IMP , Inc. Ὂ7S Package Dimensions e D b SOT -23 (3-Pin).eps L CA A2 E1 E Plastic SOT-23 (3-Pin) TO-92.eps I Bottom View1 H B C G M L D F D Section A-A Section A-A E J A K Plastic TO-92 (3-Pin) A A2 C E e D b L L1 SOT -23 (5-Pin).eps Plastic SOT-23 (5-Pin) sehcnIs retemilliM niMx aMn iMx aM )niP-3(*32-TOScitsalP A5 30.04 40.09 8.02 1.1 1A4 000.04 00.01 0.00 1.0 2A5 30.00 40.08 8.02 0.1 b2 10.00 20.00 3.00 5.0 c3 00.08 00.08 0.00 2.0 D0 11.00 21.00 8.24 0.3 E3 80.04 01.00 1.24 6.2 1E7 40.05 50.00 2.10 4.1 eC SB73.0C SB59.0 1eC SB70.0C SB09.1 L6 10.04 20.00 4.00 6.0 1LF ER120.0F ER45.0 ø° 0 °8 °0 °8 )niP-3(29-OT A5 71.05 91.05 4.45 9.4 B0 71.02 91.02 3.46 9.4 C0 05.00 16.00 7.219 4.51 D6 10.02 20.06 04.09 55.0 E5 90.05 01.01 4.27 6.2 F5 40.00 6.04 1.12 5.1 G5 4.00 60.04 1.12 5.1 H5 80.05 90.06 1.21 4.2 I0 31.05 51.00 3.34 9.3 J4 10.00 20.05 3.01 5.0 K3 90.05 11.06 3.22 9.2 L °54 °06 °54 °06 Ml acipyT811.00 0.3 )niP-5(**32-TOScitsalP A7 30.07 50.05 9.05 4.1 1A1 00.05 00.05 0.05 1.0 2A5 30.00 50.00 9.00 3.1 b1 10.09 10.00 3.00 5.0 c3 00.07 00.08 0.00 2.0 D9 01.07 11.00 8.20 0.3 E1 01.07 11.00 6.20 0.3 1E8 50.06 60.00 5.10 7.1 eC SB730.0C SB59.0 1eC SB470.0C SB09.1 L3 10.01 20.05 3.05 5.0 1LF ER200.0F ER06.0 ∅ °0 °8 °0 °8 spe.40t_1181

© 2001 IMP , Inc. Microprocessor Supervisor 7

IMP , Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Fax: 408-434-5904 e-mail: info@impinc.com http://www.impweb.com The IMP logo is a registered trademark of IMP , Inc. All other company and product names are trademarks of their respective owners. © 2001 IMP, Inc. Printed in USA Publication #: 1023 Revision: A Issue Date: 10/26/01 Type: Preliminary IMP6303IMP6303