IMP5115 IMP | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 6
Technical content
N Ultra-Fast response for Fast-20 SCSI applications N 35MHz channel bandwidth N 3.3V operation N Less than 3pF output capacitance N 375µA Sleep-mode current N Thermally self limiting N No external compensation capacitors N Implements 8-bit or 16-bit (wide) applications N Compatible with active negation drivers (60mA/channel) N Compatible with passive and Active terminations N Approved for use with SCSI 1, 2, 3 and UltraSCSI N Hot swap compatible N Pin-for-pin compatible with DS21S07A/2105 Block Diagrams Current Biasing Circuit Thermal Limiting Circuit 24mA Current Limiting Circuit Term Power DATA OUTPUT PIN DB (0) 1 of 9 Channels DISABLE PIN 1.4V 2.85V 5115_01.eps 9-Line SCSI T9-Line SCSI Tererminatminatoror – 35MHz Channel Bandwidt– 35MHz Channel Bandwidthh The IMP5115 SCSI terminator is part of IMP's family of high-perfor- mance, adaptive, non-linear mode SCSI products, which are designed to deliver true UltraSCSI performance in SCSI applications. The low voltage BiCMOS architecture employed in its design offers performance superior to older linear passive and active techniques. IMP's SCSI termination architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible — typically 35MHz, which is 100 times faster than the older linear regulator/terminator approach used by other manufacturers. Products using this older linear regulator approach have bandwidths which are dominated by the output capacitor and which are limited to 500KHz (see further discussion in the Functional Description section). This new architecture also eliminates the output compensation capacitor required in earlier terminator designs. Each is approved for use with SCSI-1, -2, -3, UltraSCSI and beyond — providing the highest performance alternative available today. Another key improvement offered by the IMP5115 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as the use of improper cable lengths and impedances. Frequently, this situation is not controlled by the peripheral or host designer and, when problems occur, they are the first to be made aware of the problem. The IMP5115 architecture is much more tolerant of marginal system integrations. Recognizing the needs of portable and configurable peripherals, the IMP5115 has a TTL compatible sleep/disable mode. Quiescent current is typically 375µA in this mode, while the output capacitance is also less than 3pF. The obvious advantage of extended battery life for portable systems is inherent in the product's sleep-mode feature. Additionally, the disable function permits factory-floor or production- line configurability, reducing inventory and product-line diversity costs. Field configurability can also be accom- plished without physically removing components which, often times results in field returns due to mishandling. Reduced component count is also inherent in the IMP5115 architecture. Traditional termination techniques require large stabilization and transient protection capacitors of up to 20µF in value and size. The IMP5115 architecture does not require these components, allowing all the cost savings associated with inventory, board space, assembly, reliability, and component costs. 1IMP5IMP 5111155 © 2000 IMP, Inc. Data Communications 1 DATA COMMUNICATIONS
2 408-432-9100/www.impweb.com © 2000 IMP , Inc. Pin Configuration
Ordering Information
16 DISABLE
5115__02.eps IMP5115 8GND 1TERM POWER 9N C 7NC 10 D5 6D4 11 D6 5D3 12 D7 4D2 13 D8 3D1 14 NC 2D0 15 NC 5115__02a.eps IMP5115 SO-16 SOWB-16 1TERM POWER 7D4 14 D6 8HEAT SINK/GND 13 D5 9NC 12 HEAT SINK/GND
10 GND 11 NC
20 DISABLE
5115_02b.eps IMP5115 TSSOP-20 r e b m u N t r aPe g n a R e r u t a r e p m eTe g a k c a P D C 5 1 1 5 P MI0 ° 5 2 1 o t C°CO S c i t s a l P n i p - 6 1 T D C 5 1 1 5 P MI0 ° 5 2 1 o t C°CO S c i t s a l P n i p - 6 1 , l e e R d n a e p a T W D C 5 1 1 5 P MI0 ° 5 2 1 o t C°CB W O S c i t s a l P n i p - 6 1 T W D C 5 1 1 5 P MI0 ° 5 2 1 o t C°CB W O S c i t s a l P n i p - 6 1 , l e e R d n a e p a T P W P C 5 1 1 5 P MI0 ° 5 2 1 o t C°CP O S S T c i t s a l P n i p - 0 2 T P W P C 5 1 1 5 P MI0 ° 5 2 1 o t C°CP O S S T c i t s a l P n i p - 0 2 , l e e R d n a e p a T 3 t a . 1 0 t _ 5 1 1 5 Thermal Data Note: 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. D Package: Thermal Resistance Junction-to-Ambient, θ Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the ambient airflow is assumed. 1IMP5IMP 5111155
© 2000 IMP, Inc. Data Communications 3 Recommended Operating Conditions2 r e t e m a r aPl o b m ySn iMp yTx aMs t i n U e g a t l o V r w P m r eTV M R E T 0 .45 .5V e g a t l o V t u p n I e l b a n E l e v e L h g iHV H I 2V M R E T V e g a t l o V t u p n I e l b a s i D l e v e L w oLV L I 08 .0V e g n a R e r u t a r e p m e T n o i t c n u J g n i t a r e p O05 21C ° . l a n o i t c n u f s i e c i v e d e h t h c i h w r e v o e g n a r e h t e t a c i d n i s n o i t i d n o c g n i t a r e p o d e d n e m m o c e R . 2 : e t o N s p e . 2 0 t _ 5 1 1 5
Electrical Characteristics
Unless otherwise specified, these specifications apply at an ambient operating temperature of T A = 25°C. TermPwr = 4.75V . Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature. r e t e m a r aPl o b m ySs n o i t i d n oCn iMp yTx aMs t i n U e g a t l o V h g i H t u p t uOV T U O 5 6 .25 8 .2V t n e r r u C y l p p u S r w P m r eTI C C n e p O = s e n i l a t a d l lA6 9 A m V 5 . 0 = s e n i l a t a d l lA5 125 2 2 V 8 . 0 < n i P e l b a s iD5 7 3 µA t n e r r u C t u p t uOI T U O V T U O V 5 . 0=1 2– 3 2– 4 2– A m t n e r r u C t u p n I e l b a s iDI N I V 5 7 . 4 = n i P e l b a s iD0 1A n V 0 = n i P e l b a s iD0 9– µA t n e r r u C e g a k a e L t u p t uOI L O V , V 8 . 0 < n i P e l b a s i DO V 5 . 0=0 1A n e d o M e l b a s i D n i e c n a t i c a p aCC T U O V T U O z H M 1 = y c n e u q e r F , V 0=3 F p h t d i w d n a B l e n n a hCW B5 3z H M l e n n a h C r e p , t n e r r u C k n i S n o i t a n i m r eTI K N I SV T U O V 4=0 6A m s p e . 3 0 t _ 5 1 1 5 1IMP5IMP 5111155
4 408-432-9100/www.impweb.com © 2000 IMP , Inc.
Application Information
IMP5115 Maximizes Line Current Cable transmission theory suggests to optimize signal speed and quality, the termination should act both as an ideal voltage refer- ence when the line is released (deasserted) and as an ideal current source when the line is active (asserted). Common active terminators which consist of linear regulators in series with resis- tors (typically 110 Ω ) are a compromise. With coventional linear terminators as the line voltage increases the amount of current decreases linearly by the equation; The IMP5115, with its unique new architecture, applies the maxi- mum amount of current regardless of line voltage until the termination high threshold (2.85V) is reached. Acting as a near ideal line terminator, the IMP5115 closely repro- duces the optimum case when the device is enabled. To enable the device the Disable pin must be driven LOW. When enabled, quiescent current is 6mA and the device will respond to line demands by delivering 24mA on assertion and by imposing 2.85V on de-assertion. Disable/Sleep Mode Disable mode places the device in a sleep state, where quiescent current typically 375µA. When disabled, all outputs are in a high impedance state. Sleep mode can be used for power conservation or to remove the terminator from the SCSI chain. An additional feature of the IMP5115 are their compatibility with active negation drivers. VV R IREF LINE−() = . Figure 3. 5115_03.eps
1 Meter, AWG 28
Figure 1. Receiving Waveform – 20MHz Figure 2. Driving Waveform – 20MHz Table 1. Power Up/ Power Down Function Table
© 2000 IMP , Inc. Data Communications 5 s e h c nIs r e t e m i l l i M n iMx aMn iMx a M * ) n i P - 6 1 ( O S A3 5 0 .09 6 0 .05 3 .15 7 . 1 1A4 0 0 .00 1 0 .00 1 .05 2 . 0 B4 1 0 .08 1 0 .05 3 .06 4 . 0 C7 0 0 .00 1 0 .09 1 .05 2 . 0 D5 8 3 .04 9 3 .08 7 .91 0 . 0 1 E0 5 1 .08 5 1 .01 8 .31 0 . 4 eC S B 0 5 0 .0C S B 7 2 . 1 H8 2 2 .04 4 2 .09 7 .50 2 . 6 L0 2 0 .00 3 0 .01 5 .07 7 . 0 ) n i P - 6 1 ( B W O S A3 9 0 .04 0 1 .05 3 .25 6 . 2 1A4 0 0 .02 1 0 .00 1 .00 3 . 0 B0 1 0 .08 1 0 .05 2 .06 4 . 0 C9 0 0 .03 1 0 .03 2 .02 3 . 0 D — 0 2 4 . 0 — 7 6 . 0 1 E5 9 2 .05 0 3 .09 4 .75 7 . 7 eC S B 0 5 0 .0C S B 7 2 . 1 H4 0 4 .09 1 4 .06 2 . 015 6 . 0 1 L5 2 0 .05 3 0 .04 6 .09 8 . 0 ) n i P - 0 2 ( P O S S T A8 6 0 .08 7 0 .03 7 .19 9 . 1 B9 0 0 .05 1 0 .05 2 .08 . 0 C5 0 0 .08 0 0 .03 1 .02 2 . 0 D3 0 3 .01 1 3 .00 7 .70 9 . 7 E5 0 2 .02 1 2 .00 2 .58 3 . 5 FC S B 5 2 0 .0C S B 7 2 . 1 G2 0 0 .08 0 0 .05 0 .01 2 . 0 H4 6 0 .02 7 0 .03 6 .13 8 . 1 L5 2 0 .07 3 0 .05 6 .05 9 . 0 M °0 °8 °0 °8 P1 0 3 .01 1 3 .05 6 .70 9 . 7 C A 2 1 0 - S M g n i w a r D C E D E J * 3 t a . 5 0 t _ 5 1 1 5 HE eB D A L M C 16-Pin (SO).eps SO (16-Pin) H E eB D A L M C 16-Pin (SOWB).eps SOWB (16-Pin) 3 2 1 EP D SEATING PLANE B G A H F E L 20-Pin (TSSOP).eps C M TSSOP (20-Pin) Package Dimensions 1IMP5IMP 5111155
2002 © IMP, Inc. Printed in USA Publication #: 7006 Revision: C Issue Date: 08/19/02 Type: Product 1IMP5IMP 5111155 IMP , Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Fax: 408-432-1085 e-mail: info@impinc.com http://www.impweb.com The IMP logo is a registered trademark of IMP , Inc. All other company and product names are trademarks of their respective owners.