IMP5111CPWPT

IMP5111 IMP | Alldatasheet

Document overview

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Technical content

N Ultra-Fast response for Fast-20 SCSI applications N 35MHz channel bandwidth N 3.3V operation N Less than 3pF output capacitance N Sleep-mode current less than 275µA N Thermally self limiting N No external compensation capacitors N Implements 8-bit or 16-bit (wide) applications N Compatible with active negation drivers (60mA/channel) N Compatible with passive and active terminations N Approved for use with SCSI 1, 2, 3 and UltraSCSI N Hot swap compatible N Pin-for-pin compatible with LX5211 and UC5606 (IMP5111) N Pin-for-pin compatible with LX5212 and UC5603/5613/5614 (IMP5112) Block Diagrams Current Biasing Circuit Thermal Limiting Circuit 24mA Current Limiting Circuit Term Power DATA OUTPUT PIN DB (0) 1 of 9 Channels DISCONNECT (IMP5111) DISCONNECT (IMP5112) 1.4V 2.85V 5111/5112_01.eps 9-Line SCSI T9-Line SCSI Tererminatminatoror – 35MHz Channel Bandwidt– 35MHz Channel Bandwidthh The 9-channel IMP5111/5112 SCSI terminator is part of IMP's family of high-performance SCSI terminators that deliver true UltraSCSI per- formance. The BiCMOS design offers superior performance over first generation linear regulator/resistor based terminators. IMP's new architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible - typically 35MHz, which is 100 times faster than the older linear regulator termi- nator approach. The bandwidth of terminators based on the older regulator/resistor terminator architecture is limited to 500kHz since a large output stabilization capacitor is required. The IMP architecture eliminates the external output compensation capacitor and the need for transient output capacitors while maintaining pin compatibility with first generation designs. Reduced component count is inherent with the IMP5111/5112. The IMP5111/5112 architecture tolerates marginal system designs. A key improvement offered by the IMP5111/5112 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as improper cable lengths and impedance. Frequently, this situation is not controlled by the peripheral or host designer. For portable and configurable peripherals, the IMP5111/5112 can be placed in a sleep mode with a disconnect signal. Quiescent current is less than 275 µA when disabled. When disabled, the outputs are in a high impedance state with output capacitance less than 3pF. IMP5IMP5 11111/51/5 111122 D ATA C OMMUNICATIONS IMP5IMP5 11111/51/5 111122 D ATA C OMMUNICATIONS Daily Silver IMP www.ds-imp.com.cn

Ordering Information

7 T1 10 T4

6 DISCONNECT* 11 V

5 GND 12 HEAT SINK/GND

4 HEAT SINK/GND 13 HEAT SINK/GND

3 T9 14 NC

2 T8 15 T5

5111/5112__02.eps IMP5111 IMP5112 * DISCONNECT (IMP5111) DISCONNECT (IMP5112) SO-16 * DISCONNECT (IMP5111) DISCONNECT (IMP5112) 12 T2 1 T7 13 T3

7 HEAT SINK/GND 18 HEAT SINK/GND

8 HEAT SINK/GND 17 HEAT SINK/GND

9 HEAT SINK/GND 16 NC

10 DISCONNECT* 15 V

11 T1 14 T4

6 HEAT SINK/GND 19 HEAT SINK/GND

5 GND 20 HEAT SINK/GND

4 NC 21 NC

3 T9 22 NC

2 T8 23 T5

5111/5112_02a.eps IMP5111 IMP5112 TSSOP-24 r e b m u N t r aPe g n a R e r u t a r e p m eTe g a k c a P P D C 1 1 1 5 P MI0 ° 5 2 1 o t C°CO S c i t s a l P n i p - 6 1 T P D C 1 1 1 5 P MI0 ° 5 2 1 o t C°CO S c i t s a l P n i p - 6 1 , l e e R d n a e p a T P W P C 1 1 1 5 P MI0 ° 5 2 1 o t C°CP O S S T c i t s a l P n i p - 4 2 T P W P C 1 1 1 5 P MI0 ° 5 2 1 o t C°CP O S S T c i t s a l P n i p - 4 2 , l e e R d n a e p a T P D C 2 1 1 5 P MI0 ° 5 2 1 o t C°CO S c i t s a l P n i p - 6 1 T P D C 2 1 1 5 P MI0 ° 5 2 1 o t C°CO S c i t s a l P n i p - 6 1 , l e e R d n a e p a T P W P C 2 1 1 5 P MI0 ° 5 2 1 o t C°CP O S S T c i t s a l P n i p - 4 2 T P W P C 2 1 1 5 P MI0 ° 5 2 1 o t C°CP O S S T c i t s a l P n i p - 4 2 , l e e R d n a e p a T 3 t a . 1 0 t _ 2 1 1 5 / 1 1 1 5 Thermal Data Operating Junction Temperature Note: 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Thermal Resistance Junction-to-Leads, θ JL Thermal Resistance Junction-to-Ambient, θ JA Thermal Resistance Junction-to-Leads, θ JL Thermal Resistance Junction-to-Ambient, θ JA Junction Temperature Calculation: T J = T A + (P D x θ JA The θ JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the ambient airflow is assumed. IMP5IMP5 11111/51/5 111122 IMP5IMP5 11111/51/5 111122 www.ds-imp.com.cn Daily Silver IMP

Recommended Operating Conditions r e t e m a r aPl o b m ySn iMp yTx aMs t i n U e g a t l o V r w P m r eTV M R E T 3 .35 .5V e g a t l o V t u p n I e l b a n E l e v e L h g iH1 1 1 5 P MIV H I M R E T V 2 1 1 5 P MI0 8 . 0 e g a t l o V t u p n I e l b a s i D l e v e L w oL1 1 1 5 P MIV L I 08 .0V 2 1 1 5 P MI2 V M R E T e g n a R e r u t a r e p m e T n o i t c n u J g n i t a r e p O05 21C ° . l a n o i t c n u f s i e c i v e d e h t h c i h w r e v o e g n a r e h t e t a c i d n i s n o i t i d n o c g n i t a r e p o d e d n e m m o c e R . 2 : e t o N s p e . 2 0 t _ 2 1 1 5 / 1 1 1 5

Electrical Characteristics

Unless otherwise specified, these specifications apply at an ambient operating temperature of T A = 25°C. TermPwr = 4.75V . Low duty cycle pulse testing techniques are used which maintain junction and case temperatures equal to the ambient temperature. r e t e m a r aPl o b m ySs n o i t i d n oCn iMp yTx aMs t i n U e g a t l o V h g i H t u p t uOV T U O 5 6 .25 8 .2V t n e r r u C y l p p u S r w P m r eTI C C n e p O = s e n i l a t a d l lA6 9 A m V 5 . 0 = s e n i l a t a d l lA5 125 2 2 1 1 1 5 P MIT C E N N O C S IDV 8 . 0 < n iP5 7 2 µA 2 1 1 5 P MIT C E N N O C S IDV 0 . 2 > n iP5 7 2 t n e r r u C t u p t uOI T U O V T U O V 5 . 0=1 2– 3 2– 4 2– A m T C E N N O C S IDt n e r r u C t u p nI1 1 1 5 P MII N I T C E N N O C S IDV 5 7 . 4 = n iP0 1A n T C E N N O C S IDV 0 = n iP0 9– µA T C E N N O C S IDt n e r r u C t u p nI2 1 1 5 P MII N I T C E N N O C S IDV 0 = n iP0 9– µA T C E N N O C S IDV 5 7 . 4 = n iP0 1A n t n e r r u C e g a k a e L t u p t uO1 1 1 5 P MII L O T C E N N O C S IDV , V 8 . 0 < n i P O V 5 . 0=0 1A n 2 1 1 5 P MIT C E N N O C S IDV , V 0 . 2 > n i P O V 5 . 0=0 1 n i e c n a t i c a p aCT C E N N O C S IDe d oMC T U O V T U O z H M 1 = y c n e u q e r F , V 0=3 F p h t d i w d n a B l e n n a hCW B5 3z H M l e n n a h C r e p , t n e r r u C k n i S n o i t a n i m r eTI K N I S V T U O V 4=0 6A m s p e . 3 0 t _ 2 1 1 5 / 1 1 1 5 IMP5IMP5 11111/51/5 111122 IMP5IMP5 11111/51/5 111122 Daily Silver IMP

Application Information

IMP5111/IMP5112 Maximizes Line Current Cable transmission theory suggests to optimize signal speed and quality, the termination should act both as an ideal voltage refer- ence when the line is released (deasserted) and as an ideal current source when the line is active (asserted). Common active terminators which consist of linear regulators in series with resis- tors (typically 110 Ω ) are a compromise. With coventional linear terminators as the line voltage increases the amount of current decreases linearly by the equation; The IMP5111/5112, with their unique architecture, applies the maximum amount of current regardless of line voltage until the termination high threshold (2.85V) is reached. Disable /Sleep Mode The IMP5111 has an active LOW disconnect pin, and the IMP5112 has an active HIGH disconnect pin. The disable mode is entered if the disconnect pin on either device is left open. When disabled the termination lines are in a high impedance state, and the power supply current drops to 275µA typically. The disable mode can be used to save power or completely eliminate the terminator from the SCSI bus. Disabled terminators appear as distributed capacitance on the bus. The IMP5111/5112 have been optimized to have only 3pF of capacitance per output when in the disabled mode. The IMP5111/5112 are compatible with active negation drivers. The devices will handle up to 60mA of sink current for drivers which exceed the 2.85V output high level VV R I REF LINE = . Figure 3. 5111/5112_03.eps

1 Meter, AWG 28 IMP5111

Figure 1. Receiving Waveform – 20MHz Figure 2. Driving Waveform – 20MHz Table 1. Power Up/ Power Down Function Table

s e h c nIs r e t e m i l l i M n iMx aMn iMx a M * ) n i P - 6 1 ( O S A3 5 0 .09 6 0 .05 3 .15 7 . 1 1A4 0 0 .00 1 0 .00 1 .05 2 . 0 B4 1 0 .08 1 0 .05 3 .06 4 . 0 C7 0 0 .00 1 0 .09 1 .05 2 . 0 D5 8 3 .04 9 3 .08 7 .91 0 . 0 1 E0 5 1 .08 5 1 .01 8 .31 0 . 4 eC S B 0 5 0 .0C S B 7 2 . 1 H8 2 2 .04 4 2 .09 7 .50 2 . 6 L6 1 0 .00 5 0 .00 4 .07 2 . 1 M °0 °8 °0 °8 ) n i P - 4 2 ( P O S S T A2 3 0 .01 4 0 .00 8 .05 0 . 1 B7 0 0 .02 1 0 .09 1 .00 3 . 0 C5 3 0 0 .01 7 0 0 .09 0 .00 8 1 . 0 D3 0 3 .01 1 3 .00 7 .70 9 . 7 E9 6 1 .06 7 1 .00 3 .48 4 . 4 FC S B 5 2 0 .0C S B 5 6 . 0 G2 0 0 .05 0 0 .05 0 .05 1 . 0 H — 3 3 4 0 . 0— 0 1 . 1 L0 2 0 .08 2 0 .00 5 .00 7 . 0 M °0 °8 °0 °8 P6 4 2 .06 5 2 .05 2 .60 5 . 6 C A 2 1 0 - S M g n i w a r D C E D E J * 3 t a . 6 0 t _ 2 1 1 5 / 1 1 1 5 HE eB D A L M C 16-Pin (SO).eps SO (16-Pin) 3 2 1 EP D SEATING PLANE B G A H F E L 24-Pin (TSSOP).eps C M TSSOP (24-Pin) Package Dimensions IMP5IMP5 11111/51/5 111122 IMP5IMP5 11111/51/5 111122 Daily Silver IMP

IMP5IMP5 11111/51/5 111122 IMP5IMP5 11111/51/5 111122 The IMP logo is a registered trademark of Daily Silver IMP. All other company and product names are trademarks of their respective owners. Daily Silver IMP Microelectronics Co.,Ltd

7 Keda Road , Hi-Tech Park,

NingBo,Zhejiang, P.R.C. Post Code : 315040 Tel:(086)-574-87906358 Fax:(086)-574-87908866 e-mail:sales@ds-imp.com.cn http://www.ds-imp.com.cn

2005 Daily Silver IMP

Revision : A Issue Date: 08 / 08 / 05 Type: Product