IMP1832

IIMP1832 IMP | Alldatasheet

Document overview

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Technical content

Also included is a watchdog timer to stop and restart a microprocessor that is “hung-up”. Three watchdog time- out periods are selectable: 150ms, 610ms and 1,200ms. If the ST input is not strobed LOW before the time-out period expires, a reset is issued. Devices are available in 8-pin DIP , 8-pin SO and compact 8-pin MicroSO packages. © 1999 IMP , Inc. 408-432-9100/www.impweb.com 1 Key Features N Pin compatible with the Dallas Semiconductor DS1832 — Over 40% lower supply current N 3.3V supply monitor N Push-pull output N Selectable watchdog period N Debounce manual push-button reset input N Precision temperature-compensated voltage reference and comparator N Power-up, power-down and brownout detection N 250ms minimum reset time N Active LOW and HIGH reset signal N Selectable trip point tolerance: 10% or 20% N Low-cost 8-pin DIP/SO and 8-pin MicroSO packages N Wide operating temperature –40 °C to +85°C Block Diagram VCC RESET PBRST 1 1832_02.eps 40k/K57 TOL IMP1832 VCC 10%/20% Tolerance Selection Reference VCC TD Push Button Debounce

2 Watchdog

Reset & Watchdog Timer ST 7 Watchdog Transition Detector VCC RESET IMP1IMP1 832832 POWER MANAGEMENT 3.3V 3.3V µµP PP Poowwer Suppler Supplyy MonitMonitor and Ror and Reset Cireset Circuitcuit – Select– Selectable Table Trriipp-P-Point Toint Tolerolerance andance and WWatcatchdog Phdog Pereriodiod – Push-Butt– Push-Button Ron Reseteset – Push-Pull R– Push-Pull Reset Outputseset Outputs The IMP1832 microprocessor supervisor can halt and restart a “hung- up” or “stalled” microprocessor, restart a microprocessor after a power failure, and debounce a manual push-button microprocessor reset switch. The IMP1832 features over 40% lower supply current than the pin compatible Dallas Semiconductor DS1832. Precision temperature compensated reference and comparator circuits monitor the 3.3V , V CC input voltage. During power-up or when the V CC power supply falls outside selectable tolerance limits, both RESET and RESET become active. When V CC rises above the threshold voltage, the reset signals remain active for an additional 250ms minimum, allowing the power supply and system microprocessor to stabilize. The trip point tolerance signal, TOL, selects the trip level tolerance to be either 10- or 20-percent. RESET and RESET outputs are push-pull. A debounced manual reset input, PBRST, activates the reset outputs for a minimum period of 250ms.

2 408-432-9100/www.impweb.com © 1999 IMP , Inc. Pin Configuration IMP1IMP1 832832 Pin Descriptions IMP1832 1832_01.eps RESET

6 RESET

Ordering Information

(tnerruC µ )A gnirotinoMegatloV noitacilppA 2381PMIP ID-8 – 04C° 58otC ° 02V 3.3 S2381PMIO S-8 – 04C° 58otC ° 02V 3.3 AMES2381PMIO SorciM-8 – 04C° 58otC ° 02V 3.3 spe.10t_2381 Pin Number 8-Pin Package Name Function

1 PBRST Debounced manual pushbutton reset input

2 TD Watchdog time delay selection. (t TD = 150ms for TD = GND, tTD = 610ms for TD = Open, and tTD =1200ms for TD = VCC )

3 TOL Selects 10% (TOL connected to GND) or 20% (TOL connected to V CC ) trip point tolerance

4 GND Ground

5 RESET Active HIGH reset output. RESET is active: 1. If VCC falls below the reset voltage trip point. 2. If PBRST is LOW. 3. If ST is not strobed LOW before the timeout period set by TD expires. 4. During power-up. 6 RESET Active LOW reset output. (See RESET)

7 ST Strobe Input

© 1999 IMP , Inc. 408-432-9100/www.impweb.com 3 IMP1IMP1 832832 Absolute Maximum Ratings

Electrical Characteristics

Voltages measured with respect to ground. These are stress ratings only and functional operation is not implied. Parameter Symbol Conditions Min Typ Max Units Supply Voltage (VCC )V CC 1.0 5.5 V ST and PBRST Input High Level V IH VCC ≥ 2.7V 2 V CC + 0.3V V ST and PBRST Input High Level V IH VCC < 2.7V V CC - 0.4V V ST and PBRST Input Low Level V IL –0.3 0.5 V VCC Trip Point (TOL = GND) V CCTP 2.80 2.88 2.97 V VCC Trip Point (TOL = VCC )V CCTP 2.47 2.55 2.64 V Watchdog Time-Out Period t TD TD = GND 62.5 150 250 ms Watchdog Time-Out Period t TD TD = VCC 500 1200 2000 ms Watchdog Time-Out Period t TD TD floating 250 610 1000 ms Output Voltage V OH I = –500µA, VCC < 2.7V V CC - 0.3V V CC - 0.1V V Output Current I OH Output = 2.4V, VCC ≥ 2.7V 350 µA Output Current I OL Output = 0.4V, VCC ≥ 2.7V 10 mA Input Leakage I IL –1.0 1.0 µA RESET Low Level V OL 0.4 V Internal Pull-Up Resistor PBRST pin 40 k Ω Operating Current I CC1 Outputs open. VCC ≤ 3.6V 20 µA and all inputs at VCC or GND Input Capacitance C IN 5p F Output Capacitance C OUT 7p F PBRST Manual Reset t PB PBRST = V IL 20 ms Minimum Low Time Reset Active Time t RST 250 610 1000 ms ST Pulse Width t ST Must not exceed tRD minimum. 20 ns Watchdog cannot be disabled. VCC Fail Detect to t RPD Pulses < 2µs at VCCTP 58 µs RESET or RESET minimum will not cause reset. VCC Slew Rate t F 20 µs PBRST Stable LOW to t PDLY 20 ms RESET and RESET Active V CC Detect to RESET or t RPU trise= 5µs 250 610 1000 ms RESET Inactive VCC Slew Rate t R 0n s Unless otherwise stated, 1.2V ≤ VCC ≤ 5.5V and over the operating temperature range of –40 °C to +85°C . All voltages are referenced to ground.

On power-down, once VCC falls below the reset threshold RESET stays LOW and is guaranteed to be 0.4V or less until V CC drops below 1.2V . The active HIGH reset signal is valid down to a V CC level of 1.2V also. Manual Reset Operation Push-button switch input, PBRST, allows the user to override the internal trip point detection circuits and issue reset signals. The pushbutton input is debounced and is pulled HIGH through an internal 40kΩ resistor. When PBRST is held LOW for the minimum time t PB , both resets become active and remain active for a minimum time period of 250ms after PBRST returns HIGH. The debounced input is guaranteed to recognize pulses greater than 20ms. No external pull-up resistor is required, since PBRST is pulled HIGH by an internal 40k Ω resistor. The PBRST can be driven from a TTL or CMOS logic line or short- ed to ground with a mechanical switch. ecnareloT tceleSe cnareloT )V(egatloVtnioPPIRT niMl animoNx aM V=LOT CC %027 4.25 5.24 6.2 DNG=LOT% 010 8.28 8.27 9.2 spe.20t2381 4 408-432-9100/www.impweb.com © 1999 IMP , Inc. IMP1IMP1 832832

Application Information

The IMP1832 monitors the microprocessor or microcontroller power supply and issues reset signals, both active HIGH and active LOW, that halt processor operation whenever the power supply voltage levels are outside a predetermined tolerance. Tolerance levels are set with the TOL pin. RESET and RESET signals are generated at the last moment of a valid V CC signal. On power-up, both reset signals are active for a minimum of 250ms after the supply has returned to intolerance level. This allows the power supply and monitored processor to stabilize before instruction execution is allowed to begin. Trip Point Tolerance Selection With TOL connected to V CC, RESET and RESET become active whenever VCC falls below 2.64V . RESET and RESET become active when VCC falls below 2.98V if TOL is connected to ground. After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of 250ms. Figure 1. Timing Diagram: Power Up Figure 2. Timing Diagram: Power Down Figure 3. Timing Diagram: Pushbutton Reset Figure 4. Application Circuit: Pushbutton Reset

1 VCC

Watchdog Timer and ST Input A watchdog timer stops and restarts a microprocessor that is “hung-up”. Through the time delay input, TD, three watchdog time-out periods are selectable: 150ms, 610ms and 1,200ms. If the strobe input, ST, is not strobed LOW prior to timeout, reset signals become active. On power-up or after the supply voltage returns to an in-tolerance condition, the reset signal remains active for 250ms minimum, allowing the power supply and system micro- processor to stabilize. ST Pulses as short as 20ns can be detected. Figure 5. Timing Diagram: Strobe Input Note: ST is ignored whenever a reset is active. Figure 6. Application Circuit: Watchdog Timer selected through the TD pin. a high-to-low transition to avoid a watchdog timeout and reset.

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IMP , Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Tel: 800-438-3722 Fax: 408-434-0335 e-mail: info@impinc.com http://www.impweb.com The IMP logo is a registered trademark of IMP , Inc. All other company and product names are trademarks of their respective owners. © 1999 IMP, Inc. Printed in USA Publication #: 1015 Revision: B Issue Date: 11/08/99 Type: Preliminary