IMP1232LPEMA | DigiCamel IC Datasheet

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IMP1232LP IMP | Alldatasheet

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PDF pages: 7

Technical content

© 1999 IMP , Inc. 408-432-9100/www.impweb.com 1 Key Features N Pin compatible with the Dallas Semiconductor DS1232LP/1232LPS — 40% lower supply current N 5V supply monitor N Selectable watchdog period N Debounce manual push-button reset input N Precision temperature-compensated voltage reference and comparator N Power-up, power-down and brownout detection N 250ms reset time N Active LOW open-drain reset and active HIGH push-pull output N Selectable trip point tolerance: 5% or 10% N Low-cost, surface mount packages: 8/16-pin SO, 8-pin DIP and 8-pin MicroSO N Wide operating temperature –40 °C to +85°C (N/EPA suffixed devices) Block Diagram RESET PBRST 1 (2) 1232_03.eps 40kΩ TOL IMP1232LP/LPS (16-Pin Package)3 (6) VCC 5%/10% Tolerance Selection Reference VCC 8 (15) RESET 5 (9) TD Push Button Debounce 2 (4) Watchdog Timebase Selection GND 4 (8) Reset & Watchdog Timer 6 (11) ST 7 (13) Watchdog Transition Detector IMP1IMP1 232LP/LPS232LP/LPS POWER MANAGEMENT 5V 5V µµP PP Poowwer Suppler Supply Monity Monitor andor and RReset Cireset Circuitcuit – Select– Selectable Table Trriipp-P-Point Toint Toleroleranceance and Wand Watcatchdog Phdog Pereriodiod – Push-Butt– Push-Button Ron Reseteset The IMP1232LP/LPS microprocessor supervisor can halt and restart a “hung-up” or “stalled” microprocessor, restart a microprocessor after a power failure, and debounce and interface a manual push-button micro- processor reset switch. The low-power supervisors feature 40% lower supply current than the pin compatible Dallas Semiconductor DS1232LP/LPS. Precision temperature compensated reference and comparator circuits monitor the 5V , V CC input voltage. During power-up or when the V CC power supply falls outside selectable tolerance limits, both the RESET and RESET become active. When V CC rises above the threshold voltage, the reset signals remain active for an additional 250ms minimum, allowing the power supply and system microprocessor to stabilize. The trip point tolerance signal, TOL, selects the trip level tolerance to be either 5- or 10-percent. Each device has both a push-pull, active HIGH reset output and an open drain, active LOW reset output. A debounced manual reset input activates the reset outputs for a mini- mum period of 250ms. Also included is a watchdog timer to stop and restart a microprocessor that is “hung-up”. Three watchdog time-out periods are selectable: 150ms, 610ms and 1,200ms. If the ST input is not strobed LOW before the time-out period expires, a reset is issued. Devices are available in 8-pin DIP , 8/16-pin SO and com- pact 8-pin MicroSO packages.

6 RESET

Ordering Information

1232_02.eps IMP1232LPSN 13 ST 14 NC

15 V CC

12 NC5NC

11 RESET6TOL

10 NC7NC

9 RESET8GND

(tnerruC µ )A gnirotinoMegatloV noitacilppA PL2321PMIP ID-80 C ° 07otC ° 03V 5 SPL2321PMIO S-610 C ° 07otC ° 03V 5 2-SPL2321PMIO S-80 C ° 07otC ° 03V 5 AMCPL2321PMIO SorciM-80 C ° 07otC ° 03V 5 AMEPL2321PMIO SorciM-80 4– C° 58otC ° 03V 5 NPL2321PMIP ID-80 4– C° 58otC ° 03V 5 2-NSPL2321PMIO S-80 4– C° 58otC ° 03V 5 NSPL2321PMIO S-610 4– C° 58otC ° 03V 5 spe.10t_2321 Pin Number Pin Number 8-Pin P8-Pin P acackkagagee 116-Pin P6-Pin P acackkagagee NNameame FFunctionunction 1 2 PBRST Debounced manual pushbutton RESET input 2 4 TD Watchdog time delay selection. (t TD = 150ms for TD = GND, tTD = 610ms for TD = Open, and tTD =1200ms for TD = VCC ) 3 6 TOL Selects 5% (TOL connected to GND) or 10% (TOL connected to V CC ) trip point tolerance 4 8 GND Ground 5 9 RESET Active HIGH reset output. RESET is active: 1. If VCC falls below the reset voltage trip point. 2. If PBRST is LOW. 3. If ST is not strobed LOW before the timeout period set by TD expires. 4. During power-up. 6 11 RESET Active LOW reset output. (See RESET) 7 13 ST Strobe Input 81 5 V CC 5V power — 1, 3, 5, 7, 10, NC No internal connection 12, 14, 16

Electrical Characteristics

(N/EMA version) 0°C to 70°C Voltages measured with respect to ground. These are stress ratings only and functional operation is not implied. Parameter Symbol Conditions Min Typ Max Units Supply Voltage (VCC )V CC 4.5 5.5 V ST and PBRST Input High Level V IH 2V CC + 0.3V V ST and PBRST Input Low Level V IL –0.3 0.8 V VCC Trip Point (TOL = GND) V CCTP 4.50 4.62 4.74 V VCC Trip Point (TOL = VCC )V CCTP 4.25 4.37 4.49 V Watchdog Time-Out Period t TD TD = GND 62.5 150 250 ms Watchdog Time-Out Period t TD TD = VCC 500 1200 2000 ms Watchdog Time-Out Period t TD TD floating 250 610 1000 ms Output Voltage V OH I = –500µA, Note 3 V CC - 0.5V V CC - 0.1V V Output Current I OH Output = 2.4V , Note 2 – 8 –10 mA Output Current I OL Output = 0.4V, 10 mA Input Leakage I IL Note 1 –1.0 1.0 µA RESET Low Level V OL 0.4 V Internal Pull-Up Resistor Note 1 40 k Ω Operating Current (CMOS) I CC1 30 µA Input Capacitance C IN 5p F Output Capacitance C OUT 10 pF PBRST Manual Reset t PB PBRST = V IL 20 ms Minimum Low Time Reset Active Time t RST 250 610 1000 ms ST Pulse Width t ST Note 4 20 ns VCC Fail Detect to t RPD 58 µs RESET or RESET VCC Slew Rate t F 4.75V to 4.25V 300 µs PBRST Stable LOW to t PDLY 20 ms RESET and RESET Active V CC Detect to RESET or t RPU tRISE = 5µs 250 610 1000 ms RESET Inactive VCC Slew Rate t R 4.25V to 4.75V 0 ns Unless otherwise stated, 4.5V ≤ VCC ≤ 5.5V and over the operating temperature range of 0 °C to +70 °C (–40 °C to +85 °C for N/EMA devices). All voltages are referenced to ground. Notes: 1. PBRST is internally pulled HIGH to V CC through a nominal 40kΩ resistor. 2. RESET is an open drain output. 3. RESET remains within 0.5V of V CC on power-down until VCC falls below 2V . RESET remains within 0.5V of ground on power-down until VCC falls below 2.0V . 4. Must not exceed the minimum watchdog time-out period (t TD). The watchdog circuit cannot be disabled. To avoid a reset, ST must be strobed.

Application Information

Reset Signal Polarity and Output Stage Structure RESET is an active LOW signal. It is developed with an open drain driver. If a pullup resistor is required, typical values are 10kΩ to 50kΩ . RESET is an active High signal developed by a CMOS push-pull output stage and is the logical opposite to RESET. Trip Point Tolerance Selection With TOL connected to V CC, RESET and RESET become active whenever VCC falls below 4.5V . RESET and RESET become active when VCC falls below 4.75V if TOL is connected to ground. After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of 250ms. On power-down, once VCC falls below the reset threshold RESET stays LOW and is guaranteed to be 0.4V or less until V CC drops below 1.2V . The active HIGH reset signal is valid down to a V CC level of 1.2V also. Figure 1. Timing Diagram: Power Up Figure 2. Timing Diagram: Power Down Figure 3. Timing Diagram: Pushbutton Reset Figure 4. Application Circuit: Pushbutton Reset

1 VCC

through an internal 40kΩ resistor. time period of 250ms after PBRST returns HIGH. is pulled HIGH by an internal 40k Ω resistor. ed to ground with a mechanical switch.

IMP1IMP1 232LP/LPS232LP/LPS Package Dimensions 6 408-432-9100/www.impweb.com © 1999 IMP , Inc. E D eA eB C 0°–15° A e b2 b L A1 Plastic DIP (8-Pin)a.eps Plastic DIP (8-Pin) L 0°– 8° C HE e D B A1 A SO (8-Pin).eps SO (8-Pin) MicroSO (8-Pin) e b D E1 E a L C D 0.10mm 0.004in A MicroSO (8-Pin).eps sehcnIs retemilliM niMx aMn iMx aM *)niP-8(OSorciM 1A0 200.09 500.00 50.05 1.0 2A5 920.04 730.05 7.05 9.0 b8 900.07 510.05 2.00 4.0 C1 500.01 900.03 1.03 2.0 D2 411.00 221.00 9.20 1.3 eC SB6520.0C SB56.0 EC SB391.0C SB09.4 1E2 411.00 221.00 9.20 1.3 L7 510.06 720.00 4.00 7.0 a °0 °6 °0 °6 )niP-8(OS A3 50.09 60.05 3.15 7.1 1A4 00.00 10.00 1.05 2.0 B3 10.00 20.03 3.01 5.0 C7 00.00 10.09 1.05 2.0 e0 50.07 2.1 E0 51.07 51.00 8.30 0.4 H8 22.04 42.00 8.50 2.6 L6 10.00 50.00 4.07 2.1 D9 81.07 91.00 8.40 0.2 *)niP-8(PIDcitsalP 2A5 11.05 91.02 9.25 9.4 b4 10.02 20.06 3.06 5.0 2b5 40.00 70.04 1.18 7.1 3b0 30.05 40.00 8.04 1.1 D5 53.00 04.02 0.96 1.01 E0 03.05 23.02 6.76 2.8 1E0 42.00 82.00 1.61 1.7 L5 11.00 51.02 9.21 8.3 ** AA781-OMgniwarDCEDEJ* * AA211-SMgniwarDCEDEJ AB100-SMgniwarDCEDEJ* 3ta.40t_2321

IMP1IMP1 232LP/LPS232LP/LPS IMP , Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Tel: 800-438-3722 Fax: 408-434-0335 e-mail: info@impinc.com http://www.impweb.com The IMP logo is a registered trademark of IMP , Inc. All other company and product names are trademarks of their respective owners. © 1999 IMP, Inc. Printed in USA Publication #: 1011 Revision: B Issue Date: 11/08/99 Type: Preliminary Package Dimensions SO (16-Pin) HE eB D A L 0°– 8° C SO (14-Pin).eps sehcnIs retemilliM niMx aMn iMx aM *)niP-61(OS A6 29.03 401.05 3.25 6.2 1A0 400.08 110.00 1.00 3.0 B3 10.00 20.03 3.01 5.0 C1 900.05 210.03 2.02 3.0 D7 793.03 314.00 1.010 5.01 E4 192.02 662.00 4.70 6.7 eC SB050.0C SB72.1 H4 93.09 14.00 0.015 6.01 L6 10.00 50.00 4.07 2.1 AA310-SMgniwarDCEDEJ* 3ta.30t_62/4252

Product Information

IMP1232LPEMA specifications and overview.

Summary

5V 關P Power Suppl er Supply Monit y Monitor and or and Reset Cir eset Circuit

Description

5V 關P Power Suppl er Supply Monit y Monitor and or and Reset Cir eset Circuit

Source title IMP1232LPEMA Datasheet(PDF) - IMP, Inc

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