DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 10
Technical content
Features
- Dedicated clock buffer power pins for reduced noise, crosstalk and jitter
- Input clock frequency of 25 MHz to 33.3 MHz
- Output frequencies of XINx1, XINx2, XINx3 and XINx4
- Output grouped in two banks of five clocks each
- One REF XIN clock output
- SMBus clock control interface for individual clock disabling and SSCG control and individual back frequency selection
- Output clock duty cycle is 50% (± 5%)
- < 250 ps skew between output clocks within a bank
- Output jitter < 250 psec (175 psec with all outputs at the same frequency)
- Spread Spectrum feature for reduced electromagnetic interference (EMI)
- OE pins for entire output bank enable control and testability
- 48-pin SSOP and TSSOP packages Note: 1. A and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device’s XIN pin. OEA and OEB will three-state REF.
Table 1. Test Mode Logic Table[1]
Notes: 2. Pin numbers ending with * indicate that th ey contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is connected to them. 3. A bypass capacitor (0.1 F) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the trace. 4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s). Pin Description[3] Pin[2] Name PWR [4] I/O Description 3X I N V D D A I Crystal Buffer input pin. Connects to a crystal, or an external clock source. Serves as input clock TCLK, in Test mode. 4X O U T V D D A O Crystal Buffer output pin. Connects to a crystal only. When a Can Oscillator is used or in Test mode, this pin is kept unconnected. 1 REF VDD O Buffered inverted outputs of the signal applied at Xin, typically 33.33 or 25.0 MHz 24* OEA VDD I Output Enable for clock bank A. Causes the CLKA output clocks to be in a three-state condition when driven to a logic low level. 25* OEB VDD I Output Enable for clock bank B. Causes the CLKB output clocks to be in a three-state condition when driven to a logic low level.
18 AGOOD# VDD O When this output signal is a logic low level, it indicates that the output clocks of the
A bank are locked to the input reference clock. This output is latched.
31 BGOOD# VDD O When this output signal is at a logic low level, it indicates that the output clocks of
the B bank are locked to the input reference clock. This output is latched. 6*, 7* SA(0,1) VDD I Clock Bank A selection bits. These control the clock frequency that will be present on the outputs of the A bank of buffers. See Table 1 for frequency codes and selection values. 43*, 42* SB(0,1) VDD I Clock Bank B selection bits. These control the clock frequency that will be present on the outputs of the B bank of buffers. See Table 1 for frequency codes and selection values. 20*, 21*, 22* IA(0:2) VDD I SMBus address selection input pins. See Table 3 SMBus Address table. 27* SSCG# VDD I Enables Spread Spectrum clock modulation when at a logic low level, see Spread Spectrum Clocking on page 6. 48 SDATA VDD I/O Data for the internal SMBus circuitry. 47 SCLK VDD I Clock for the internal SMBus circuitry. 11, 14 VDDA – PWR 3.3V common power supply pin for Bank A PCI clocks CLKA. 38, 35 VDDB – PWR 3.3V common power supply pin for Bank B PCI clocks CLKB. 2, 44, 46 VDD – PWR Power supply for internal Core logic. 23, 29, 30 AVDD – PWR Power for internal analog circuitry. This supply should have a separately decoupled current source from VDD. 9, 10, 12, 15, CLKA (0:4) VDDA O A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks. 40, 39, 37, 34, CLKB (0:4) VDDB O A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks. 5, 8, 13, 17, 19, 26, 28, 32, 36, 41, 45 VSS – PWR Ground pins for the device.
clock output buffers, can be individually enabled or disabled. Table 2. Block Read and Block Write Protocol
9 Write = 0
10 Acknowledge from slave
19 Acknowledge from slave
28 Acknowledge from slave
37 Acknowledge from slave
46 Acknowledge from slave
Table 3. SMBus Address Selection Table 7 1 TESTEN Test Mode Enable.
Table 4. Clarification Table for Byte0, bit 5 Table 5. Test Table
71 R e s e r v e d
61 R e s e r v e d
51 R e s e r v e d
parallel resonant crystal is attached to the XIN and XOUT pins. cation the XOUT pin must be left disconnected. orderly and predictable manner.
- At initial power-up this bit is set of a logic 1 state and thus
the output clock’s frequency. CXINFTG= The clock generators XIN pin effective device internal capacitance to ground. CXOUTFTG= The clock generators XOUT pin effective device internal capacitance to ground. CXINPCB= The effective capacitance to ground of the crystal to device PCB trace. CXOUTPCB= The effective capacitance to ground of the crystal to device PCB trace. CXINDISC= Any discrete capacitance that is placed between the XIn pin and ground. CXOUTDISC= Any discrete capacitance that is placed between the XIn pin and ground.
- For best performance and accurate frequencies from this device , it is recommended but not mandatory that the chosen crystal meets or exceeds these specifi-
- Larger values may cause this device to exhibit oscillator startup problems.
Table 6. Suggested Oscillator Crystal Parameters
designed to work into a load of 20 pF. greater extent, at all it's harmonics. pin 27 (SSCG#) or internally via SMBus Byte 0 Bit 0 and 6. Byte 0 Bit 6 LOW to set the feature active. Table 7. Spectrum Spreading Selection Table[7]
- When SSCG is enabled, the device will down spread the clock over a range that is 1% of its resting frequency. This means that for a 100-MHz output clock
frequency will sweep through a spectral range from 99 to 100 MHz. Figure 1. Spread Spectrum
Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD,VDDP Core Supply Voltage –0.5 4.6 V VDDA Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to V SS –0.5 V DD + 0.5 VDC TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 15 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) 45 °C/W UL–94 Flammability Rating At 1/8 in. V – 0 MSL Moisture Sensitivity Level 1 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Parameter Description Condition Min. Max. Unit VDD, VDDA, VDDB 3.3 Operating Voltage 3.3V ± 5% 3.135 3.465 V VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – – VIL Input Low Voltage S(A,B)O, S(A,B)1, OE(A,B) V SS – 0.5 0.8 V VIH Input High Voltage 2.0 V DD + 0. 5 V IIL Input Leakage Current except pull-ups or pull-downs 0<V IN < VDD –5 5 µA VOL Output Low Voltage I OL = 1 mA – 0.4 V VOH Output High Voltage I OH = –1 mA 2.4 – V IOZ High-Impedance Output Current –10 10 µA CIN Input Pin Capacitance 2 5 pF COUT Output Pin Capacitance 3 6 pF LIN Pin Inductance – 7 nH CXTAL Crystal Pin Capacitance From XIN and XOUT pins to ground 32 38 pF VXIH Xin High Voltage 0.7V DD VDD V VXIL Xin Low Voltage 0 0.3V DD V IDD Dynamic Supply Current At 133 MHz and all outputs loaded per Table 8 –3 0 0 m A IPD Power-down Supply Current PD# Asserted – 1 mA Parameter Description Condition Min. Max. Unit Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70%. 45 55 % XINFREQ XIN Frequency When Xin is driven from an external clock source 25 33.3 MHz
Figure 2. Test and Measurement Set-up Table 8. Loading
Ordering Information
Part Number Package Type Product Flow IMIC9530CY 48-Pin SSOP Commercial, 0° to 70°C IMIC9530CYT 48-Pin SSOP – Tape and Reel Commercial, 0° to 70°C IMIC9530CT 48-Pin TSSOP Commercial, 0° to 70°C IMIC9530CTT 48-Pin TSSOP – Tape and Reel Commercial, 0° to 70°C Lead-free CYI9530ZXC 48-Pin TSSOP Commercial, 0° to 70°C CYI9530ZXCT 48-Pin TSSOP – Tape and Reel Commercial, 0° to 70°C
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil- icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre- sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli- cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Package Drawing and Dimensions 48-lead Shrunk Small Outline Package O48 1.100[0.043] SEATING PLANE 124 0.508[0.020] 0.500[0.019] 7.950[0.313] 0.25[0.010] 6.198[0.244] 12.395[0.488] 8.255[0.325] 5.994[0.236] 0.950[0.037] 0.500[0.020] BSC 12.598[0.496] 0.152[0.006] 0.762[0.030] 0°-8° DIMENSIONS IN MM[INCHES] MIN. MAX. MAX. 0.170[0.006] 0.279[0.011] GAUGE PLANE 0.20[0.008] 25 48 0.100[0.003] 0.200[0.008] REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG. 48-lead (240-mil) TSSOP II Z4824