HWC30NC HW | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 2
Technical content
Features
- Low Cost GaAs Power FET
- • •• Class A or Class AB Operation
- • •• 11 dB Typical Gain at 4 GHz
- • •• 5V to 10V Operation
Description
The HWC30NC is a medium power GaAs FET designed for various L-band & S-band applications. Absolute Maximum Ratings VDS Drain to Source Voltage +15V VGS Gate to Source Voltage -5V ID Drain Current I DSS IG Gate Current 3mA TCH Channel Temperature 175 °C TSTG Storage Temperature -65 to +175 °C PT * Power Dissipation 6W * mounted on an infinite heat sink Outline Dimensions S o u r c e S o u r c e Electrical Specifications (T A=25 °C) f =4 GHz for all RF Tests Symbol Parameters & Conditions Units Min. Typ. Max. IDSS Saturated Current at V DS =3V, V GS =0V mA 500 600 900 VP Pinch-off Voltage at V DS =3V, I D=30mA V -3.5 -2.0 -1.5 gm Transconductance at V DS =3V, I D=300mA mS - 300 - P1dB Power Output at Test Points V DS =10V, I D=0.5 I DSS dBm 29 30 - G1dB Gain at 1dB Compression Point V DS =10V, I D=0.5 I DSS dB 9 10 - PAE Power-Added Efficiency (P OUT = P 1dB ) VDS =10V, I D=0.5 I DSS % 30 35 - Small Signal Common Source Scattering Parameters 860 650 430 210 0.0 58.5 344.5 400.0 Units: µ m Thickness: 100 ±5 Chip size ±50 Bond Pads 1-3 (Gate): 60 x 60 Bond Pads 4-6 (Drain): 60 x 60
C-Band Power FET Non-Via Hole Chip Autumn 2002 V1 S-MAGN AND ANGLES V DS =10V, I DS =0.5I DSS Bonding Manner Gate, drain pad: 1 wire on each pad Source pad: 2 wires on each side