GAL22LV10 LATTICE | Alldatasheet

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I I I I I I I I NC NC NC GND I I I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q Vcc I/O/Q I/O/Q I/O/Q 42 6 161412 FUNCTIONAL BLOCK DIAGRAMFEATURES

  • HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — 4 ns Maximum Propagation Delay — Fmax = 250 MHz — 3 ns Maximum from Clock Input to Data Output — UltraMOS ® Advanced CMOS Technology
  • 3.3V LOW VOLTAGE 22V10 ARCHITECTURE — JEDEC-Compatible 3.3V Interface Standard — 5V Compatible Inputs — I/O Interfaces with Standard 5V TTL Devices (GAL22LV10C)
  • ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)

2 CELL TECHNOLOGY

— Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention

  • TEN OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity
  • PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability
  • APPLICATIONS INCLUDE: — Glue Logic for 3.3V Systems — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade
  • ELECTRONIC SIGNATURE FOR IDENTIFICATION PROGRAMMABLE AND-ARRAY (132X44) I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I/CLK I I I I I I I I I I RESET PRESET OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC GAL22LV10 Top View PLCC PIN CONFIGURATION GAL22LV10 Low Voltage E2CMOS PLD Generic Array Logic™ Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

DESCRIPTION

The GAL22LV10D, at 4 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL22LV10C can interface with both 3.3V and 5V signal levels. The GAL22LV10 is manufactured using Lattice Semiconductor's advanced 3.3V E 2CMOS process, which com- bines CMOS with Electrically Erasable (E2) floating gate technol- ogy. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. 22lv10_03 New 5V Tolerant Inputs on 22LV10D

GAL22LV10 ORDERING INFORMATION Commercial Grade Specifications )sn(dpT) sn(usT) sn(ocT) Am(ccI# gniredrOe gakcaP 433 0 31J L4-D01VL22LAGC CLPdaeL-82 55 .35 .30 31J L5-D01VL22LAGC CLPdaeL-82 5.75 .65 5 7J L7-C01VL22LAGC CLPdaeL-82 015 .75 .65 7J L01-C01VL22LAGC CLPdaeL-82 510 10 15 7J L51-C01VL22LAGC CLPdaeL-82 PART NUMBER DESCRIPTION Blank = CommercialGrade PackagePowerL = Low Power Speed (ns) XXXXXXXX XX X X X Device Name J = PLCC GAL22LV10D GAL22LV10C

OUTPUT LOGIC MACROCELL (OLMC) OUTPUT LOGIC MACROCELL CONFIGURATIONS GAL22LV10 OUTPUT LOGIC MACROCELL (OLMC) Each of the Macrocells of the GAL22LV10 has two primary func- tional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are nor- mally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an in- dividual product-term for each OLMC, and can therefore be de- fined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product- term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. The GAL22LV10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. The GAL22LV10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asyn- chronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all reg- isters to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. AR SP D Q QCLK

4 TO 1

2 TO 1

S0 = 1 S1 = 1 S0 = 0 S1 = 1 S0 = 0 S1 = 0 S0 = 1 S1 = 0 AR SP D Q QCLK AR SP D Q QCLK

GAL22LV10 LOGIC DIAGRAM / JEDEC FUSE MAP 26OLMC 5810 5811 0440 0880 ASYNCHRONOUS RESET (TO ALL REGISTERS) 0 4 8 1 21 62 02 42 83 23 64 0 SYNCHRONOUS PRESET (TO ALL REGISTERS) 0000 5764 0044 0396 27S0 5808 5809 25OLMC 5812 5813 0924 1452 24OLMC 5814 5815 1496 2112 23OLMC 5816 5817 2156 2860 21OLMC 5818 5819 2904 3608 20OLMC 5820 5821 3652 4268 OLMC 5822 5823 4312 4840 18OLMC 5824 5825 4884 5324 5368 5720 17OLMC 5826 5827 13 16

8 OLMC

L S B M S B Byte 7 Byte 6 Byte 5 Byte 4 Byte 2 Byte 1 Byte 0Byte 3

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 3.3V and T A = 25 °C COMMERCIAL ICC Operating Power VIL = 0V VIH = 3.0V Unused Inputs at VIL — 90 130 mA Supply Current ftoggle = 1MHz Outputs Open VIL Input Low Voltage Vss - 0.3 — 0.8 V VIH Input High Voltage 2.0 — 5.25 V I/O High Voltage 2.0 — Vcc+0.5 V IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -100 µA IIH Input or I/O High Leakage Current ( Vcc-0.2)V ≤ VIN ≤ VCC ——1 0 µA Input High Leakage Current Vcc ≤ VIN ≤ 5.25V — — 10 µA I/O High Leakage Current Vcc ≤ VIN ≤ 4.6V — — 20 mA VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V IOL = 500µA Vin = VIL or VIH — — 0.2 V VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V IOH = -100µA Vin = VIL or VIH Vcc-0.2V — — V IOL Low Level Output Current — — 8 mA IOH High Level Output Current — — –8 mA IOS 2 Output Short Circuit Current VCC = 3.3V VOUT = 0.5V TA= 25°C -15 — -80 mA ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING COND. Commercial Devices: Supply voltage (VCC ) Ambient Temperature with 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC ELECTRICAL CHARACTERISTICS Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. TYP. 3 MAX. UNITS

MIN. MAX. tpd2 A Input or I/O to Combinational Output 1 4 1 5 ns tco2 A Clock to Output Delay 1 3 1 3.5 ns tcf3 — Clock to Feedback Delay — 2.5 — 3 ns tsu — Setup Time, Input or Feedback before Clock ↑ 3 — 3.5 — ns th — Hold Time, Input or Feedback after Clock ↑ 0— 0 — n s A Maximum Clock Frequency with 167 — 143 — MHz External Feedback, 1/(tsu + tco) fmax 4 A Maximum Clock Frequency with 182 — 154 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 250 — 200 — MHz No Feedback twh 4 — Clock Pulse Duration, High 2 — 2.5 — ns twl4 — Clock Pulse Duration, Low 2 — 2.5 — ns ten B Input or I/O to Output Enabled 1 5 1 6 ns tdis C Input or I/O to Output Disabled 1 5 1 6 ns tar A Input or I/O to Asynchronous Reset of Register 1 4.5 1 5.5 ns tarw — Asynchronous Reset Pulse Duration 4.5 — 5.5 — ns tarr — Asynchronous Reset to Clock ↑ Recovery Time 3.5 — 4 — ns tspr — Synchronous Preset to Clock ↑ Recovery Time 3.5 — 4 — ns AC SWITCHING CHARACTERISTICS MIN. MAX. UNITSPARAMETER TEST COND 1. DESCRIPTION CAPACITANCE (T A = 25°C, f = 1.0 MHz) SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS C I Input Capacitance 5 pF V CC = 3.3V, VI = 0V C I/O I/O Capacitance 5 pF V CC = 3.3V, VI/O = 0V 1) Refer to Switching Test Conditions section. 2) Minimum values for tpd and tco are not 100% tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not 100% tested. COMCOM Over Recommended Operating Conditions

ABSOLUTE MAXIMUM RATINGS (1) Ambient Temperature with 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). RECOMMENDED OPERATING COND. Commercial Devices: Supply voltage (VCC ) VIL Input Low Voltage Vss – 0.5 — 0.8 V VIH Input High Voltage 2.0 — 5.25 V IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -10 µA IIH Input or I/O High Leakage Current ( VCC - 0.2)V ≤ VIN ≤ VCC ——1 0 µA VCC ≤ VIN ≤ 5.25V ——3 0 m A VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V IOL = 0.5 mA Vin = VIL or VIH — — 0.2 V VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V IOH = -0.5 mA Vin = VIL or VIH Vcc-0.45 — — V IOH = -100 µA Vin = VIL or VIH Vcc-0.2 — — V IOL Low Level Output Current — — 8 mA IOH High Level Output Current — — -4 mA IOS 1 Output Short Circuit Current VCC = 3.3V VOUT = 0.5VTA = 25°C -15 — -60 mA DC ELECTRICAL CHARACTERISTICS Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. TYP. 2 MAX. UNITS 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 3.3V and T A = 25 °C COMMERCIAL ICC Operating Power VIL = 0.0V VIH = 3.0V — 45 75 mA Supply Current ftoggle = 1MHz Outputs Open

tpd2 A Input or I/O to Combinatorial Output 2 7.5 2 10 2 15 ns tco2 A Clock to Output Delay 1 5 1 6.5 1 10 ns tcf3 — Clock to Feedback Delay — 3 — 5 — 5 ns tsu — Setup Time, Input or Fdbk before Clk↑ 6.5 — 7.5 — 10 — ns th — Hold Time, Input or Fdbk after Clk↑ 0—0—0— n s A Maximum Clock Frequency with 87 — 71 — 50 — MHz External Feedback, 1/(tsu + tco) fmax 4 A Maximum Clock Frequency with 105 — 80 — 66 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 125 — 111 — 83 — MHz No Feedback twh — Clock Pulse Duration, High 3.5 — 4 — 6 — ns twl — Clock Pulse Duration, Low 3.5 — 4 — 6 — ns ten B Input or I/O to Output Enabled 2 10 2 12 2 15 ns tdis C Input or I/O to Output Disabled 2 10 2 12 2 15 ns tar A Input or I/O to Asynch. Reset of Reg. 2 11 2 13 2 20 ns tarw — Asynch. Reset Pulse Duration 7 — 8 — 12 — ns tarr — Asynch. Reset to Clk ↑ Recovery Time 7 — 8 — 10 — ns tspr — Synch. Preset to Clk ↑ Recovery Time 8 — 10 — 10 — ns -15 MIN. MAX. -10 MIN. MAX. UNITSPARAM TEST COND. 1 Over Recommended Operating Conditions AC SWITCHING CHARACTERISTICS MIN. MAX. COM 1) Refer to Switching Test Conditions section. 2) Minimum values for tpd and tco are not 100% tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Description section. 4) Refer to fmax Description section. SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS C I Input Capacitance 8 pF V CC = 3.3V, VI = 0V C I/O I/O Capacitance 8 pF V CC = 3.3V, VI/O = 0V CAPACITANCE (T A = 25°C, f = 1.0 MHz)

Input or I/O to Output Enable/Disable Registered Output Combinatorial Output INPUT or I/O FEEDBACK REGISTERED OUTPUT CLK VALID INPUT tsu tco th (external fdbk) 1/ fmax CLK (w/o fdbk) twh twl 1/ fmax Clock Width REGISTERED OUTPUT CLK tarw tar tarr INPUT or I/O FEEDBACK DRIVING AR fmax with Feedback CLK REGISTERED FEEDBACK tcf tsu 1/ fmax (internal fdbk) Asynchronous ResetSynchronous Preset tentdis INPUT or I/O FEEDBACK OUTPUT VALID INPUTINPUT or I/O FEEDBACK tpd COMBINATORIAL OUTPUT REGISTERED OUTPUT CLK INPUT or I/O FEEDBACK DRIVING SP tsu th tco tspr SWITCHING WAVEFORMS

fmax with Internal Feedback 1/(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. REGISTERLOGIC ARRAY tcotsu CLK fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. REGISTERLOGIC ARRAY CLK tsu + th CLK REGISTER LOGIC ARRAY tcf tpd

GAL22LV10D: SWITCHING TEST CONDITIONS *CL includes test fixture and probe capacitance. TEST POINT Z0 = 50Ω , CL = 35pF*FROM OUTPUT (O/Q) UNDER TEST +1.45V R 1 Input Pulse Levels GND to 3.0V Input Rise and Fall Times 1.5ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See Figure Output Load Conditions (see figure) Test Condition R 1 C L A5 0 Ω 35pF B High Z to Active High at 1.9V 50Ω 35pF High Z to Active Low at 1.0V 50Ω 35pF C Active High to High Z at 1.9V 50Ω 35pF Active Low to High Z at 1.0V 50Ω 35pF Input Pulse Levels GND to 3.0V Input Rise and Fall Times 2.0ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See Figure 3-state levels are measured 0.5V from steady-state active level. GAL22LV10C: SWITCHING TEST CONDITIONS Output Load Conditions (see figure) Test Condition R 1 R 2 C L A 316 Ω 348Ω 35pF B Active High 316 Ω 348Ω 35pF Active Low 316 Ω 348Ω 35pF C Active High 316 Ω 348Ω 5pF Active Low 316 Ω 348Ω 5pF TEST POINT C *L FROM OUTPUT (O/Q) UNDER TEST +3.3V *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE R 2 R 1

An electronic signature (ES) is provided in every GAL22LV10 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the se- curity cell. The electronic signature is an additional feature not present in other manufacturers' 22V10 devices. To use the extra feature of the user-programmable electronic signature it is necessary to choose a Lattice Semiconductor 22V10 device type when com- piling a set of logic equations. In addition, many device program- mers have two separate selections for the device, typically a GAL22LV10 and a GAL22V10-UES (UES = User Electronic Sig- nature) or GAL22V10-ES. This allows users to maintain compat- ibility with existing 22V10 designs, while still having the option to use the GAL device's extra feature. The JEDEC map for the GAL22LV10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. However, the GAL22LV10 device can still be programmed with a standard 22V10 JEDEC map (5828 fuses) with any qualified device pro- grammer. OUTPUT REGISTER PRELOAD When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state condi- tions. The GAL22LV10 device includes circuitry that allows each reg- istered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically. INPUT BUFFERS GAL22LV10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The input and I/O pins on the GAL22LV10D also have built-in ac- tive pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. (See equivalent input and I/O schematics on the following page.) Typical Input Pull-up Characteristic SECURITY CELL A security cell is provided in every GAL22LV10 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always avail- able to the user, regardless of the state of this control cell. LATCH-UP PROTECTION GAL22LV10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. DEVICE PROGRAMMING GAL devices are programmed using a Lattice Semiconductor- approved Logic Programmer, available from a number of manu- facturers (see the the GAL Development Tools section). Com- plete programming of the device takes only a few seconds. Eras- ing of the device is transparent to the user, and is done automati- cally as part of the programming cycle. Input Voltage (V) Input Current (mA) -80 -70 -60 -50 -40 -30 -20 -10 0.5 1.5 2.5 3.5

Typ. Vref = Vcc Typical Output Typ. Vref = Vcc Typical Input POWER-UP RESET Circuitry within the GAL22V10 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q out- puts set low after a specified time (tpr, 1µs MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asyn- chronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL22V10. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal sys- tem operation, avoid clocking the device until all input and feed- back path setup times have been met. The clock must also meet the minimum pulse width requirements. INPUT/OUTPUT EQUIVALENT SCHEMATICS Vcc PIN VrefTri-State Control Active Pull-up Circuit (GAL22LV10D Only) Feedback (To Input Buffer) PIN Feedback Data Output Vcc PIN Vcc Vref Active Pull-up Circuit (GAL22LV10D Only) ESD Protection Circuit ESD Protection Circuit Vcc PIN Vcc (min.) tpr Internal Register Reset to Logic "0" Device Pin Reset to Logic "1" twl tsu Device Pin Reset to Logic "0" Vcc CLK INTERNAL REGISTER Q - OUTPUT ACTIVE LOW OUTPUT REGISTER ACTIVE HIGH OUTPUT REGISTER

GAL22LV10D: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Normalized Tpd vs Vcc Supply Voltage (V) Normalized Tpd 0.8 0.9 1.1 1.2 PT H->L PT L->H Normalized Tco vs Vcc Supply Voltage (V) Normalized Tco 0.95 0.975 1.025 1.05 RISE FALL Normalized Tsu vs Vcc Supply Voltage (V) Normalized Tsu 0.8 0.9 1.1 1.2 PT H->L PT L->H Normalized Tpd vs Temp Temperature (deg. C) Normalized Tpd 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 PT H->L PT L->H Normalized Tco vs Temp Temperature (deg. C) Normalized Tco 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 RISE FALL Normalized Tsu vs Temp Temperature (deg. C) Normalized Tsu 0.7 0.8 0.9 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 PT H->L PT L->H Delta Tpd vs # of Outputs Switching Number of Outputs Switching Delta Tpd (ns) -0.5 -0.4 -0.3 -0.2 -0.1 123456789 1 0 RISE FALL Delta Tco vs # of Outputs Switching Number of Outputs Switching Delta Tco (ns) -0.5 -0.4 -0.3 -0.2 -0.1 123456789 1 0 RISE FALL Delta Tpd vs Output Loading Output Loading (pF) Delta Tpd (ns) 0 50 100 150 200 250 300 RISE FALL Delta Tco vs Output Loading Output Loading (pF) Delta Tco (ns) 0 50 100 150 200 250 300 RISE FALL

GAL22LV10D: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Vol vs Iol Iol (mA) Vol (V) 0.2 0.4 0.6 0.8 Voh vs Ioh Ioh(mA) Voh (V) Voh vs Ioh Ioh(mA) Voh (V) 2.7 2.8 2.9 3.1 Normalized Icc vs Vcc Supply Voltage (V) Normalized Icc 0.60 0.80 1.00 1.20 1.40 Normalized Icc vs Temp Temperature (deg. C) Normalized Icc 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Normalized Icc vs Freq. Frequency (MHz) Normalized Icc 1.00 1.05 1.10 1.15 1.20 1.25 1.30 0 25 50 75 100 Delta Icc vs Vin (1 input) Vin (V) Delta Icc (mA) Input Clamp (Vik) Vik (V) Iik (mA)

GAL22LV10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Normalized Tpd vs Vcc Supply Voltage (V) Normalized Tpd 0.8 0.9 1.1 1.2 PT H->L PT L->H Normalized Tco vs Vcc Supply Voltage (V) Normalized Tco 0.95 0.975 1.025 1.05 RISE FALL Normalized Tsu vs Vcc Supply Voltage (V) Normalized Tsu 0.8 0.9 1.1 1.2 PT H->L PT L->H Normalized Tpd vs Temp Temperature (deg. C) Normalized Tpd 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 PT H->L PT L->H Normalized Tco vs Temp Temperature (deg. C) Normalized Tco 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 RISE FALL Normalized Tsu vs Temp Temperature (deg. C) Normalized Tsu 0.7 0.8 0.9 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 PT H->L PT L->H Delta Tpd vs # of Outputs Switching Number of Outputs Switching Delta Tpd (ns) -0.5 -0.4 -0.3 -0.2 -0.1 123456789 1 0 RISE FALL Delta Tco vs # of Outputs Switching Number of Outputs Switching Delta Tco (ns) -0.5 -0.4 -0.3 -0.2 -0.1 123456789 1 0 RISE FALL Delta Tpd vs Output Loading Output Loading (pF) Delta Tpd (ns) 0 50 100 150 200 250 300 RISE FALL Delta Tco vs Output Loading Output Loading (pF) Delta Tco (ns) 0 50 100 150 200 250 300 RISE FALL

GAL22LV10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Vol vs Iol Iol (mA) Vol (V) 0.2 0.4 0.6 0.8 Voh vs Ioh Ioh(mA) Voh (V) Voh vs Ioh Ioh(mA) Voh (V) 2.7 2.8 2.9 3.1 Normalized Icc vs Vcc Supply Voltage (V) Normalized Icc 0.60 0.80 1.00 1.20 1.40 Normalized Icc vs Temp Temperature (deg. C) Normalized Icc 0.8 0.9 1.1 1.2 -55 -25 0 25 50 75 100 125 Normalized Icc vs Freq. Frequency (MHz) Normalized Icc 0.80 1.00 1.20 1.40 1.60 1.80 0 2 55 07 5 1 0 0 Delta Icc vs Vin (1 input) Vin (V) Delta Icc (mA) Input Clamp (Vik) Vik (V) Iik (mA)