GAL20V8Z-15QJ

GAL20V8Z LATTICE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 19

Technical content

Features

• ZERO POWER E 2CMOS TECHNOLOGY — 100 µA Standby Current — Input Transition Detection on GAL20V8Z — Dedicated Power-down Pin on GAL20V8ZD — Input and Output Latching During Power Down
• HIGH PERFORMANCE E 2CMOS TECHNOLOGY — 12 ns Maximum Propagation Delay — Fmax = 83.3 MHz — 8 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Output Drive — UltraMOS ® Advanced CMOS Technology
• E 2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity — Architecturally Similar to Standard GAL20V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability
• APPLICATIONS INCLUDE: — Battery Powered Systems — DMA Control — State Machine Control — High Speed Graphics Processing
• ELECTRONIC SIGNATURE FOR IDENTIFICATION GAL20V8Z GAL20V8ZD Top View DIP GAL 20V8Z 20V8ZD CLKI I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/DPP I I I I I I I I I I/OE I/CLK OE OLMC OLMC OLMC OLMC OLMC OLMC OLMC IMUX IMUX PROGRAMMABLE AND-ARRAY (64 X 40) OLMC PLCC 20v8zzd_03

Description

The GAL20V8Z and GAL20V8ZD, at 100 µA standby current and 12ns propagation delay provides the highest speed and lowest power combination PLD available in the market. The GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad- vanced zero power E 2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. The GAL20V8Z uses Input Transition Detection (ITD) to put the device in standby mode and is capable of emulating the full func- tionality of the standard GAL20V8. The GAL20V8ZD utilizes a dedicated power-down pin (DPP) to put the device in standby mode. It has 19 inputs available to the AND array. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and function- ality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Functional Block Diagram Pin Configuration

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) I SB (µA) Ordering # Package 12 10 8 55 100 GAL20V8Z-12QP 24-Pin Plastic DIP 55 100 GAL20V8Z-12QJ 28-Lead PLCC 15 15 10 55 100 GAL20V8Z-15QP 24-Pin Plastic DIP 55 100 GAL20V8Z-15QJ 28-Lead PLCC Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) I SB (µA) Ordering # Package 12 10 8 55 100 GAL20V8ZD-12QP 24-Pin Plastic DIP 55 100 GAL20V8ZD-12QJ 28-Lead PLCC 15 15 10 55 100 GAL20V8ZD-15QP 24-Pin Plastic DIP 55 100 GAL20V8ZD-15QJ 28-Lead PLCC GAL20V8ZD: Commercial Grade Specifications Blank = Commercial Grade Package Active Power Q = Quarter Power XXXXXXXX XX X X X Device Name P = Plastic DIP J = PLCC GAL20V8Z (Zero Power ITD) GAL20V8ZD (Zero Power DPP) Speed (ns) GAL20V8Z/ZD Ordering Information GAL20V8Z: Commercial Grade Specifications Part Number Description

The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accom- plished by development software/hardware and is completely trans- parent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes is illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the in- put/output configuration. These two global and 16 individual archi- tecture bits define all possible configurations in a GAL20V8Z/ZD. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will trans- parently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. Software compilers support the three different global OLMC modes as different device types. Most compilers also have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combina- torial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. For further details, refer to the compiler soft- ware manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1(2) and pin 13(16) are permanently con- figured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. In complex mode pin 1(2) and pin 13(16) become dedicated in- puts and use the feedback paths of pin 22(26) and pin 15(18) re- spectively. Because of this feedback path usage, pin 22(26) and pin 15(18) do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 18(21) and 19(23)) will not have the feedback option as these pins are always configured as dedicated combinatorial output. When using the standard GAL20V8 JEDEC fuse pattern generated by the logic compilers for the GAL20V8ZD, special attention must be given to pin 4(5) (DPP) to make sure that it is not used as one of the functional inputs. Output Logic Macrocell (OLMC) Compiler Support for OLMC

Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - Pin 1(2) & Pin 13(16) are permanently configured as CLK & OE for registered output configuration. Registered Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 1(2) controls common CLK for the registered outputs. - Pin 13(16) controls common OE for the registered outputs. - Pin 1(2) & Pin 13(16) are permanently configured as CLK & OE for registered output configuration. In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 20R8 and 20RP4 devices with various permutations of polarity, I/O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/Os are possible in this mode. Dedicated input or output functions can be implemented as sub- sets of the I/O function. Registered outputs have eight product terms per output. I/Os have seven product terms per output. Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It cannot be used as functional input. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. DQ Q CLK OE XOR XOR Registered Mode

64-USER ELECTRONIC SIGNATURE FUSES DIP (PLCC) Package Pinouts MSB LSB SYN-2704 AC0-2705 * Note: Input not available on GAL20V8ZD OE 0000 PTD 2640 0280 0320 0600 0640 0920 0960 1240 1280 1560 1600 1880 1920 2200 2240 2520 OLMC OLMC XOR-2567 AC1-2639 OLMC XOR-2566 AC1-2638 OLMC XOR-2565 AC1-2637 OLMC XOR-2564 AC1-2636 XOR-2563 AC1-2635 OLMC XOR-2562 AC1-2634 OLMC OLMC XOR-2561 AC1-2633 XOR-2560 AC1-2632 11(13) 10(12) 9(11) 8(10) 7(9) 6(7) 5(6) 4(5) 3(4) 2(3) 1(2) 23(27) 22(26) 21(25) 20(24) 19(23) 18(21) 17(20) 16(19) 15(18) 14(17) 13(16) 2703 2824 3632201612840 Registered Mode Logic Diagram

In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 20L8 and 20P8 devices with programmable polarity in each macrocell. Up to six I/Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 15(18) & 22(26)) do not have input capability. Designs requiring eight I/Os can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1(2) and 13(16) are always available as data inputs into the AND array. Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It cannot be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1 has no effect on this mode. - Pin 16(19) through Pin 21(25) are configured to this function. Combinatorial Output Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1 has no effect on this mode. - Pin 15(18) and Pin 22(26) are configured to this function. XOR XOR Complex Mode

DIP (PLCC) Package Pinouts * Note: Input not available on GAL20V8ZD 64-USER ELECTRONIC SIGNATURE FUSES 0000 PTD 2640 0280 0320 0600 0640 0920 0960 1240 1280 1560 1600 1880 1920 2200 2240 2520 OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC 23(27) 22(26) 21(25) 20(24) 19(23) 18(21) 17(20) 16(19) 15(18) 14(17) 13(16) 11(13) 10(12) 9(11) 8(10) 7(9) 6(7) 5(6) 4(5) 3(4) 2(3) 1(2) 2703 XOR-2567 AC1-2639 XOR-2566 AC1-2638 XOR-2565 AC1-2637 XOR-2564 AC1-2636 XOR-2563 AC1-2635 XOR-2562 AC1-2634 XOR-2561 AC1-2633 XOR-2560 AC1-2632 2824 3632201612840 Complex Mode Logic Diagram

In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 14L8 and 16P6 devices with many permutations of ge- neric output polarity or input choices. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has pro- grammable polarity. Pins 1(2) and 13(16) are always available as data inputs into the AND array. The center two macrocells (pins 18(21) & 19(23)) can- not be used in the input configuration. Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It cannot be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram. Combinatorial Output with Feedback Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - All OLMC except pins 18(21) & 19(23) can be configured to this function. Combinatorial Output Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - Pins 18(21) & 19(23) are permanently configured to this function. Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - All OLMC except pins 18(21) & 19(23) can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Vcc XOR Vcc XOR Simple Mode

DIP (PLCC) Package Pinouts MSB LSB 64-USER ELECTRONIC SIGNATURE FUSES SYN-2704 AC0-2705 * Note: Input not available on GAL20V8ZD 0000 PTD 2640 0280 0320 0600 0640 0920 0960 1240 1280 1560 1600 1880 1920 2200 2240 2520 OLMC OLMC OLMC OLMC OLMC OLMC OLMC XOR-2560 AC1-2632 OLMC XOR-2561 AC1-2633 XOR-2562 AC1-2634 XOR-2563 AC1-2635 XOR-2564 AC1-2636 XOR-2565 AC1-2637 XOR-2566 AC1-2638 XOR-2567 AC1-2639 23(27) 22(26) 21(25) 20(24) 19(23) 18(21) 17(20) 16(19) 15(18) 14(17) 13(16) 2703 11(13) 10(12) 9(11) 8(10) 7(9) 6(7) 5(6) 4(5) 3(4) 2(3) 1(2) 2824 3632201612840 Simple Mode Logic Diagram

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS C I Input Capacitance 10 pF V CC = 5.0V, VI = 2.0V C I/O I/O Capacitance 10 pF V CC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested Recommended Operating Conditions Commercial Devices: Supply voltage (VCC ) Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. TYP . 2 MAX. UNITS VIL Input Low Voltage Vss – 0.5 — 0.8 V VIH Input High Voltage 2.0 — Vcc+1 V IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –10 µA IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——1 0 µA VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V IOH = -100 µA Vin = VIL or VIH Vcc-1 — — V IOL Low Level Output Current — — 16 mA IOH High Level Output Current — — –3.2 mA IOS 1 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 — –150 mA COMMERCIAL ISB Stand-by Power VIL = GND VIH = Vcc Outputs Open Z-12/-15 — 50 100 µA Supply Current ZD-12/-15 ICC Operating Power VIL = 0.5V VIH = 3.0V Z-12/-15 — — 55 mA Supply Current ftoggle = 15 MHz Outputs Open ZD-12/-15 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 5V and T A = 25 °C Absolute Maximum Ratings(1) Ambient Temperature with 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Capacitance (TA = 25°C, f = 1.0 MHz)

AC Switching Characteristics Over Recommended Operating Conditions tpd A Input or I/O to Combinational Output 3 12 3 15 ns tco A Clock to Output Delay 2 8 2 10 ns tcf2 — Clock to Feedback Delay — 6 — 7 ns tsu — Setup Time, Input or Feedback before Clock ↑ 10 — 15 — ns th — Hold Time, Input or Feedback after Clock ↑ 0—0—n s A Maximum Clock Frequency with 55 — 40 — MHz External Feedback, 1/(tsu + tco) fmax 3 A Maximum Clock Frequency with 62.5 — 45.5 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 83.3 — 62.5 — MHz No Feedback twh — Clock Pulse Duration, High 6 — 8 — ns twl — Clock Pulse Duration, Low 6 — 8 — ns ten B Input or I/O to Output Enabled — 12 — 15 ns B OE to Output Enabled — 12 — 15 ns tdis C Input or I/O to Output Disabled — 15 — 15 ns C OE to Output Disabled — 12 — 15 ns tas — Last Active Input to Standby 60 140 50 150 ns tsa4 — Standby to Active Output 6 13 5 15 ns PARAMETER UNITS -15 MIN. MAX. TEST COND 1. DESCRIPTION -12 MIN. MAX. 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. 4) Add tsa to tpd, tsu, ten and tdis when the device is coming out of standby state. COMCOM POWER INPUT or I/O FEEDBACK OE CLK OUTPUT tas tpd ten, tdis Icc Isb tsa tsu tco * * Note: Rising clock edges are allowed during tsa but outputs are not guaranteed. Standby Power Timing Waveforms

AC Switching Characteristics Over Recommended Operating Conditions tpd A Input or I/O to Combinational Output 3 12 3 15 ns tco A Clock to Output Delay 2 8 2 10 ns tcf2 — Clock to Feedback Delay — 6 — 7n s tsu — Setup Time, Input or Feedback before Clock↑ 10 — 15 — ns th — Hold Time, Input or Feedback after Clock↑ 0 — 0 — ns A Maximum Clock Frequency with 55 — 40 — MHz External Feedback, 1/(tsu + tco) fmax 3 A Maximum Clock Frequency with 62.5 — 45.5 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 83.3 — 62.5 — MHz No Feedback twh — Clock Pulse Duration, High 6 — 8 — ns twl — Clock Pulse Duration, Low 6 — 8 — ns ten B Input or I/O to Output Enabled — 12 — 15 ns B OE to Output Enabled — 12 — 15 ns tdis C Input or I/O to Output Disabled — 15 — 15 ns C OE to Output Disabled — 12 — 15 ns PARAMETER UNITS -15 MIN. MAX. TEST COND 1. DESCRIPTION -12 MIN. MAX. 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. COMCOM

twhd — DPP Pulse Duration High 12 — 15 — ns twld — DPP Pulse Duration Low 25 — 30 — ns tivdh — Valid Input before DPP High 5 — 8 — ns tgvdh — Valid OE before DPP High 0 — 0 — ns tcvdh — Valid Clock Before DPP High 0 — 0 — ns tdhix — Input Don't Care after DPP High — 2 — 5n s tdhgx — OE Don't Care after DPP High — 6 — 9n s tdhcx — Clock Don't Care after DPP High — 8 — 11 ns tdliv — DPP Low to Valid Input 12 — 15 — ns tdlgv — DPP Low to Valid OE 16 — 20 — ns tdlcv — DPP Low to Valid Clock 18 — 20 — ns tdlov A DPP Low to Valid Output 5 24 5 30 ns PARAMETER UNITS -15 MIN. MAX. TEST COND 1. DESCRIPTION -12 MIN. MAX. 1) Refer to Switching Test Conditions section. ACTIVE TO STANDBY STANDBY TO ACTIVE tdhcx DPP INPUT or I/O FEEDBACK OE CLK OUTPUT tcvdh tgvdh tivdh tdhgx tdhix tpd,ten,tdis tco tdliv tdlgv tdlcv tdlov Dedicated Power-Down Pin Specifications Over Recommended Operating Conditions COMCOM Dedicated Power-Down Pin Timing Waveforms

Input or I/O to Output Enable/Disable Clock Width OE to Output Enable/Disable fmax with Feedback COMBINATIONAL OUTPUT VALID INPUTINPUT or I/O FEEDBACK tpd COMBINATIONAL OUTPUT INPUT or I/O FEEDBACK tentdis INPUT or I/O FEEDBACK REGISTERED OUTPUT CLK VALID INPUT (external fdbk) tsu tco th 1/fmax OE REGISTERED OUTPUT tentdis CLK REGISTERED FEEDBACK tcf tsu 1/fmax (internal fdbk) CLK (w/o fb) 1/fmax twltwh Switching Waveforms

Output Load Conditions (see figure) Test Condition R 1 R 2 C L A 300 Ω 390Ω 50pF B Active High ∞ 390Ω 50pF Active Low 300 Ω 390Ω 50pF C Active High ∞ 390Ω 5pF Active Low 300 Ω 390Ω 5pF Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See Figure 3-state levels are measured 0.5V from steady-state active level. Note: tcf is a calculated value, derived by sub- tracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combi- natorial output is equal to tcf + tpd. fmax with Internal Feedback 1/(tsu+tcf) fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. TEST POINT C *L FROM OUTPUT (O/Q) UNDER TEST +5V *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE R 2 R 1 REGISTERLOGIC ARRAY tcotsu CLK fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. REGISTERLOGIC ARRAY CLK tsu + th CLK REGISTER LOGIC ARRAY tcf tpd fmax Specifications Switching Test Conditions

An electronic signature word is provided in every GAL20V8Z/ZD device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is al- ways available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calcula- tions. Changing the electronic signature will alter checksum. Security Cell A security cell is provided in the GAL20V8Z/ZD devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the de- vice, so the original configuration can never be examined once this cell is programmed. The electronic signature data is always avail- able to the user, regardless of the state of this security cell. Device Programming GAL devices are programmed using a Lattice Semiconductor- approved Logic Programmer, available from a number of manu- facturers (see the GAL Development Tools Section of the Data Book). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. Input Transition Detection (ITD) The GAL20V8Z relies on its internal input detection circuitry to put the device in power down mode. If there is no input transition for the specified period of time, the device will go into the power down state. Any valid input transition will put the device back into active state. The first rising clock transition from power-down state only acts as a wake up signal into the device and will not clock the data input through to the output (refer to standby power timing waveform for more detail). Any input pulse widths greater than 5ns at input voltage level of 1.5V will be detected as input transition. The device will not detect any input pulse widths less than 1ns measured at input voltage level of 1.5V as input transition. Dedicated Power-Down Pin The GAL20V8ZD uses pin 4 (pin 5 on PLCC) as the dedicated power-down signal to put the device in power-down state. DPP is an active high signal where logic high driven on this signal puts the device into power-down state. Input pin 4 (5) cannot be used as a functional input on this device. Input Current (uA) Input Voltage (Volts) Typical Input Characteristic -40 -30 -20 -10 012345 Output Register Preload When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The GAL20V8Z/ZD devices includes circuitry that allows each reg- istered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If nec- essary, approved GAL programmers capable of executing text vectors perform output register preload automatically. Input Buffers GAL20V8Z/ZD devices are designed with TTL level compatible in- put buffers. These buffers, with their characteristically high imped- ance, load driving logic much less than traditional bipolar devices. This allows for a greater fan out from the driving logic. GAL20V8Z/ZD input buffers have latches within the buffers. As a result, when the device goes into standby mode the inputs will be latched to its values prior to standby. In order to overcome the input latches, they will have to be driven by an external source. Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins for both devices be connected to another active input, V CC , or GND. Doing this will tend to improve noise immunity and reduce I CC for the device.

Typical OutputTypical Input Circuitry within the GAL20V8Z/ZD provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1µs MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL20V8Z/ZD. First, the V CC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Vcc PIN Vcc ESD Protection Circuit ESD Protection Circuit Vcc PIN Vcc PIN Tri-State Control Feedback (To Input Buffer) PIN Feedback Data Output Vcc CLK INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Vcc (min.) tpr Internal Register Reset to Logic "0" Device Pin Reset to Logic "1" twl tsu Power-Up Reset Input/Output Equivalent Schematics

Supply Voltage (V) Normalized Tpd 0.8 0.9 1.1 1.2 PT H->L PT L->H Normalized Tco vs Vcc Supply Voltage (V) Normalized Tco 0.8 0.9 1.1 1.2 RISE FALL Normalized Tsu vs Vcc Supply Voltage (V) Normalized Tsu 0.8 0.9 1.1 1.2 1.3 1.4 PT H->L PT L->H Normalized Tpd vs Temp Temperature (deg. C) Normalized Tpd 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 100 125 PT H->L PT L->H Normalized Tco vs Temp Temperature (deg. C) Normalized Tco 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 100 125 RISE FALL Normalized Tsu vs Temp Temperature (deg. C) Normalized Tsu 0.7 0.8 0.9 1.1 1.2 1.3 1.4 -55 -25 100 125 PT H->L PT L->H Delta Tpd vs # of Outputs Switching Number of Outputs Switching Delta Tpd (ns) -1.5 -0.5 12345678 RISE FALL Delta Tco vs # of Outputs Switching Number of Outputs Switching Delta Tco (ns) -1.5 -0.5 12345678 RISE FALL Delta Tpd vs Output Loading Output Loading (pF) Delta Tpd (ns) 0 50 100 150 200 250 300 RISE FALL Delta Tco vs Output Loading Output Loading (pF) Delta Tco (ns) 0 50 100 150 200 250 300 RISE FALL Typical AC and DC Characteristics

Iol (mA) Vol (V) 0.25 0.5 0.75 1.25 1.5 0.00 20.00 40.00 60.00 Voh vs Ioh Ioh(mA) Voh (V) Voh vs Ioh Ioh(mA) Voh (V) 2.5 3.5 4.5 Normalized Icc vs Vcc Supply Voltage (V) Normalized Icc 0.70 0.80 0.90 1.00 1.10 1.20 1.30 Normalized Icc vs Temp Temperature (deg. C) Normalized Icc 0.8 0.9 1.1 1.2 -55 -25 0 25 50 75 100 125 Normalized Icc vs Freq. (DPP & ITD > 10MHz) Frequency (MHz) Normalized Icc 0.80 0.90 1.00 1.10 1.20 1.30 0 25 50 75 100 Delta Icc vs Vin (1 input) Vin (V) Delta Icc (mA) Input Clamp (Vik) Vik (V) Iik (mA) Normalized Icc vs Freq. (ITD) Frequency (KHz) Normalized Icc 0.2 0.4 0.6 0.8 1 10 100 1000 10000 Typical AC and DC Characteristics