GAL20LV8

GAL20LV8 LATTICE | Alldatasheet

Document overview

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Technical content

Features

• HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output — UltraMOS ® Advanced CMOS Technology — TTL-Compatible Balanced 8mA Output Drive
• 3.3V LOW VOLTAGE 20V8 ARCHITECTURE — JEDEC-Compatible 3.3V Interface Standard — 5V Compatible Inputs
• ACTIVE PULL-UPS ON ALL PINS

2 CELL TECHNOLOGY

— Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability
• APPLICATIONS INCLUDE: — Glue Logic for 3.3V Systems — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION 22 8 NC I/CLK I I I I I I I NC NC NC GND I I I/OE I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q Vcc I/O/Q I I 12 14 16 18 GAL20LV8D Top View CLKI I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I I I I I I I I I I/OE I/CLK OE OLMC OLMC OLMC OLMC OLMC OLMC OLMC IMUX IMUX PROGRAMMABLE AND-ARRAY (64 X 40) OLMC PLCC New 5V TolerantInputs on 20LV8D

Description

The GAL20LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL20LV8D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which com- bines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be repro- grammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configura- tions possible with the GAL20LV8D are the PAL architectures listed in the table of the macrocell description section. GAL20LV8D devices are capable of emulating any of these PAL architectures with full function/fuse map compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and function- ality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Functional Block Diagram Pin Configuration

Blank = CommercialGrade PackagePowerL = Low Power Speed (ns) XXXXXXXX XX X X X Device Name J = PLCC GAL20LV8D Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package 3.5 3 2.5 70 GAL20LV8D-3LJ 28-Lead PLCC 5 4 3 70 GAL20LV8D-5LJ 28-Lead PLCC 7.5 5 5 70 GAL20LV8D-7LJ 28-Lead PLCC Commercial Grade Specifications Part Number Description

The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accom- plished by development software/hardware and is completely trans- parent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes is illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the in- put/output configuration. These two global and 16 individual archi- tecture bits define all possible configurations in a GAL20LV8D . The information given on these architecture bits is only to give a bet- ter understanding of the device. Compiler software will transpar- ently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GAL20LV8D can emulate. It also shows the OLMC mode under which the devices emulate the PAL architecture. Software compilers support the three different global OLMC modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the soft- ware to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 2 and pin 16 are permanently configured as clock and output enable, respectively. These pins cannot be con- figured as dedicated inputs in the registered mode. In complex mode pin 2 and pin 16 become dedicated inputs and use the feedback paths of pin 26 and pin 18 respectively. Because of this feedback path usage, pin 26 and pin 18 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 21 and 23) will not have the feedback option as these pins are always configured as dedicated combinatorial output. Registered Complex Simple Auto Mode Select ABEL P20V8R P20V8C P20V8AS P20V8 CUPL G20V8MS G20V8MA G20V8AS G20V8 LOG/iC GAL20V8_R GAL20V8_C7 GAL20V8_C8 GAL20V8 OrCAD-PLD "Registered" 1 "Complex"1 "Simple"1 GAL20V8A PLDesigner P20V8R 2 P20V8C 2 P20V8C 2 P20V8A TANGO-PLD G20V8R G20V8C G20V8AS 3 G20V8 1) Used with Configuration keyword. 2) Prior to Version 2.0 support. 3) Supported on Version 1.20 or later. PAL Architectures GAL20LV8D Emulated by GAL20LV8D Global OLMC Mode 20R8 Registered 20R6 Registered 20R4 Registered 20RP8 Registered 20RP6 Registered 20RP4 Registered 20L8 Complex 20H8 Complex 20P8 Complex 14L8 Simple 16L6 Simple 18L4 Simple 20L2 Simple 14H8 Simple 16H6 Simple 18H4 Simple 20H2 Simple 14P8 Simple 16P6 Simple 18P4 Simple 20P2 Simple Output Logic Macrocell (OLMC) Compiler Support for OLMC

In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 20R8 and 20RP4 devices with various permutations of polarity, I/O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/Os are possible in this mode. Dedicated input or output functions can be implemented as sub- sets of the I/O function. Registered outputs have eight product terms per output. I/Os have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. Registered Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 2 controls common CLK for the registered outputs. - Pin 16 controls common OE for the registered outputs. - Pin 2 & Pin 16 are permanently configured as CLK & OE for registered output configuration. Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - Pin 2 & Pin 16 are permanently configured as CLK & OE for registered output configuration. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. DQ Q CLK OE XOR XOR Registered Mode

2520 XOR-2567

41 6 12802 0 2 4 2 8 3 2 3 6 64-USER ELECTRONIC SIGNATURE FUSES MSB LSB SYN-2704 AC0-2705 Registered Mode Logic Diagram

In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 20L8 and 20P8 devices with programmable polarity in each macrocell. Up to six I/Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 18 & 26) do not have input capability. De- signs requiring eight I/Os can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 2 and 16 are always available as data inputs into the AND array. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 19 through Pin 25 are configured to this function. Combinatorial Output Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 18 and Pin 26 are configured to this function. XOR XOR Complex Mode

64-USER ELECTRONIC SIGNATURE FUSES 0000 2703 PTD 2640 0280 0320 0600 0640 0920 0960 1240 1280 1560 1600 1880 1920 2200 2240 41 6 12802 0 2 4 2 8 3 2 3 6 Complex Mode Logic Diagram

Combinatorial Output with Feedback Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - All OLMC except pins 21 & 23 can be configured to this function. Combinatorial Output Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - Pins 21 & 23 are permanently configured to this function. Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - All OLMC except pins 21 & 23 can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. In the Simple mode, pins are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 14L8 and 16P6 devices with many permutations of ge- neric output polarity or input choices. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has pro- grammable polarity. Pins 2 and 16 are always available as data inputs into the AND array. The "center" two macrocells (pins 21 & 23) cannot be used in the input configuration. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Vcc XOR Vcc XOR Simple Mode

41 6 12802 0 2 4 2 8 3 2 3 6 MSB LSB 64-USER ELECTRONIC SIGNATURE FUSES SYN-2704 AC0-2705 Simple Mode Logic Diagram

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 3.3V and T A = 25 °C COMMERCIAL ICC Operating Power VIL = 0V VIH = 3.0V Unused Inputs at VIL —4 57 0 m A Supply Current ftoggle = 1MHz Outputs Open VIL Input Low Voltage Vss – 0.3 — 0.8 V VIH Input High Voltage 2.0 — 5.25 V I/O High Voltage 2.0 — Vcc+0.5 V IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA IIH Input or I/O High Leakage Current ( Vcc-0.2)V ≤ VIN ≤ VCC ——1 0 µA Input High Leakage Current Vcc ≤ VIN ≤ 5.25V — — 10 µA I/O High Leakage Current Vcc ≤ VIN ≤ 4.6V — — 20 mA VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V IOL = 500µA Vin = VIL or VIH — — 0.2 V VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V IOH = -100µA Vin = VIL or VIH Vcc-0.2V — — V IOL Low Level Output Current — — 8 mA IOH High Level Output Current — — –8 mA IOS 2 Output Short Circuit Current VCC = 3.3V VOUT = 0.5V TA= 25°C –15 — –80 mA Recommended Operating Conditions Commercial Devices: Supply voltage (VCC ) Absolute Maximum Ratings(1) Ambient Temperature with 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). SYMBOL PARAMETER CONDITION MIN. TYP . 3 MAX. UNITS Over Recommended Operating Conditions (Unless Otherwise Specified)

tpd2 A Input or I/O to Combinational Output 1 3.5 1 5 1 7.5 ns tco2 A Clock to Output Delay 1 2.5 1 3 1 5 ns tcf3 — Clock to Feedback Delay — 2 — 2 — 3 ns tsu — Setup Time, Input or Feedback before Clock ↑ 3— 4 —5—n s th — Hold Time, Input or Feedback after Clock ↑ 0— 0 —0—n s A Maximum Clock Frequency with 180 — 142.8 — 100 — MHz External Feedback, 1/(tsu + tco) fmax 4 A Maximum Clock Frequency with 200 — 166 — 125 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 250 — 166 — 125 — MHz No Feedback twh 4 — Clock Pulse Duration, High 2 — 3 — 4 — ns twl4 — Clock Pulse Duration, Low 2 — 3 — 4 — ns ten B Input or I/O to Output Enabled — 4.5 — 6 — 7.5 ns B OE to Output Enabled — 3.5 — 5 — 6.5 ns tdis C Input or I/O to Output Disabled — 4.5 — 6 — 7.5 ns C OE to Output Disabled — 3.5 — 5 — 6.5 ns MIN. MAX. MIN. MAX. UNITSPARAMETER TEST COND 1. DESCRIPTION 1) Refer to Switching Test Conditions section. 2) Minimum values for tpd and tco are not 100% tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not 100% tested. SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS C I Input Capacitance 5 pF V CC = 3.3V, VI = 0V C I/O I/O Capacitance 5 pF V CC = 3.3V, VI/O = 0V MIN. MAX. COM COM AC Switching Characteristics Over Recommended Operating Conditions Capacitance (TA = 25°C, f = 1.0 MHz)

Registered OutputCombinatorial Output OE to Output Enable/DisableInput or I/O to Output Enable/Disable fmax with Feedback Clock Width COMBINATIONAL OUTPUT VALID INPUTINPUT or I/O FEEDBACK tpd COMBINATIONAL OUTPUT INPUT or I/O FEEDBACK tentdis CLK (w/o fb) 1/fmax twltwh INPUT or I/O FEEDBACK REGISTERED OUTPUT CLK VALID INPUT (external fdbk) tsu tco th 1/fmax OE REGISTERED OUTPUT tentdis CLK REGISTERED FEEDBACK tcf tsu 1/fmax (internal fdbk) Switching Waveforms

fmax with Internal Feedback 1/(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. REGISTERLOGIC ARRAY tcotsu CLK CLK REGISTER LOGIC ARRAY tcf tpd fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. TEST POINT Z0 = 50Ω , CL = 35pF*FROM OUTPUT (O/Q) UNDER TEST +1.45V R 1 *CL includes test fixture and probe capacitance. REGISTERLOGIC ARRAY CLK tsu + th Output Load Conditions (see figure) Test Condition R 1 C L A5 0 Ω 35pF B High Z to Active High at 1.9V 50Ω 35pF High Z to Active Low at 1.0V 50Ω 35pF C Active High to High Z at 1.9V 50Ω 35pF Active Low to High Z at 1.0V 50Ω 35pF Input Pulse Levels GND to 3.0V Input Rise and Fall Times 1.5ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See Figure fmax Descriptions Switching Test Conditions

Input Voltage (V) -80 -70 -60 -50 -40 -30 -20 -10 0.5 1.5 2.5 3.5 Input Current (µA) Electronic Signature An electronic signature is provided in every GAL20LV8D device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calcula- tions. Changing the electronic signature will alter the checksum. Security Cell A security cell is provided in the GAL20LV8D devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the de- vice, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Latch-Up Protection GAL20LV8D devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots. Device Programming GAL devices are programmed using a Lattice Semiconductor- approved Logic Programmer, available from a number of manu- facturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. Output Register Preload When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. GAL20LV8D devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing text vectors perform output register preload automatically. Input Buffers GAL20LV8D devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The GAL20LV8D input and I/O pins have built-in active pull-ups. As a result, unused inputs and I/Os will float to a TTL “high” (logical “1”). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, V CC , or Ground. Doing this will tend to improve noise immunity and reduce ICC for the device. Typical Input Pull-up Characteristic

Typ. Vref = Vcc Typical Output Typ. Vref = Vcc Typical Input Vcc PIN VrefTri-State Control Active Pull-up Circuit Feedback (To Input Buffer) PIN Feedback Data Output Circuitry within the GAL20LV8D provides a reset signal to all reg- isters during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1µs MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchro- nous nature of system power-up, some conditions must be met to provide a valid power-up reset of the device. First, the V CC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will re- set within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Vcc PIN Vcc Vref Active Pull-up Circuit ESD Protection Circuit ESD Protection Circuit Vcc PIN Vcc CLK INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Vcc (min.) tpr Internal Register Reset to Logic "0" Device Pin Reset to Logic "1" twl tsu Power-Up Reset Input/Output Equivalent Schematics

Supply Voltage (V) Normalized Tpd 0.8 0.9 1.1 1.2 PT H->L PT L->H Normalized Tco vs Vcc Supply Voltage (V) Normalized Tco 0.8 0.9 1.1 1.2 RISE FALL Normalized Tsu vs Vcc Supply Voltage (V) Normalized Tsu 0.8 0.9 1.1 1.2 PT H->L PT L->H Normalized Tpd vs Temp Temperature (deg. C) Normalized Tpd 0.8 0.9 1.1 1.2 -55 -25 0 25 50 75 100 125 PT H->L PT L->H Normalized Tco vs Temp Temperature (deg. C) Normalized Tco 0.8 0.9 1.1 1.2 -55 -25 0 25 50 75 100 125 RISE FALL Normalized Tsu vs Temp Temperature (deg. C) Normalized Tsu 0.8 0.9 1.1 1.2 -55 -25 0 25 50 75 100 125 PT H->L PT L->H Delta Tpd vs # of Outputs Switching Number of Outputs Switching Delta Tpd (ns) -0.5 -0.4 -0.3 -0.2 -0.1 1234567 8 RISE FALL Delta Tco vs # of Outputs Switching Number of Outputs Switching Delta Tco (ns) -0.5 -0.4 -0.3 -0.2 -0.1 12345678 RISE FALL Delta Tpd vs Output Loading Output Loading (pF) Delta Tpd (ns) 0 50 100 150 200 250 300 RISE FALL Delta Tco vs Output Loading Output Loading (pF) Delta Tco (ns) 0 50 100 150 200 250 300 RISE FALL Typical AC and DC Characteristic Diagrams

Iol (mA) Vol (V) 0.25 0.5 0.75 Voh vs Ioh Ioh(mA) Voh (V) 0.5 1.5 2.5 Voh vs Ioh Ioh(mA) Voh (V) 2.8 2.85 2.9 2.95 Normalized Icc vs Vcc Supply Voltage (V) Normalized Icc 0.80 0.90 1.00 1.10 1.20 Normalized Icc vs Temp Temperature (deg. C) Normalized Icc 0.8 0.9 1.1 1.2 -55 -25 0 25 50 75 100 125 Normalized Icc vs Freq. Frequency (MHz) Normalized Icc 0.80 0.90 1.00 1.10 1.20 1.30 1.40 0 25 50 75 100 Delta Icc vs Vin (1 input) Vin (V) Delta Icc (mA) Input Clamp (Vik) Vik (V) Iik (mA) Typical AC and DC Characteristic Diagrams