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Technical content

Features

  • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 100 MHz — 6 ns Maximum from Clock Input to Data Output — TTL Compatible 12 mA Outputs — UltraMOS ® Advanced CMOS Technology
  • 50% REDUCTION IN POWER FROM BIPOLAR — 75mA Typ Icc
  • ACTIVE PULL-UPS ON ALL PINS (GAL16V8D-7 and GAL16V8D-10)
  • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention
  • EIGHT OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity — Also Emulates 20-pin PAL ® Devices with Full Function/ Fuse Map/Parametric Compatibility
  • PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability
  • APPLICATIONS INCLUDE: — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade
  • ELECTRONIC SIGNATURE FOR IDENTIFICATION I/CLK I I/O/Q I I/O/Q I I/O/Q I I/O/Q I I/O/Q I I/O/Q I I/O/Q I I/O/Q CLK OE OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC PROGRAMMABLE AND-ARRAY (64 X 32) I/OE

Description

The GAL16V8/883 is a high performance E 2CMOS program- mable logic device processed in full compliance to MIL-STD-883. This military grade device combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed/power performance available in the 883 qualified PLD market. The GAL16V8D/883, at 7.5ns maxi- mum propagation delay time, is the world's fastest military quali- fied CMOS PLD. The generic GAL architecture provides maximum design flexibil- ity by allowing the Output Logic Macrocell (OLMC) to be config- ured by the user. The GAL16V8/883 is capable of emulating all standard 20-pin PAL ® devices with full function/fuse map/para- metric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. Therefore, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. 22 0 I/CLKII I I I I I I GND Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/OE 91 1 1 3 10 11 20I/CLK I I I I I I I I GND Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/OE GAL16V8 Top View LCC CERDIP GAL 16V8 Copyright © 2010 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 16v8mil_04 Functional Block Diagram Pin Configuration

Specifications GAL16V8D-7/10/883 Devices have been discontinued. VIL Input Low Voltage Vss – 0.5 — 0.8 V VIH Input High Voltage 2.0 — Vcc+1 V IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 μA IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——1 0 μA VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V IOL Low Level Output Current — — 12 mA IOH High Level Output Current — — –2 mA IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25°C –30 — –150 mA ICC Operating Power VIL = 0.5V VIH = 3.0V L-7/-10 — 75 130 mA Supply Current ftoggle = 15MHz Outputs Open 1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T A = 25 °C Recommended Operating Conditions Supply voltage (VCC) Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. TYP . 3 MAX. UNITS Absolute Maximum Ratings(1) Case Temperature with 1.Stresses above those listed under the “Absolute Maximum Rat- ings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).

Specifications GAL16V8D-7/10/883 Devices have been discontinued. tpd A Input or I/O to Combinational Output 1 7.5 2 10 ns tco A Clock to Output Delay 1617n s tcf2 — Clock to Feedback Delay — 6 — 7 ns tsu — Setup Time, Input or Feedback before Clock ↑ 7— 1 0 —n s th — Hold Time, Input or Feedback after Clock ↑ 0—0—n s A Maximum Clock Frequency with 76.9 — 58.8 — MHz External Feedback, 1/(tsu + tco) fmax3 A Maximum Clock Frequency with 76.9 — 58.8 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 100 — 62.5 — MHz No Feedback twh — Clock Pulse Duration, High 5 — 8 — ns twl — Clock Pulse Duration, Low 5 — 8 — ns ten B Input or I/O to Output Enabled 1 9 — 10 ns B OE to Output Enabled 1 7 — 10 ns tdis C Input or I/O to Output Disabled 1 9 — 10 ns C OE to Output Disabled 1 7 — 10 ns PARAMETER UNITSTEST COND1. DESCRIPTION 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS CI Input Capacitance 10 pF V CC = 5.0V, VI = 2.0V CI/O I/O Capacitance 10 pF V CC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. -10 MIN. MAX. MIN. MAX. Capacitance (TA = 25°C, f = 1.0 MHz) AC Switching Characteristics Over Recommended Operating Conditions

Specifications GAL16V8D/883 Devices have been discontinued. VIL Input Low Voltage Vss – 0.5 — 0.8 V VIH Input High Voltage 2.0 — Vcc+1 V IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –10 μA IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——1 0 μA VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V IOL Low Level Output Current — — 12 mA IOH High Level Output Current — — –2 mA IOS1 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25°C –30 — –150 mA ICC Operating Power VIL = 0.5V VIH = 3.0V L -15/ -20/-30 — 75 130 mA Supply Current ftoggle = 15MHz Outputs Open 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T A = 25 °C Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. TYP . 2 MAX. UNITS Absolute Maximum Ratings(1) Case Temperature with 1.Stresses above those listed under the “Absolute Maximum Rat- ings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Recommended Operating Conditions Supply voltage (VCC)

Specifications GAL16V8D/883 Devices have been discontinued. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS CI Input Capacitance 10 pF V CC = 5.0V, VI = 2.0V CI/O I/O Capacitance 10 pF V CC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. tpd A Input or I/O to Combinational Output 3 15 3 20 3 30 ns tco A Clock to Output Delay 2 12 2 15 2 20 ns tcf2 — Clock to Feedback Delay — 12 — 15 — 20 ns tsu — Setup Time, Input or Feedback before Clock ↑ 12 — 15 — 25 — ns th — Hold Time, Input or Feedback after Clock ↑ 0— 0— 0 —n s A Maximum Clock Frequency with 41.6 — 33.3 — 22.2 — MHz External Feedback, 1/(tsu + tco) fmax3 A Maximum Clock Frequency with 41.6 — 33.3 — 22.2 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 50 — 41.6 — 33.3 — MHz No Feedback twh — Clock Pulse Duration, High 10 — 12 — 15 — ns twl — Clock Pulse Duration, Low 10 — 12 — 15 — ns ten B Input or I/O to Output Enabled — 15 — 20 — 30 ns B OE to Output Enabled — 15 — 18 — 25 ns tdis C Input or I/O to Output Disabled — 15 — 20 — 30 ns C OE to Output Disabled — 15 — 18 — 25 ns 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. -20 MIN. MAX. -15 MIN. MAX. PARAMETER UNITSDESCRIPTIONTEST COND1. -30 MIN. MAX. AC Switching Characteristics Over Recommended Operating Conditions

Specifications GAL16V8/883 Devices have been discontinued. Registered OutputCombinatorial Output OE to Output Enable/DisableInput or I/O to Output Enable/Disable fmax with Feedback Clock Width COMBINATIONAL OUTPUT VALID INPUTINPUT or I/O FEEDBACK tpd COMBINATIONAL OUTPUT INPUT or I/O FEEDBACK tentdis CLK (w/o fb) 1/fmax twltwh INPUT or I/O FEEDBACK REGISTERED OUTPUT CLK VALID INPUT (external fdbk) tsu tco th 1/fmax OE REGISTERED OUTPUT tentdis CLK REGISTERED FEEDBACK tcf tsu 1/fmax (internal fdbk) Switching Waveforms

Specifications GAL16V8/883 Devices have been discontinued. fmax with Internal Feedback 1/(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See Figure 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition R 1 R2 CL A 390 Ω 750Ω 50pF B Active High ∞ 750Ω 50pF Active Low 390 Ω 750Ω 50pF C Active High ∞ 750Ω 5pF Active Low 390 Ω 750Ω 5pF TEST POINT C *L FROM OUTPUT (O/Q) UNDER TEST +5V *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE R 2 R 1 REGISTERLOGIC ARRAY tcotsu CLK fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. REGISTERLOGIC ARRAY CLK tsu + th CLK REGISTER LOGIC ARRAY tcf tpd fmax Descriptions Switching Test Conditions

Specifications GAL16V8/883 Devices have been discontinued. MIL Process /883 = 883 Process Package PowerL = Low Power Speed (ns) XXXXXXXX XX X X X Device Name D = CERDIP R = LCC GAL16V8D Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recom- mended. Part Number Description 1. Discontinued per PCN #06-07. 2. Discontinued per PCN #05A-10. #gniredrO dpT )sn() sn( )sn( )sn() sn( usT )sn() sn( )sn( )sn() sn( ocT )sn() sn( )sn( )sn() sn( ccI )Am() Am( )Am( )Am() Am( egakcaP3 88-DTS-LIM# DMS 5.77 6 0 31P IDRECniP-023 88/DL7-D8V61LAG 2 AR7093898-2695 031C CLniP-023 88/RL7-D8V61LAG 1 A27093898-2695 010 17 0 31P IDRECniP-023 88/DL01-D8V61LAG 2 AR4093898-2695 031C CLniP-023 88/RL01-D8V61LAG 2 A24093898-2695 512 12 10 31P IDRECniP-023 88/DL51-D8V61LAG 2 AR3093898-2695 031C CLniP-023 88/RL51-D8V61LAG 2 A23093898-2695 025 15 10 31P IDRECniP-023 88/DL02-D8V61LAG 2 AR2093898-2695 031C CLniP-023 88/RL02-D8V61LAG 2 A22093898-2695 035 20 20 31P IDRECniP-023 88/DL03-D8V61LAG 2 AR1093898-2695