G121600N000 SII | Alldatasheet
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- 4.5 Electrical Characteristics «ssssssssscsssesssssecccsssecensessennsessanecenscecnsesssnseesnsesss
- 1.6 Optical Characteristics ssssssssssssssvsssssssssensnnnnnsccssceseeeeccsenseceeececeesennees
- 1.7 LC Panel Life Time csessessseseesssseesvssssensssscensenesnsssncencencensenssnsanennssncsncneenes
- 1.8 Dimensions sssseceesseeeeeseeeecesssssssenssesessessesessnssasssessseessooseneeeeaeneeressaserenes
- 2.1 Block Diagram -sss+ssesssseesessecsssesssnsensnnesssssneecssnsscssnssssnecennsssnnsccensesenneees
- 2.2 Segment Drivers (HD61202) svssssrsssssersssssesssesssssssssnsscenscssssecensecssneessnees
- 2.3 Common Driver (HD61203) ssrsssssssssrvssesersseecrssessssnsccensccensecsanecsnnsscnnens
- 2.4 Bias Voltage Generator —-sssssssssssssssssessesseeseseeensennnnnnnnsnseseccnnsnnnnnnenssssees
- 3.2 Timing Characteristicsessssssssssssssssseeeesssssseceecennnsssececeessnnnnnnneeceeceeeennnes
- 3.4 Instructions ssevunsececsseuanesonesconsessusueneserenensonssavanceararereveresereses
- 3.5 Contrast Adjustment and Power Supply Example srrrrrrssrsereersseeesssceseeeece
LIQUID CRYSTAL DISPLAY MODULE G121600N000 USER’S MANUAL Seiko Instruments Inc.
This manual provides technical information covering functions and operational instructions for the G1216 liquid crystal display modules made by Seiko Instruments Inc. Please read through this manual before operating the product. Distribution of this manual to third parties for any purpose other than operation of the product is prohibited. The descriptions herein are subject to change without prior notice. Revision Record Version Revision Date
1 Original December 1993
Copyright® 1993 by Seiko Instruments Inc. Printed in Japan
41, GENERAL 1.1. General The G1216 is a very thin LCD module on which a full-dot matrix LCD panel and a CMOS IC driver are integrated. The LCD panel used here features wide viewing angle and high contrast. This full dot configuration allows a wide variety of patterns to be displayed depending upon the input data. The display position is the intersection point of the matrix transparent electrodes. This prevents display distortion and displacement. Incorporating a display RAM and a display timing signal generator into the G1216 allows for direct connection with the MPU circuit without using an LCD controller.
1.2 Features
+ 128x 64 full dot matrix configuration * 1/64 duty, 1/9 bias + Two 4096-bit internal display data RAMs + Aninternal display timing signal generator + 8-bit parallel interface + Instructions: Display Data Read/Write, Display ON/OFF, Display Start Line, X-Address (Page) Set, Y- Address Set, and Status Read. + Two types of power supply: Vpp = +5V, Vic + Reflective, gray mode + Positive display Display data “H”: Display ON: blue display color Display data “L”: Display OFF: gray background + Awide operating temperature range -1-
1.3 Absolute Maximum Ratings
Vss = OV [tem | Symbot_ | Gonaions [win [wo] Unie] rower woe vn | ose | at voltage 50 1096RH [input vottage | vw | | =0.3 | Vow os |v | [weegiie | tee | server | ve | oe 1 temperature | Tg | = | -30 S| +80 |e Storege | = | seems | +20 | +85 hamidity [= st000ms | +20 +65 | RH
1.4 Mechanical Characteristics
| Viewingarea (HxV) mm] | 600x325 [weigh tg 5m H: Horizontal V: Vertical 1: Thickness (max.)
1.5 Electrical Characteristics
Vop = 5V£5%, Vss = OV, Ta = —20°C to +70°C | item symbot [conditions] min. | typ. | Max | unit_| Sage RR eee ff eT vonage! [tow [vue | = fo [= [03vo0 |v _ f itopes te ff 28 fee votege? [tow | vir [| = sf o | - | os | v | output [High | Vou | lon=- 205. | 24 | - | - |v | voltage | vc [= 20] -a2 | -30 | vv | a consumption’ Mes-e2v | = [18 | 40 | ma_| [ Feneteweny [tw [| = Let = | | 1 Applied to RST. 2 Applied to DBo to DB7, E, R/W, D/I, CS1 and CS2. 3 Applied to DB to DB7. 4 Display patterns: checkered patterns. -2-
1.6 Optical Characteristics
1/64 duty, 1/9 bias, fram = 71.4Hz, Vopr = Vpp - Vic, LED backlight: OFF [tem [sim | consion [rene [min | typ | mas | unt | Remer| opr = 13. r- Viewing angle ° [4 | = Degree Refer to © = 270° 25 Vopr = 13.2 V |e | - | - | Q@= 0° Contrast s = | meee | Vopr = 13.2V rc oor ee Response time > Note 4 Vopr 14.1V [= | 2300 | 3500 | Measuring instrument : Canon illuminometer LC-3S Note 1: Definition of angle @ and @ Note 2: Definition of viewing angles 61 and 62 Light Z (8=0") gb 62 Lo Contrast C Y (B= 180") EEX 20 | » . j----- Ko GARG al x’ ” X(B=90%) ! ' zs a \\S Viewi z ° iewing angle '¥(@=0°) Remark: The optimum viewing angle by (@=90°) visual inspection and angle @ at Cmax do not always match. -3-
Note 3: Definition of contrast (C) Note 4: Definition of response time c Brightness of non-selected dot (reflection) Bz = “Brightness of selected dot (reflection) By ' Brightness for selected om | By dot Wii Non-selected Non-selected stati i status selected status splay OFF) } Brightness curve for non- Light 10Z brightness ' selected dot t ry (reflection) ! . 90% i Brightness 1 By ' iS
5 Dark Toa ton
Operating Vopr : Operating voltage ton: Response time (rise) voltage(V) ferm : Frame frequency toes: Response time (fall) Note: Measurement must be made using a transmissive LCD panel. 1.7. LC panel life time ife ti 25°C + 10°C 1 m Life time’ <65%RH 100,000 or more hrs
1 Definition of life time: the time up to occurrence of any of the following:
+ Contrast reduces to 30% of the initial value. + Current consumption becomes three times the initial value. + Orientation deteriorates significantly. + The display malfunctions. -4-
1.8 Dimensions
Unit: mm General dimensional tolerance: + 0.5 750 2s es Sin alg | 20 | oe | - a | ae 1 es: 3 CE 2 ! C= xe a | ona | “| 5| & a\\s ' ‘ s ' : \\ 4-R10 H | | <2 HKo00000000000000000¢e ay 3 | Fa 2 2. 2 Y )- 01.0 sl 043 254 x 19 = 4826 (1337) oo cere Figure 1 Dimensions VO terminal functions [wo [sym [Functions | [No] sym [Functions | 1 | Vo | Power supply voltage: +5.0V [11 | pe, | Data bus (MSB) GND: OV [12 | cs1_| Chip select (1) LC drive voltage Chip select (2) [4 | DB» | Data bus (LsB) [14 [rst [Reset ['s | pe, | databus [ss {wf aesarnte [6 | pe, | databus Data/Instruction [7 [pp; [databus | La | [enable ['s [bb, [databus | «18 | eno | Frameground) [9 | os; [batabus | Lt | vc P= [io | pa [patabus | Lo Pc [= 1 FGND is connected to the metallic frame of the module. Use this frame when grounding. -5-
- CIRCUIT CONFIGURATION
2.1 Block Diagram
This product consists of two HD61202 segment drivers, an HD61203 common driver and a bias voltage generator. Figure 2 shows the block diagram. DBp to DB7 pocro rrr RST, RW, D/LE ' 1 t 1 cs2 + = i I t cst 7 / ! 1 1 Mic t Bias Voltage [Var Ver Var Vt \\ ! Generator il i‘ \\ i 1 1 1 H Va Mr ' ve oy UT | ! Ve { H Vt Segment Driver 1 Segment Driver2 |} Vsg ' 1 ' 1 t i \\847 847 t 1 1 1 i { : ' ! Common Driver le 12864 full dot matrix LCD ' ' ! t 1 ' 1 1 1 1 t ' Figure 2 Block Diagram
2.2 Segment Drivers (HD61202)
The segment driver is a 64 drive output CMOS IC. The G1216 is driven with the panel divided into two right and left displays. A segment driver controls the divided screen. 8 bits of data transmitted from the MPU are saved in the internal display RAM, and the segment signal is generated to drive the LC- 1 bit of display RAM data corresponds to 1 dot lighting or non-lighting on the LC panel. -6-
2.2.1 Block Diagram (Segment Driver)
RST Vop Vss Vic CS RW Dil & DBoto DBy Segment Driver ee ee ee ey Interface Control - a i Input and Output Buffer ' Busy Flag I I Output Input Instruction Register I Register Register i a er Display ON/OFF Display Start Line X, Y-Address Register Counter 2-Address Display Data RAM Counter a 4096 bit YT Display Data Latch | ef Se Va M fete eee eerie $1 42 FRM cL? v1 Y2 64 Va : Vi Figure 3 Segment Driver -7-
2.2.2 Functions and Operations of Main Blocks
(1) Interface Control Unit The interface control unit consists of the following blocks: @ Input and output buffer @ Input and output register @ Instruction register The above blocks are selected according to the following combinations of R/W and D/I signals: Output Register Read internal Operation (Display Data RAM —> Output Register) Input Register Write Internal Operation (Input Resister > Display Data RAM) fo [| 1 | Busy Check and Status Read [oo [0 | instruction SOS @ Input and output buffer The data is transmitted through eight data buses (DBp to DB7). DB7 -----+ MSB (most significant bit) DBo ---++ LSB (least significant bit) The data can be input and output only when the Chip Select is selected. Therefore, if the Chip Select is not selected, the internal condition remains unchanged and instruction will not be executed, even when changing the signal of the input terminals excluding the RST (reset) terminal. Note that the RST operates regardless of CS1 and CS2. @ Input and output register This product is provided with an input register and an output register so that the product can interface with MPUs having speed differing from the internal operation. © Input register The input register is a register that is used for temporarily storing the data to be written in the display data RAM. The data to be written from the MPU to the input register will be automatically written in the display data RAM through internal operation. When the Chip Select is selected and R/ W = 0, D/1 =0, the data is written in the register, synchronized with the fall of signal E. © Output register The output register is a register that is used for temporarily storing the data to be read from the display data RAM. -8-
In order to read the content of the output register, the Chip Select must be selected, D/I must be 1, and R/W must be 1. When executing the “Read” instruction, the contents of the output register stored at that time are output during the time that "E” is 1. When “E” falls, display data of the currently indicated address is written in the output register. After that, the address advances by one. The contents of the output register are rewritten by the Read instruction. The data is retained by the address set or other instructions. Accordingly, when performing the address set, and next executing the Read instruction, the data of the specified address is not output and the data of the address which is specified is output at the second data read time. Therefore, when setting the address, adummy read is needed once. See Figure 4. D/I R/W LJ e_f[LI LILI LEP teUr tit Lil Address Output Register [ Naddressdata__| N+1addressdata Busy Address | 3, Data Read| gp DataRead| g, Data Read DBp to DB7 Check | Set Chek (dummy) Check (Naddress cheek (N+ 1 address (Address data) data) Figure 4 Read Timing (2) Busy flag The status when busy flag is “1” means that the module is operating internally. Instructions other than he Status Read are not available at this time. The busy flag is output to DB7 by the Status Read instruction. Ensure that the busy flag is “0” before executing the instruction. e — ff VL KT ausy > 4 3 Fe Stars Fy F¢ is frequency of $1 or g2 (1/2 the source oscillation frequency of HD61203): 215 kHz typ. Figure5 Busy Flag (3) Display ON/OFF Flip/Flop The display ON/OFF Flip/Flop is a flip-flop function that determines whether the display data corresponding to the RAM data is output to the segment on the LCD (ON status ) or goes to all nonlit status regardless of the RAM data (OFF status). This is controlled by the display ON/OFF instruction. When the RST signal becomes “0,” the display goes to OFF status. This flip-flop status is output to DBs by the Status Read instruction. Even when performing display ON/OFF, the data inside the RAM is not affected. -9-
(4) Display start line register The display start line register is a register which determines the line address (see Figure 6) for which data is displayed on the top line of the LCD screen when displaying the contents of the display data RAM on the LCD screen. It is also used to scroll the display. The 6 bit (0 to 63) display start line information is written in this register by the Display Start Line Set Instruction. The contents of this register are transmitted to address counter Z at “H” level of the FRM signal (common driver output) which indicates the display start on the screen. (5) Z-address counter The Z-address counter generates the address to output the display data synchronized with the common signal. This is a 6-bit counter which counts at the fall of the CL signal (common driver output). The contents of the display start line register are preset to the Z-address counter at “H” level of the FRM signal (common driver output). (6) Display data RAM The display data RAM is a RAM that stores the display dot data. 1 bit of RAM data corresponds to lighting (data = 1) or non-lighting (data = 0) of 1 dot of the display on the LCD screen. Figure 6 shows the relationship between the address and data inside the RAM on either the right or left screen (64x64 dots). In this case, the display start line is 0. -10-
(Display start line: 0) com2 eee eee eee com3 wee eee eee, CcOM4 cOMS cOM6 cOM7 Common driver coms output com9 X1 to X6q i Sesee toe it ‘ --— comez— i [ [ [| [ T| come3 | | Ty comea{ | | [] fT TT Segment driver output Y;toYgg ——>1 62/6316 Line address Datainside DBo(LSB) JORG ee ToToT1 Ftineo displayRAM pp, rH fefefols| eee [olo][1}-Line1 X- address DB: retfetefotst fototiF tine | (pase) DB3 mete foto yn [i fo[s| DB, more lols {s| X=0 DB. Hol LL tt “Toyotas | pa X=1 tit ' X=2 ols fofoto|"--"-----fofofo] _ ifififafat fofofortines2z f°~ Lofofofofo] ______ [ofofoF tine ss Y-address Yo Y1 2 Y3 Ya YorYe2Ye3 Figure 6 Relationship Between Display and Data Inside Display RAM (7) X, Y- address counter X, Y-address counter is a 9-bit counter which gives the address of the internal display data RAM. It is necessary to set the X-address counter of the three upper bits, and the Y-address counter of the six lower bits using differing instructions. @ X-address counter Address counter X is a simple register that is not provided with a count function. The address is set by instruction. -11-
© Y-address counter This counter sets the address by instruction and is automatically advanced by the read/write operation. Counting is performed by looping the values 0 to 63.
2.3 Common driver (HD61203)
The common driver is a 64 drive output CMOS IC. Incorporating an oscillation circuit, this driver generates the common signal and timing signals (LC AC drive control, and one-frame timing signal) necessary for the LC display, and controls the display by supplying the timing signals to the segment drivers.
2.4 Bias voltage generator
Six levels of standard voltage Va to Vf are applied to the drivers as a bias voltage. This voltage is generated by resistance division of Vopr and driven by a voltage follower through an operational amplifier. Vop o o Va R. Cc ' PH © Vb R. ¢c 4 pH o Ve Ry CT c [> o Ve Operational 1 ¢ Ry Amplifier Vic © o V+ 1/9 bias: Ro= (9-4) Ri = 5Ry Figure7 Bias Voltage Generator -12-
3.1 Terminal Functions
Table 1. Terminal Functions : Write (R/W = 0):Latches data of DBp to DB7 at the fall of E. an instruction after reset is released.
3.2. Timing Characteristics [nem [ Symbol [win [ye [Max [unit | note | [eceerime | teve | tooo | - [=| ns | 2 | [epurewianen | Pwen | 450 | - |] ns | 1.2 | [epubewarney | Pee | 450 | - | =| ns | 2 | [erseime te fas | ns | | [eainme tte TT fas] ns |_| | Addressetuptime | tas | tao | || ns | 2 | [adéresrowstine | tan | to | [ns [2 | [osasetpime | tosw_ | 200 | - | =| ms [1 [datadeiaytime | toon | = | - | 320] ns | 2.3 | Dataholdtime during read | tone | 20 | - | -| ns | 2 | Note 1: | When the MPU writes: Note2: | When the MPU reads: teve teye OVY| tas, | i R/W K D/l 0.8y, tosw: Dil o8y Bp to DBy rr DBp to DBy 7 ae Note 3: Load circuits (DB to DB7) b, SR Ry = 2.4k0 Test point M R =11k0 - c R Do C = 130 pF (including jig capacity) a Da Diodes D1 to D4 are 1$2074®. -14-
3.3. Reset Function Setting the RST terminal to a low level when the power is on allows for initial setup. @ Display OFF @ Display start line register: Set address 0. While the RST remains at a low level, instructions other than the status read cannot be accepted. Execute other instructions after confirming that DB, =0 (reset release) and DB7=0 (ready) , using the status read instruction. The power conditions for power-on initial setup are as follows:. Preecine [ter | v9 | - | - | =| [swine | te | - | - [| [= | 4.5V. Voo tasty) tr 0.7Vpp RST ee If the RESET is executed during operation, retention of the contents of all registers (excluding an ON/OFF register) and the RAM is not guaranteed. Always set them again. -15-
3.4 Instructions
3.4.1 General
Instructions are listed on Table 2. Instructions other than the Status Read instruction will not be executed if they are sent while another instruction is already being executed. The busy flag is “1” when executing the instruction. Check whether or not the flag is “1” before transmitting the instructions from the MPU. “ Table 2 List of Instructions Function | [ee er [so [os [oon [ou [so] Turns ON/OFF total display. Data and 1 | Display intgral status in the display RAM remain unchanged. ON/OFF 1: ON S OFF . . Determines the RAM line to be displayed on 2 | Display Display start lines the top line (COM1) on the display. start line (0to63) X-address X-address(page) | Sets the X-address of the RAM (page) in (page) set 1 (0to7) the X-address (page) register. i \\M in the Y-< Y-address yeaddress Set Yendares of the RAM in the Y-address set (0to 63) : R Reads the status. 5 8 On] eE RESET 1: Reset 0: Normal tatus read ¢ 11s ON/OFF 1: Display OFF 0: Display ON y OFF) E BUSY 1: during internal operation T 0: READY status Writes data DBo (LSB) to | Accesses the a DB, (MSB)onthedata | RAMin which ‘splay Write Data bus into the display address has been data write RAM. specified beforehand. After that the Y- Reads data DBy (LSB) to | address Displa: DB, (MSB) from the advances by one. 7 | Display Read Data display RAM into the data read data bus. Note: The BUSY time varies depending upon the frequency F¢ (:215 kHz (typ.)) of 41, 42(1/F 4 S Tausy S 3/F¢).
3.4.2 Detailed explanation
(1) Display ON/OFF cole [ofofofofsfr]i[i]r fol Turns the display ON when D = 1, and OFF when D=0. When the display is turned OFF by D=0, the original display appears if D is set to 1 because the display data is retained in the display data RAM. -16-
(2) Display start line cole [oTo[r{itajafaltajala] ~—Upper bits Lower bits —> Sets the display data RAM line address expressed with binary AAAAAA in the display start line register. When displaying the content of the display data RAM, the display data on the line addresses which are set in the register is displayed on the top line an the LCD screen. For address configuration inside the display data, refer to Figure 6. Figure 8 shows display examples of start lines Oto 3. comi ~~ com1 a eee come com2 Ean com3 com3 EEE COM4 com4 coms coms it ty come coms iT Ty com7 com7 4 [| [I | coms come — [UU] | comg coma —_] com10 comi0 an - i . : - i - i comso comeo—j_| Ht I | comet come: + 9 [ [| come2 come2 comea veeeeeene comes —_] Cte. Display start line =0 Display start line =1 comi ne eee com1 eae coma | | {| com2 com3 coma nnn coma nnn coma itty coms aan coms — | [TT | coms + _| | coms En coma ptt coms nnn com10 | TI com10 I] - H . ; 20 [] i . Tq i comeo— | comeo comet comer [ ] || | comes —|_] [| come3 nan comea fn eee come4 eee Display start line =2 Display start line = 3 Figure8 Relationship Between Display Start Lines and Displays -17-
(3) X-address (page) set code LofoTifoTs[i[rfasala] —~<—upper bits Lower bits > The display data RAM “X” address (page) which is expressed with binary AAA is set in the X-address register. Following write/read operations from the MPU are performed on the specified X-address (page) until the next X-address (page) set is performed. The configuration of display data RAM and X-address is shown in Figure 9. (4) Y-address set coee [oloyTo[:[ajayajaljala] “upper bits Lower bits 2 The display data RAM Y- address which is expressed with binary AAAAAA is set in the Y-address counter. After that the Y-address counter advances by one each time write/read is performed from the MPU. The configuration of the display data RAM and Y-address is shown in Figure 9. Y-address DBy to PageO X=0 DB, DBy to Page 1 X=1 DB, DBy to Page6 X=6 DB, DBy to Page7 X=7 DB, ) Figure9 Display Data RAM Address Configuration -18-
(5) Status read code [1 | 0 Tou] 0 Touorf usr] o [oJ o [0 | BUSY: When BUSY = 1, it means that the the module is operating internally and the next instruction is not accepted until BUSY = 0. After confirming that BUSY = 0, it is necessary to perform the next write. ON/OFF: Indicates that the display is OFF when ON/OFF = 1. Indicates that the display is ON when ON/OFF = 0. RESET: _ Indicates that initial setup is performed by the RST signal. Indicates that the initialization is being performed when RESET = 1 and instructions other than the Status Read instruction are not accepted. When RESET = 0, initialization is completed and operation status is normal. (6) Display data write code [oT + To[Toto[ojo{ojo]o|] Writes 8-bit binary data DDDDDDDD in the display data RAM. After the write is completed, the Y- address is automatically advanced by one (7) Display data read cove [1] i ]oTofololo]{ojo]o| ~— Upper bits Lower bits > Read 8-bit binary data DDDDDDDD from the display data RAM. After read is performed, the Y- address is automatically advanced by one. A dummy read is necessary once, immediately after the address set is completed. For details, refer to segment driver output register section. -19-
3.5 Contrast Adjustment and Power Supply Example
The LC panel viewing angle and display screen contrast are greatly affected by the ambient temperature. The recommended LC drive voltage (Vopr) at each temperature is given below. Vopr is a value at which the best display is visually obtained. This value does not always correspond to the value at which the best contrast (Cmax.) is obtained. A contrast adjustment circuit example is shown below: Vv (| jes . ee 5V Cc Rg=1.2k0 Vss 8 ( bl ) Ry (variable resistor 2 ¥ [LN =10kO 12V Vic C1,C2 = 10 pF Figure 10 Contrast Adjustment
3.6 MPU Connection Diagram
010 07 — pot007 AT AT ~ D8 008, A0toA15 aoe Renal oad ca BO Co E [= ce " w irs | — — B2 DA i | i a ey ed ee i é 8 BS cs2 Vop Vss Vic Figure 11 Example of Connection to Z80A -20-
4, PRECAUTIONS Safety + Ifthe LCD panel is damaged, be careful not to get the liquid crystal in your mouth. If the liquid crystal touches your skin or clothes, promptly wash it off using soap and plenty of water. Handling + Avoid static electricity, as it will damage the CMOS LSI. + The LCD panel is made of plate glass. Do not hit or crush it. + Donot remove the panel or frame from the module. + The polarizer of the display is very fragile. Handle it very carefully. Mounting and design + Mount the module by using the specified mounting parts and holes. + To protect the module against external pressure, place a transparent plate (e.g., acrylic or glass) on the module, leaving a small gap between the display surface and transparent plate. trExample Small gap Exterior face Transparent plate 4 PP a Pd, io—Ek_ oo OT oo screw + Design the system so that no input signal is given unless the power-supply voltage is applied. + Keep the module dry. Avoid condensation to prevent the transparent electrodes from being damaged. Storage + Store the module in a dark place, where the temperature is 25°C + 10°C and the relative humidity below 65%. + Do not store the module near organic solvents or corrosive gases. + Keep the module (including accessories) safe from vibration, shock and external pressure Cleaning + Do not wipe the polarizer with a dry cloth, as it may scratch the surface. . + Wipe the module gently with a soft cloth soaked with a petroleum benzine. + Donot use ketonic (ketone) solvents (ketone and acetone) or aromatic solvents (toluene and xylene), as they may damage the polarizer. -21-
-A- -B- -C- -D- -E- -Fe -l-
-L- -O- -P - -R- Reset cece eee e eee eeee eter eeeeeeeeees 6,8, 13,15 -S- StOPAGe eee ete e eect eeeee eee etetereeee 21 -T- -V- -W- -X- -Y- -Z-
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