G121300N000 SII | Alldatasheet
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Datasheet sections
- 1.2 Features ccvvescsvsscssescssessssssessessssssssssnsessesnsssssssscsssssssssnsessnsecssnecsssneensanss
- 1.3 Absolute Maximum Ratings ssssssssssssssssssssssssssssssseseececcencecennannnesssoesnnees
- 1.4 Mechanical Characteristics sssssssssssssssessssssesssecssesssesssecenesssessnessnecenees
- 1.5 Electrical Characteristics cssvvssssssssssessessssssssrnsesssnnsesesnsesnssssssneennsnessnes
- 1.6 Optical Characteristics ---ssrssssssssssssseseesessssseneccnsesnnecsnssenccnnesencenesnees
- 1.8 Dimensions — «ssssvsssesssseeenecrssernsccsnecenvecssvenssesssvcssvessssssncenssenecasessnessness
- 2.1 Block Diagram --++sssssssssssssssssssssnsssnnceeseeeeesseessnununnansnnnnnnnnnnnnnnnnnnennnenees
- 2.3 Common Driver (HD61203) srsssssersseseevssessssseesssnecnsssecsnnsesssnsscssnesssnsesse
- 2.4 Bias Voltage Generator ssssssssssseeeeeeeseesensssnnnnnnnnncenencencnncecereceeereeeeereeee
- 3.1 Terminal Functions csrsrsssssssssssssssessseossssessssssesssssesssnsecssneccessscssnnesssasesse
- 3.3 Reset FUMCRION — «sseseesseseeccessseseccrccensneresseecnnnvereccenenseerserenssessessneseessssee
- 3.5 Contrast Adjustment and Power Supply Example sssrrersssersssessesesseresees
- 3.6 MPU Connection Diagram ssssssssssseesessennssssssnnnnnesecnsesensesssecsecensecents
LIQUID CRYSTAL DISPLAY MODULE G121300N000 USER'S MANUAL Seiko Instruments Inc.
ANUS 16 1o¥UuUU-2UUE This manual provides technical information covering functions and operational instructions for the G1213 liquid crystal display modules made by Seiko Instruments Inc. Please read through this manual before operating the product. Distribution of this manual to third parties for any purpose other than operation of the product is prohibited. The descriptions herein are subject to change without prior notice. Revision Record Version Revision Date
1 Original December 1993
Copyright© 1993 by Seiko Instruments Inc. Printed in Japan
AAIN.IVU.G 12 12UUINUUU-20UE 1. GENERAL
1.1 General
The G1213 is a very thin LCD module on which a full-dot matrix LCD panel and a CMOS IC driver are integrated. The LCD panel used here features wide viewing angle and high contrast. This full dot configuration allows a wide variety of patterns to be displayed depending upon the input data. The display position is the intersection point of the matrix transparent electrodes. This prevents display distortion and displacement. Incorporating a display RAM and a display timing signal generator into the G1213 allows for direct connection with the MPU circuit without using an LCD controller. 1.2. Features + 128 x 32 full dot matrix configuration + 1/64 duty, 1/9 bias + A4096-bit internal display data RAM + Aninternal display timing signal generator + 8-bit parallel interface + Instructions: Display Data Read/Write, Display ON/OFF, Display Start Line, X-Address (Page) Set, Y- Address Set, and Status Read. + Two types of power supply: Von = +5V, Vic + Reflective, gray mode + Positive display Display data “H”: Display ON: blue display color Display data “L”: Display OFF: gray background - Awide operating temperature range -1-
Rie te lovunvueoeUk, 1.3. Absolute Maximum Ratings Vss = OV [en symbat [contort [win [tae | ni | Taz2sc |_-03 | 70 |v voltage 50+ 10%4RH [input vortage | vw | | -03 | Vo 03 | vv | tempersure | Tag | - | 30 | + aoc eee ramidity [= | st000hs | +2065 | RH
1.4 Mechanical Characteristics
| Viewingarea (Hxv) mm | 600x213 | Activedisplayarea(Hxv) Imm] | 55.01 16.29 H: Horizontal V : Vertical T : Thickness (max.)
1.5 Electrical Characteristics
Vpp = 5V£5%, Vss = OV, Ta = -20°C to +70°C [tem symbot [conditions | in. | typ. | Max | Unit | Input Yaigh | Ve [= 07% | = | Yoo | vf eS ee input [High | vr [= | 20 | | voo |v | ee eee output [High | Vow | tow=-205.a | 24 | - | - | v | ie eae te pee [rewerwony [vee fda ee ee 1 Applied to RST. 2 Applied to DBg to DBz, E, R/W, Dil, CS. 3 Applied to DBg to DB7. 4 Display patterns: checkered patterns. -2-
1.6 Optical Characteristics
1/64 duty, 1/9 bias, ferm = 140 Hz, Vopr = Vpp ~ Vic, LED backlight: OFF [em [asm | conaons [ron [ min | to. | mex | unt [ remar| opr = 13. Viewing angle c pa} Degree Refer to 22.0 Pa |o=z0 jase Pao =f | Q= 0° ¢ 250 Notes Vopr = 13.0V 9 0, pees [2p SL Response time = Note 4 Vopr= 14.4V | = | 1300 | 2000 | Measuring instrument : Canon illuminometer LC-3S Note 1: Definition of angle @ and © Note 2: Definition of viewing angles 61 and 62 Light Z (8=0°) ib 62 Lo Contrast C Y (= 180") Ee 20 | aw? LCD panel H ! » OC ee oso Qe SS 3 35 2 ~ Viewing angle Y(B=0% Remark: The optimum viewing angle by (@=90°) visual inspection and angle @ at Cmax do not always match. -3-
AN.NO.G1213UUNUUU-3DUE Note 3: Definition of contrast (C) Note 4: Definition of response time c Brightness of non-selected dot (reflection) B Brightness of selected dot (reflection) By ' Brightness for selected ) te dot 4 tea - Non-selecte Non-selected stat { status i lec d status Non-selacted atus , Brightness 1 curve for non- Light ~ I 10% Brightness \\ selected dot (reflection) ! 100% 90% ' Brightness 1 By v . Dark Tt 0 b>] ton bem tot Operating Vopr : Operating voltage ton: Response time (rise) voltage(V) fenm : Frame frequency toy: Response time (fall) Note: Measurement must be made using a transmissive LCD panel. 1.7. LC panel life time fo time! 25°C + 10°C Life time <6S%RH 100,000 or more hrs
1 Definition of life time: the time up to occurrence of any of the following:
+ Contrast reduces to 30% of the initial value. + Current consumption becomes three times the initial value. - Orientation deteriorates significantly. + The display malfunctions. -4-
AN.NO.U 12 1SUUNUUU-3DUE
1.8 Dimensions
Unit: mm General dimensional tolerance: + 0.5 750 25 25) 3 jes 8 - ne . s 3 “5 ml} 7 &, al? [ “14 WId 1 ol al ' t | 3/8 | | 3 | a] ol 8 H 4-R10 | | 5) = ( Lee : pT } |
5 No00000000000000000¢0-4 dy 3 |
% 1337 254 X 19 = 48.26 (1337) wf " E - oa Figure 1 Dimensions W/O terminal functions [wo [sym [functions | [No | sym. [Functions | | 1 | Vp | Power supply voltage: +5.0V Data bus (MSB) [2 | vss | cnp:ov [2 [cs [chipselece [13 | ast [Reset [4 [DB _| bata bus (Ls8) [14 | rw [Readwrite [-s | pe, | databus Data/instruction | 6 | pe, | databus | [enable [7 | be; [databus | a7 | ono | Framegroundt [e | bp, [databus | [te | e Po [9 | pas |batabus | ft Pc Pe [10 | bas [patabus | Leo nc fo 1 FeNp is connected to the metallic frame of the module. Use this frame when grounding. -5-
AN.NO.G1213UUNUUU-3DUE 2. CIRCUIT CONFIGURATION
2.1 Block Diagram
This product consists of an HD61202 segment driver, an HD61203 common driver and a bias voltage generator. Figure 2 shows the block diagram. DBo to DB7 qorror rrr rrr r ‘ RST, RAW, D/IE ! ' t ' cs i Var Vou Vor VE 1 Vic H Bias Voltage : ! H Generator ' 1 ' ' 1 1 v. ' Vop 1 a 1 ' Vb ' I Ve ' ' Ve Segment Driver ' H ' Vss 1 ' 1 ' { i H 128 x32 full dot matrix ' H Common Driver Leb H 1 pL NY ' 1 1 1 t ' 1 t 1 be nnn nnn n nn enn nnn nnn ee een ee nen e ween nnn n enn nnn nnd Figure 2 Block Diagram
2.2 Segment Drivers (HD61202)
The segment driver is a 64 drive output CMOS IC. A 64 (SEG1 to SEG64) x 64 (COM1 to COM64) dot display on the segment driver is divided into a 64 (SEG1 to SEG64) x 32 (COM1 to COM 32) dot display and a 64 (SEG1 to SEG64) x 32 (COM33 to COM 64) dot display on the LCD display, located right and left, and is configured in a 128 x 32 dot display. The 8 bits of data transmitted from the MPU is stored in the internal display RAM, and the segment signal is generated for LC drive. One bit of display RAM data corresponds to one dot lighting or non-lighting on the LC panel. -6-
2.2.1 Block Diagram (Segment Driver)
RST Vop Vss Vic CS RW D/i = E_~—- DBg to DB, Segment Driver eo ee ey Interface Control + I Po H r Input and Output Buffer ' ! i} . 8. 8 . ! !
1 Output Input Instruction Register 1
Display ON/OFF Display Start Line X, Y-Address Register Counter Z-Address Display Data RAM Counter | 4096 bit ne Display Data Latch La ee V, M deter ie e rei eie ere iies gi 42 FRM cL ye yt Y2 Yes Vg - ve Figure 3 Segment Driver -7-
AN.NO.G121300NOU0-3DUE
2.2.2 Functions and Operations of Main Blocks
(1) Interface Control Unit The interface control unit consists of the following blocks: © Input and output buffer @ Input and output register @ Instruction register The above blocks are selected according to the following combinations of R/W and D/I signals: Output Register Read Internal Operation (Display Data RAM > Output Register)
1 Input Register Write
Internal Operation (Input Resister —> Display Data RAM) po | 1 | Busy Check and Status Read Lo [0 | instruction OSS @ Input and output buffer The data is transmitted through eight data buses (DBo to DB7). DB7 --+++ MSB (most significant bit) The data can be input and output only when the Chip Select is selected. Therefore, if the Chip Select is not selected, the internal condition remains unchanged and instruction will not be executed, even when changing the signal of the input terminals excluding the RST (reset) terminal. Note that the RST operates regardless of CS. @ Input and output register This product is provided with an input register and an output register so that the product can interface with MPUs having speed differing from the internal operation. © Input register The input register is a register that is used for temporarily storing the data to be written in the display data RAM. The data to be written from the MPU to the input register will be automatically written in the display data RAM through internal operation. When the Chip Select is selected and R/ W = 0, D/1 =0, the data is written in the register, synchronized with the fall of signal E. © Output register The output register is a register that is used for temporarily storing the data to be read from the display data RAM. -8-
AN.NO.G1213UUNUUU-3DUE In order to read the content of the output register, the Chip Select must be selected, D/I must be 1, and R/W must be 1. When executing the “Read” instruction, the contents of the output register stored at that time are output during the time that "E” is 1. When “E” falls, display data of the currently indicated address is written in the output register. After that, the address advances by one. The contents of the output register are rewritten by the Read instruction. The data is retained by the address set or other instructions. Accordingly, when performing the address set, and next executing the Read instruction, the data of the specified address is not output and the data of the address which is specified is output at the second data read time. Therefore, when setting the address, a dummy read is needed once. See Figure 4. D/I RW e_fLIELI LF LS UF UF LiFe Address Output Register [Waddressdata__[ N+ 1 address data Busy Address | 5, DataRead| g, DataRead| , Data Read DBotoDB7 | check | set Chece (dummy) | check |(Naddress | Check (N+ address (Address data) data) Figure 4 Read Timing (2) Busy flag The status when busy flag is “1” means that the module is operating internally. Instructions other than he Status Read are not available at this time. The busy flag is output to DB7 by the Status Read instruction. Ensure that the busy flag is “0” before executing the instruction. a ch FT susy >| 1 3 Fe STouns Fe F¢ is frequency of $1 or 42 (1/2 the source oscillation frequency of HD61203): 215 kHz typ. . Figure 5 Busy Flag (3) Display ON/OFF Flip/Flop The display ON/OFF Flip/Flop is a flip-flop function that determines whether the display data corresponding to the RAM data is output to the segment on the LCD (ON status ) or goes to all nonlit status regardless of the RAM data (OFF status). This is controlled by the display ON/OFF instruction. When the RST signal becomes “0,” the display goes to OFF status. This flip-flop status is output to DBs by the Status Read instruction. Even when performing display ON/OFF, the data inside the RAM is not affected. -9-
ANNU. 12 12UUINUUU-2UUE (4) Display start line register The display start line register is a register which determines the line address (see Figure 6) for which data is displayed on the top line of the left-half LCD screen when displaying the contents of the display data RAM on the LCD screen. It is also used to scroll the display. The 6 bit (0 to 63) display start line information is written in this register by the Display Start Line Set Instruction. The contents of this register are transmitted to address counter Z at “H” level of the FRM signal (common driver output) which indicates the display start on the screen. (5) Z-address counter The Z-address counter generates the address to output the display data synchronized with the common signal. This is a 6-bit counter which counts at the fall of the CL signal (common driver output). The contents of the display start line register are preset to the Z-address counter at "H” level of the FRM signal (common driver output). (6) Display data RAM The display data RAM is a RAM that stores the display dot data. 1 bit of RAM data corresponds to lighting (data = 1) or non-lighting (data = 0) of 1 dot of the display on the LCD screen. Figure 6 shows the relationship between the address and data inside the RAM on the 128 x 32 dot display. In this case, the display start line is 0. -10-
AN.NO.G121SUUNUUU-3DUE Display pattern ( Display start line: 0) Common driver Common driver output X4 to X32 output X33 to Xe cOM1 ceeeeeeee poy bb btn = COM33 com2 woee eee e ee. beqaebeb donb oad LJ COM34 com3 ee eer ae i com4 H mer ! COMS ! ! : come t { 1 cOoM7 H ' cOM8 H i \\ comg 3 ! ! ratte od [Mi Ict---- a ' 1 oo oe eo Ju-b 4-4] - a ' coma0 fF ET aa oe rer coms! Se ae [1 F-comes COM32 poy 1 Lt ttt oe [ 1 COM64 Segment driver = se tput Y; to Y mabe ae output Y4 XY mee 62 ae Data inside 12/3) 4)5 ~ >= DBo ‘ise pop TT fo] weeeee eee [ofo[s} Line oO DB, rr foforols | ____--_..-Jofo[1 -— tine1 X- address OB3 mo foto tots ep fot] X=0 DBa moe bb ott] ~ DBs tre ototot st _____.fofots] DB, jfofofetoto| ~___-.-.--,ofofo] noe potolo) X=1 ! ; ' X=2 ' ' ' \\ Jolt fofo] +0 | folsfololo| . fofofo] Ker ifatififaf foto] ot— tine 62 fofofofojo] ~~ [ofofot—tiness Y-address Yo Y1¥2 Y3 Ya Yor 6z¥63 Figure 6 Relationship Between Display and Data Inside Display RAM (7) X,¥- address counter : X, Y-address counter is a 9-bit counter which gives the address of the internal display data RAM. It is necessary to set the X-address counter of the three upper bits, and the Y-address counter of the six lower bits using differing instructions. -11-
© X-address counter Address counter X is a simple register that is not provided with a count function. The address is set by instruction. @ Y-address counter This counter sets the address by instruction and is automatically advanced by the read/write operation. Counting is performed by looping the values 0 to 63. 2.3. Common driver (HD61203) The common driver is a 64 drive output CMOS IC. Incorporating an oscillation circuit, this driver generates the common signal and timing signals (LC AC drive control, and one-frame timing signal) necessary for the LC display, and controls the display by supplying the timing signals to the segment driver.
2.4 Bias voltage generator
Six levels of standard voltage Va to Vf are applied to the drivers as a bias voltage. This voltage is generated by resistance division of Vopr and driven by a voltage follower through an operational amplifier. Vpp o Oo Va R. c 1 pH © Vb R. c ' PH 0 Ve c R. c : PS o Ve Operational Ry Amplifier c Vic © o VE 1/9 bias: Ro = (9-4) Ri = 5 Ry Figure7 Bias Voltage Generator -12-
- OPERATING INSTRUCTIONS 3.1. Terminal Functions Table 1 Terminal Functions [Sorat [ev [v0 [oem] Funan a Input | Mpu_ | Enable Write (R/W = 0):Latches data of DBg to DB7 at the fall of E. Read (R/W = 1):Outputs data to DBp to DB7 while "E” keeps a high level.
1 Input MPU ReadMrite selection
R/W = 1: When E = 1 and CS = 0, the data is output to DBp to DB7 and read is available by MPU. RW =0: When CS = 0, DBo to DB7 are ready for receiving the input. Dil 1 Input MPU Data/Instruction selection D/l = 1: Indicates that the data in DBo to DB7 is the display data. D/l =0: Indicates that the data in DBo to DB7 is the instruction code. Chip select input. Data input and output is possible under cs Input the following status: P p p [seus [0 RST Input mpu___| Reset signal Setting the RST signal to a low level allows for initial setup. (1) ON/OFF register: 0 setup (display OFF) (2) Display start line register: 0 line setup (display starts from O line) The setup status is retained until the status is changed by an instruction after reset is released. a 1 FGND terminal is connected to the metallic frame of the module. Use this terminal when grounding the frame. -13-
AN.NO.G1213UUNUUU-SDUE 3.2. Timing Characteristics [em Ssmbot [win [Tym [Max [unit | wot ] Jeqeerme | tere | t000 | || ns | 2 | [epusewarnon | Pen | 450 | - | =| ns | 1.2 | [epucewamnear | Per | 450 | - | ns | 1.2 | [evserime tte TT ass |e [efairme tte Ts | ns | 2 [accremseroprime | tas | tao | [ns | [adéresthowstime | tw [to | || ns | 2 [oatasewptime | tow | 200 | - || ns | t| [osadeiaytme | toon | = | - | 320] ns | 23 | Datahoistimedurngwete | tow | 10 | - |] ns [1 Note 1: | When the MPU writes: Note 2: | When the MPU reads: teve teve 2.0VA| tas 2.0V iw | R/W fas, | mN ‘ Td =O ~ rel ‘al D/l 0.8y Dil 0.8y, mel on > | DBp to DB7 i ee: DBp to DBF rr a Note 3: Load circuits (DB to DB7) by =f R, = 2.4k0 Test point R= 11k0 - Cc R B C = 130 pF (including jig capacity) aa Da Diodes D1 to D4 are 152074 ®. -14-
3.3. Reset Function Setting the RST terminal to a low level when the power is on allows for initial setup. © Display OFF @ Display start line register: Set address 0. While the RST remains at a low level, instructions other than the status read cannot be accepted. Execute other instructions after confirming that DB,=0 (reset release) and DB7=0 (ready) , using the status read instruction. The power conditions for power-on initial setup are as follows:. [retin [te | | - | - | =| [wseime [ef = | - | [= | 4.5V. Vpp tasty) tr 0.7Vpp RST "ke If the RESET is executed during operation, retention of the contents of all registers (excluding an ON/OFF register) and the RAM is not guaranteed. Always set them again. -15-
ANN.ING.U 1é 1SUUINUUU-S UE
3.4 Instructions
3.4.1 General
Instructions are listed on Table 2. Instructions other than the Status Read instruction will not be executed if they are sent while another instruction is already being executed. The busy flag is “1” when executing the instruction. Check whether or not the flag is “1” before transmitting the instructions from the MPU. Table 2 List of Instructions Instruction Function | [ew [0/1 [be [85 | bas | ba, | pa, | ba, | oa, | ba, | Turns ON/OFF total display. Data and Display 1 internal status in the display RAM remain unchanged. ON/OFF 1:ON 0: OFF _ . Determines the RAM line to be displayed on Display Display start lines the top line (COM!) on the left-half display start line (0to 63) (EG1 to SEG64) X-address X-address(page) | Sets the X-address of the RAM (page) in (page) set (0to7) the X-address (page) register. Y-address Y-address set adress of the RAM in the Y-address set (0 to 63) . R Reads the status. 8 : : on | & RESET 1: Reset 0: Normal Status read ’ ats ON/OFF 1: Display OFF 0: Display ON Y OFF) E BUSY 1: during internal operation T 0: READY status Writes data DBo (LSB) to | Accesses the isp DB, (MSB)onthedata | RAM inwhich Display Write Data bus into the display address has been data write RAM. specified beforehand. After that the Y- Reads data DBy (LSB) to | address . DB; (MSB) from the advances by one. 7 | Display Read Data display RAM into the data read data bus. Note: The BUSY time varies depending upon the frequency F¢ (:215 kHz (typ.)) of ¢1,¢2(1/F¢ = Teusy = 3/F¢).
3.4.2 Detailed explanation
(1) Display ON/OFF cole [ofToftofofs]i{i[ififo| Turns the display ON when D = 1, and OFF when D=0. When the display is turned OFF by D=0, the original display appears if D is set to 1 because the display data is retained in the display data RAM. -16-
AN.INU.S 14 IoUUTNUU-2 UE (2) Display start line code LoToTi Ti faqaltaqafala] ~— Upper bits Lower bits > Sets the display data RAM line address expressed with binary AAAAAA in the display start line register. When displaying the content of the display data RAM, the display data on the line addresses which are set in the register is displayed on the top line on the left-half LCD screen. For address configuration inside the display data, refer to Figure 6. Figure 8 shows display examples of start lines 0 to 3. com1 oe mo" coms3 com2 i i com3 H to. coma i i: coms ¢ ie come - 7S ! : ! i : i j coM61 Display start line =0 com1 — “TTT TE coms com2 H ioe com3 ! i - coma H ioe coms i ie come - - | : : ' H coMme61 come—T MT... a comes Display start line = 1 com ~~ oe MMe com2 H ie com3 i to. coma i i - OMS ! i. comé - 1 1 - it j cOM61 Display start line =2 -17-
com — POTTY CTF comsa com2 i io com3 i Po. coma H i. coms i too. come : - i j come61 coma TTT) a comes Display start line =3 Figure8 Relationship Between Display Start Lines and Displays (3) X-address (page) set code Loto]: [ofifitifajafal ~~ Upper bits Lower bits > The display data RAM “X” address (page) which is expressed with binary AAA is set in the X-address register. Following write/read operations from the MPU are performed on the specified X-address (page) until the next X-address (page) set is performed. The configuration of display data RAM and X-address is shown in Figure 9. (4) Y-address set cole [oTofof:[alalafalfalfal] ~< upper bits Lower bits > The display data RAM Y- address which is expressed with binary AAAAAA is set in the Y-address counter. After that the Y-address counter advances by one each time write/read is performed from the MPU. The configuration of the display data RAM and Y-address is shown in Figure 9. DBy to Page O X=0 DB, DBy to Page 1 X=1 bB, DBy to Page 6 X=6 DB, DB, to Page7 X=7 DB, Figure9 Display Data RAM Address Configuration -18-
(5) Status read code L1 [0 Ju] 0 [oworfusr] o [oo | 0 | BUSY: When BUSY = 1, it means that the the module is operating internally and the next instruction is not accepted until BUSY = 0. After confirming that BUSY = 0, it is necessary to perform the next write. ON/OFF: Indicates that the display is OFF when ON/OFF = 1. Indicates that the display is ON when ON/OFF = 0. RESET: Indicates that initial setup is performed by the RST signal. Indicates that the initialization is being performed when RESET = 1 and instructions other than the Status Read instruction are not accepted. When RESET = 0, initialization is completed and operation status is normal. (6) Display data write code [o[s[o]o[o[o[o]o{o]o] ~<—Upper bits Lower bits >> Writes 8-bit binary data DDDDDDDD in the display data RAM. After the write is completed, the Y- address is automatically advanced by one (7) Display data read code [1 [i To]o[Tofotofofo]{o] ~<— upper bits Lower bits > Read 8-bit binary data DDDDDDDD from the display data RAM. After read is performed, the Y- address is automatically advanced by one. A dummy read is necessary once, immediately after the address set is completed. For details, refer to segment driver output register section. -19-
3.5 Contrast Adjustment and Power Supply Example
The LC panel viewing angle and display screen contrast are greatly affected by the ambient temperature. The recommended LC drive voltage (Vopr) at each temperature is given below. Vopr is a value at which the best display is visually obtained. This value does not always correspond to the value at which the best contrast (Cmax.) is obtained. A contrast adjustment circuit example is shown below: Vi Rg=1.2kQ Vss . Ry (variable resistor) c2. LN | =10k0 12V | > Vic C1, C2= 10 pF Figure 10 Contrast Adjustment
3.6 MPU Connection Diagram
D0 to D7 ——~ Dote D7 ADtOA7 ~ DBp to DBy A0to A15 av Recall pond CE BO ri E [4 ge ee — Als B2 Dil i ee | i) a » “ a |_. — — 1 i eG Ll. ¢ é BS cs2 : Vop Vss Vic Figure 11 Example of Connection to Z80A -20-
- PRECAUTIONS Safety + Ifthe LCD panel is damaged, be careful not to get the liquid crystal in your mouth. If the liquid crystal touches your skin or clothes, promptly wash it off using soap and plenty of water. Handling + Avoid static electricity, as it will damage the CMOS LSI. + The LCD panel is made of plate glass. Do not hit or crush it. + Do not remove the panel or frame from the module. + The polarizer of the display is very fragile. Handle it very carefully. Mounting and desian + Mount the module by using the specified mounting parts and holes. + To protect the module against external pressure, place a transparent plate (e.g., acrylic or glass) on the module, leaving a small gap between the display surface and transparent plate. trExample Small gap Exterior face Transparent plate 4 Pp ee a 7. I A i A eS | Ol Le DR _scew + Design the system so that no input signal is given unless the power-supply voltage is applied. + Keep the module dry. Avoid condensation to prevent the transparent electrodes from being damaged. Storage + Store the module ina dark place, where the temperature is 25°C + 10°C and the relative humidity below 65%. + Do not store the module near organic solvents or corrosive gases. + Keep the module (including accessories) safe from vibration, shock and external pressure. Cleaning + Do not wipe the polarizer with a dry cloth, as it may scratch the surface. + Wipe the module gently with a soft cloth soaked with a petroleum benzine. + Donotuse ketonic (ketone) solvents (ketone and acetone) or aromatic solvents (toluene and xylene), as they may damage the polarizer. -21-
-A- Active display area 1... eee ee cee eet eee cence 2 -B- -c- -D- -E- -F- -I-
-L- -O- -P- -R- Reset... ee eee eee eee ee cece eect eeeeeeeeeees 5,8, 13,15 -S- Statusread 00... cece e cece e eee eee ees 8,9, 15, 16, 19 Storage 2... cece eee ee eee eee ete renee 24 -T- -V- -W- -X- X-address counter 2.2... eee cee cette cece eect eee eeee 12 "X, Y-address counter ee -Y- -Z-
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