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Rev. 1.2 4/16 Copyright © 2016 by Silicon Laboratories Si3402BISO-EVB Si3402BISO-EVB ISOLATED E VALUATION B OARD FOR THE Si3402B 1. Description The Si3402B isolated evaluation board (Si3402BISO-EVB Rev 2) is a reference design for power supplies in Power over Ethernet (PoE) Powered Device (PD) applicatio ns. The Si3402B is described more completely in the data sheet and application notes. This document desc ribes only the Si3402BISO-EVB evaluation board. An evaluation board demonstrating the non-isolated application is described in the Si3402B-EVB User’s Guide. 2. Planning for Successful Designs Silicon Labs strongly recommends the use of the schematic and la yout databases provid ed with the evaluation boards as the starting point for your design. Use of external components other than those described and recommended in this document is generally discouraged. Refer to Table 2 on page 9 for more information on critical component specifications. Ca reful attention to the recommended layout guidelines is required to enable robust designs and full specification compliance. To hel p ensure design success, please submit your schematic and layout databases to www.silabs.com/support for review and feedback. 3. Si3402B Board Interface Ethernet data and power are applied to the board thro ugh the RJ-45 connector (J1). The board itself has no Ethernet data transmission functionality, but, as a convenience, the Ethernet transformer secondary is brought out to the test points. Power may be applied in the following ways:  Connecting a dc source to Pins 1, 2 and 3, 6 of the Ethernet cable (either polarity).  Connecting a dc source to Pins 4, 5 and 7, 8 of the Ethernet cable (either polarity).  Using an IEEE 802.3-2015-compliant, PoE-capable PSE, such as Trendnet TPE-1020WS. The Si3402BISO-EVB board schematics and layout are shown in Figures 1 through 6. The dc output is at connectors J11(+) and J12(–). Boards are generally shipped configured to produce +5 V output voltage but can be configured for +3.3 V or other output voltages as shown in Table 2 on page 9. The preconfigured Class 3 signature also can be modified according to Table 3 on page 10. The D8–D15 Schottky-type diode bridge bypass is recommended only for higher power levels (Class 3 operation). For lower power levels, such as Class 1 and Class 2, the diodes can be removed. When the Si3402B is used in external diode bridge configuration, it requires at least one pair of the CTx and SPx pins to be connected to the PoE voltage input terminals (to the input of the external bridge). The feedback loop compensation has been optimized for 3.3, 5, 9, and 12 V output as well as with standard and low ESR capacitors in the output filter section (Table 2 on page 9). The use of low ESR capacitors is recommended for lower output ripple, improved load transient response and low temperature (below 0 °C) operation.

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Vneg is a thermal plane as well as ESD and EMI. on backside 1 to 1.2mm pitch 0.3 to 0.33mm diameter. Capacitors C10-C17 are for ESD immunity.. Place optional bypass diodes for high power applications (>7W) in parallel. Vpos is an EMI and ESD plane. Use top layer. SP1/SP2 should be connected. Figure 1. Si3402B Schematic—5 V, Class 3 PD

Figure 2. Si3402B Layout (Top Layer)

Figure 3. Primary Side (Layer 2)

Figure 4. Internal 1 (Layer 3)

Figure 5. Internal 2 (Layer 4)

Figure 6. Secondary Side (Bottom Layer)

the Si3402B PoE PD Controller in Isolated and Non-Isolated Designs” for more information. Table 1. Si3402BISO-EVB Bill of Materials

100 V ±10% X7R C0603 C0603X7R101-102K Venkel

1 DFLT30A-7 D2 4.65 A 30 V Zener POWERDI-123 DFLT30A-7 Diodes Inc. 1 PDS1040 D3 10 A 40 V Schottky POWERDI-5 PDS1040-13 Diodes Inc.

8 SS2150 D8, D9, D10, D11,

2 A 150 V Single DO-214AC SS2150-LTP MCC

1 RJ-45 J1 Receptacle RJ45-SI-52004 SI-52003-F Bel

2 BND_POST J11, J12 15 A Banana Banana-Jack 101 ABBATRON

1 FA2924 T1 XFMR-FA2924 FA2924-AL Coilcraft

1 TLV431 U3 Shunt TLV431-DBZ TLV431BCDBZR TI

7 Black TP1, TP2, TP3, TP4,

Table 2. Component Selection for other Output Voltages and Filter Types

3.3 V Output Transformer*

10 W, 470 pF

5.0 V Output

9.0 V Output Transformer*

12.0 V Output Transformer* EP10

*Note: Coilcraft part number. EP13 core is recommended for >10 W output power.

Table 3. Component Selection for Different Classification Levels

Rev. 1.2 11 APPENDIX —Si3402BISO D ESIGN AND L AYOUT CHECKLIST Introduction Although all four EVB designs are preconfigured as Class 3 PDs with 5 V outputs, the schematics and layouts can easily be adapted to meet a wide variety of common output voltages and power levels. The complete EVB design databases for the standard 5 V/Class 3 configuration are included in the EVB kit and can also be requested through S ilicon Labs customer support at www.silabs.com/PoE under the “Documentation” link. Silicon Labs strongly recommends using these EVB sche matics and layout files as a starting point to ensure robust performance and to help avoid common mistakes in the schematic capture and PCB layout processes. Following are recommended design checklists that can assist in trouble-free development of robust PD designs: Refer also to the Si3402B data sheet and AN956 when using the checklists below. 1. Design Planning Checklist: a. Silicon Labs strongly recommends using the EVB schematics and layout files as a starting point as you begin integrating the Si3402B into your system design process. b. Determine your load’s power requirements (i.e., V OUT and IOUT consumed by the PD, including the typical expected transient surge conditions). In general, to achieve the highest overall efficiency performance of the Si3402, choose the highest voltage used in your PD and then post regulate to the lower supply rails, if necessary. c. If your PD design consumes >7 W, make sure you bypass the Si3402’s on-chip diode bridges with external Schottky diode bridges or discrete Schottky diodes. Bypassing the Si3402’s on-chip diode bridges with external bridges or discrete diodes is required to help spread the heat generated in designs dissipating >7W . d. Based on your required PD power level, select the app ropriate class resistor value by referring to Table 3 of AN956. This sets the Rclass resistor (R3 in Figure 1 on page 2). e. The feedback loop stability has b een checked over the entire load range for the specific component choices in Table 1. Low ESR filter capacitors will give better load transient response and lower output ripple so they are generally preferred. For the standard ESR capacitor, the ESR increase at very low temperatures may cause a loop stability issue. A typical evaluation board has been shown to exhibit instability under very heavy loads at –20 °C. Due to self-heating, this condition is not a great concern. However, using a low ESR filter capacitor solves this problem (but requires some recompensation of the feedback loop). Silicon Laboratories recommends against component substitution in the filtering and feedback path as this may result in unstable operation. Also, use care in situations that have additional capacitive loading as this will also affect loop stability. 2. General Design Checklist Items: a. ESD caps (C10–C17 in Figure 1) are strongly recommended for designs where system-level ESD (IEC6100-4-2) must provide >15 kV tolerance. b. If your design uses an AUX su pply, make sure to include a 3  surge limiting resistor in series with the AUX supply for hot insertion. Refer to AN956 when AUX supply is 48 V. c. Silicon Labs strongly recommen ds the inclusion of a minimum load (250 mW) to avoid switcher pulsing when no load is present, and to avoid false disconnection when less than 10 mA is drawn from the PSE. If your load is not at least 250 mW, add a resistor load to dissipate at least 250 mW. d. If using PLOSS function, make sure it’s properly te rminated for connection in your PD subsystem. If PLOSS is not needed, leave this pin floating.

12 Rev. 1.2 3. Layout Guidelines: a. Make sure the VNEG pin of the Si3402B is c onnected to the backside of the QFN package with an adequate thermal plane, as noted in the data sheet and AN956. b. Keep the trace length from connecting to SWO an d retuning to Vss1 and Vss2 as short as possible. Make all of the power (high current) traces as short, direct, and thick as possible. It is a good practice on a standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere. c. Usually one standard via handle s 200 mA of current. If the trace will need to conduct a significant amount of current from one plane to the other use multiple vias. d. Keep the circular area of the loop from the Swit cher FET output to the inductor or transformer and returning from the input filter capacitors (C1–C4) to Vss2 as small a diameter as possible. Also, minimize the circular area of the loop from the output of the inductor or transformer to the Schottky diode and returning through the fist stage output filter capacitor back to the inductor or transformer as small as possible. If possible, keep the direction of current flow in these two loops the same. e. Connect the sense points to the output terminals dire ctly to avoid load regulation issues related to IR drops in the PCB traces. The sense points are the output side of R5 and Pin 3 of TLV431. f. Keep the feedback and loop st ability components as far from the transformer/inductor and noisy power traces as possible. g. If the outputs have a ground plane or positive out put plane, do not connect the high current carrying components and the filter capacitors through the plane. Connect them together and then connect to the plane at a single point. h. As a convenience in layout, please note that the IC is symmetrical with respect to CT1, CT2, SP1 and SP2. These leads can be interchanged. At least one pair of CT1/CT2 or SP1/SP2 should be connected. To help ensure first pass success, please su bmit your schematics and layout files to www.silabs.com/support for review. Other technical questions may be submitted as well.

Rev. 1.2 13 DOCUMENT CHANGE LIST Revision 1.1 to Revision 1.2  Initial release of Si3402BISO-EVB User’s Guide, modified from Si3402-ISO-EVB User’s Guide Revision 1.1.

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