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ESP32-C3-DEVKITC-02

ESPRESSIF SYSTEMS (SHAN...

UltraLowPower SoC with RISCV SingleCore CPU Version 1.1

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Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 44

Technical content

Datasheet sections

1 ESP32C3 Series Comparison
1.1 ESP32-C3 Series Nomenclature
1.2 Comparison
2 Pin Definition
2.1 Pin Layout
2.2 Pin Description
2.3 Power Scheme
2.4 Strapping Pins
3 Functional Description
3.1 CPU and Memory
3.1.1 CPU
3.1.2 Internal Memory
3.1.3 External Flash
3.1.4 Address Mapping Structure
3.1.5 Cache
3.2 System Clocks
3.2.1 CPU Clock
3.2.2 RTC Clock
3.3 Analog Peripherals
3.3.1 Analog-to-Digital Converter (ADC)
3.3.2 Temperature Sensor
3.4 Digital Peripherals
3.4.1 General Purpose Input / Output Interface (GPIO)
3.4.2 Serial Peripheral Interface (SPI)
3.4.3 Universal Asynchronous Receiver Transmitter (UART)
3.4.4 I2C Interface
3.4.5 I2S Interface
3.4.6 Remote Control Peripheral
3.4.7 LED PWM Controller
3.4.8 General DMA Controller
3.4.9 USB Serial/JTAG Controller
3.5 Radio and Wi-Fi
3.5.3 Clock Generator

Datasheet sections

3.5.4 Wi-Fi Radio and Baseband
3.5.5 Wi-Fi MAC
3.5.6 Networking Features
3.6 Bluetooth LE
3.6.1 Bluetooth LE Radio and PHY
3.6.2 Bluetooth LE Link Layer Controller
3.7 Low Power Management
3.8 Timers
3.8.1 General Purpose Timers
3.8.2 System Timer
3.8.3 Watchdog Timers
3.9 Cryptographic Hardware Accelerators
3.10 Physical Security Features
3.11 Peripheral Pin Configurations
4 Electrical Characteristics
4.1 Absolute Maximum Ratings
4.2 Recommended Operating Conditions
4.3 VDD_SPI Output Characteristics
4.5 ADC Characteristics
4.6 Current Consumption
4.7 Reliability
4.8 Wi-Fi Radio
4.8.1 Wi-Fi RF Transmitter (TX) Specifications
4.8.2 Wi-Fi RF Receiver (RX) Specifications
4.9 Bluetooth LE Radio
4.9.1 Bluetooth LE RF Transmitter (TX) Specifications
4.9.2 Bluetooth LE RF Receiver (RX) Specifications
5 Package Information
6 Related Documentation and Resources

ESP32C3 Series Datasheet UltraLowPower SoC with RISCV SingleCore CPU Supporting IEEE 802.11b/g/n (2.4 GHz WiFi) and Bluetooth® 5 (LE) Including: ESP32-C3 ESP32-C3FN4 ESP32-C3FH4 Version 1.1 Espressif Systems Copyright © 2021 www.espressif.com

ESP32-C3 series of SoCs is an ultra-low-power and highly-integrated MCU-based solution that supports 2.4 GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). The block diagram of ESP32-C3 is shown below. Core System Wireless MAC and Baseband Wi-Fi MAC Wi-Fi Baseband Bluetooth LE Link Controller Bluetooth LE Baseband 2.4 GHz Balun + Switch2.4 GHz Receiver

2.4 GHz

Espressif’s ESP32-C3 Wi-Fi + Bluetooth® Low Energy SoC ROM SRAM RSA RNG Digital Signature SHA AES HMAC Secure Boot USB Serial/ JTAG GPIO UART TWAI® General-purpose Timers I2S I2C Pulse Counter LED PWM Camera Interface SPI0/1 RMT SPI2 DIG ADC Controller System Timers RTC GPIO Temperature Sensor RTC Memory RTC Watchdog Timer PMU RTC Modules having power in speciﬁc power modes: Active Active and Modem-sleep All modes Active, Modem-sleep, and Light-sleep; optional in Light-sleep⚙ GDMA LCD Interface Watchdog Timers Figure 1: Block Diagram of ESP32C3 Solution Highlights

A complete WiFi subsystem that complies with IEEE 802.11b/g/n protocol and supports Station mode, SoftAP mode, SoftAP + Station mode, and promiscuous mode
A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth mesh
32bit RISCV singlecore processor with a four-stage pipeline that operates at up to 160 MHz
Stateoftheart power and RF performance
Storage capacities ensured by 400 KB of SRAM (16 KB for cache) and 384 KB of ROM on the chip, and SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to external flash
Reliable security features ensured by – Cryptographic hardware accelerators that support AES-128/256, Hash, RSA, HMAC, digital signature and secure boot – Random number generator – Permission control on accessing internal Espressif Systems 2 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

memory, external memory, and peripherals – External memory encryption and decryption

Rich set of peripheral interfaces and GPIOs, ideal for various scenarios and complex

applications

Features

WiFi

IEEE 802.11 b/g/n-compliant
Supports 20 MHz, 40 MHz bandwidth in 2.4 GHz band
1T1R mode with data rate up to 150 Mbps
Wi-Fi Multimedia (WMM)
TX/RX A-MPDU, TX/RX A-MSDU
Immediate Block ACK
Fragmentation and defragmentation
Transmit opportunity (TXOP)
Automatic Beacon monitoring (hardware TSF)
4 × virtual Wi-Fi interfaces
Simultaneous support for Infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode Note that when ESP32-C3 scans in Station mode, the SoftAP channel will change along with the Station channel
Antenna diversity
802.11mc FTM
Supports external power amplifier Bluetooth
Bluetooth LE: Bluetooth 5, Bluetooth mesh
High power mode (18 dBm)
Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps
Advertising extensions
Multiple advertisement sets
Channel selection algorithm #2
Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna CPU and Memory
32-bit RISC-V single-core processor, up to 160 MHz
CoreMark® score: – 1 core at 160 MHz: 407.22 CoreMark; 2.55 CoreMark/MHz
384 KB ROM
400 KB SRAM (16 KB for cache)
8 KB SRAM in RTC
Embedded flash (see details in Chapter1 ESP32-C3 Series Comparison)
SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to multiple external flash
Access to flash accelerated by cache
Supports flash in-Circuit Programming (ICP) Advanced Peripheral Interfaces
22 × programmable GPIOs
Digital interfaces: – 3 × SPI – 2 × UART – 1 × I2C – 1 × I2S – Remote control peripheral, with 2 transmit channels and 2 receive channels – LED PWM controller, with up to 6 channels – Full-speed USB Serial/JTAG controller – General DMA controller (GDMA), with 3 transmit channels and 3 receive channels – 1 × TWAI® controller compatible with ISO 11898-1 (CAN Specification 2.0)
Analog interfaces: Espressif Systems 3 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

– 2 × 12-bit SAR ADCs, up to 6 channels – 1 × temperature sensor

Timers: – 2 × 54-bit general-purpose timers – 3 × watchdog timers – 1 × 52-bit system timer Low Power Management
Power Management Unit with four power modes Security
Secure boot
Flash encryption
4096-bit OTP, up to 1792 bits for use
Cryptographic hardware acceleration: – AES-128/256 (FIPS PUB 197)
Permission Control
SHA Accelerator (FIPS PUB 180-4)
RSA Accelerator
Random Number Generator (RNG)
HMAC
Digital signature Applications (A Nonexhaustive List) With ultra-low power consumption, ESP32-C3 is an ideal choice for IoT devices in the following areas:
Smart Home – Light control – Smart button – Smart plug – Indoor positioning
Industrial Automation – Industrial robot – Mesh network – Human machine interface (HMI) – Industrial field bus
Health Care – Health monitor – Baby monitor
Consumer Electronics – Smart watch and bracelet – Over-the-top (OTT) devices – Wi-Fi and Bluetooth speaker – Logger toys and proximity sensing toys
Smart Agriculture – Smart greenhouse – Smart irrigation – Agriculture robot
Retail and Catering – POS machines – Service robot
Audio Device – Internet music players – Live streaming devices – Internet radio players
Generic Low-power IoT Sensor Hubs
Generic Low-power IoT Data Loggers Espressif Systems 4 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

1 ESP32-C3 Series Comparison 9

2 Pin Description 10

3 Description of ESP32-C3 Power-up and Reset Timing Parameters 13

4 Strapping Pins 14

5 Parameter Descriptions of Setup and Hold Times for the Strapping Pins 15

6 IO MUX Pin Functions 19

7 Power-Up Glitches on Pins 20

8 Mapping of SPI Signals and Chip Pads 21

9 Connection Between ESP32-C3 and External Flash 21

10 Peripheral Pin Configurations 27

12 Recommended Operating Conditions 30

13 VDD_SPI Output Characteristics 30

14 DC Characteristics (3.3 V, 25 °C) 31

15 ADC Characteristics 31

16 Current Consumption Depending on RF Modes 32

17 Current Consumption Depending on Work Modes 32

18 Reliability Qualifications 32

19 Wi-Fi Frequency 33

20 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 33

21 TX EVM Test 34

22 RX Sensitivity 34

23 Maximum RX Level 35

24 RX Adjacent Channel Rejection 35

25 Bluetooth LE Frequency 35

26 Transmitter Characteristics - Bluetooth LE 1 Mbps 36

27 Transmitter Characteristics - Bluetooth LE 2 Mbps 36

28 Transmitter Characteristics - Bluetooth LE 125 Kbps 36

29 Transmitter Characteristics - Bluetooth LE 500 Kbps 37

30 Receiver Characteristics - Bluetooth LE 1 Mbps 37

31 Receiver Characteristics - Bluetooth LE 2 Mbps 38

32 Receiver Characteristics - Bluetooth LE 125 Kbps 38

33 Receiver Characteristics - Bluetooth LE 500 Kbps 39

Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

1 Block Diagram of ESP32-C3 2

2 ESP32-C3 Series Nomenclature 9

3 ESP32-C3 Pin Layout (Top View) 10

4 ESP32-C3 Power Scheme 12

5 ESP32-C3 Power-up and Reset Timing 13

6 Setup and Hold Times for the Strapping Pins 14

7 Address Mapping Structure 17

8 QFN32 (5×5 mm) Package 40

Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

1 ESP32-C3 Series Comparison

ESP32C3 Series Comparison

1.1 ESP32C3 Series Nomenclature

F x Chip series Embedded ﬂash Flash temperature H: High temperature N: Normal temperature Flash VL]H Figure 2: ESP32C3 Series Nomenclature

1.2 Comparison

T able 1: ESP32C3 Series Comparison Ordering Code Embedded Flash Ambient T emperature (°C) Package (mm) ESP32-C3 — –40 ∼ 105 QFN32 (5*5) ESP32-C3FN4 4 MB –40 ∼ 85 QFN32 (5*5) ESP32-C3FH4 4 MB –40 ∼ 105 QFN32 (5*5) Espressif Systems 9 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

2 Pin Definition

Pin Definition

2.1 Pin Layout

VDD3P3_RTC MTDI MTMS GPIO3 CHIP_EN GPIO2 XTAL_32K_N XTAL_32K_P VDD3P3 VDD3P3 LNA_IN VDDA VDDA XTAL_P XTAL_N U0TXD U0RXD GPIO19 GPIO18 SPID SPICLK SPICS0 SPIWP SPIHD VDD_SPI VDD3P3_CPU ESP32-C3

33 GND

Figure 3: ESP32C3 Pin Layout (T op View)

2.2 Pin Description

T able 2: Pin Description Name No. T ype Power Domain Function LNA_IN 1 I/O — RF input and output VDD3P3 2 PA — Analog power supply VDD3P3 3 PA — Analog power supply XTAL_32K_P 4 I/O/T VDD3P3_RTC GPIO0, ADC1_CH0, XTAL_32K_P XTAL_32K_N 5 I/O/T VDD3P3_RTC GPIO1, ADC1_CH1, XTAL_32K_N GPIO2 6 I/O/T VDD3P3_RTC GPIO2, ADC1_CH2, FSPIQ Espressif Systems 10 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

Name No. T ype Power Domain Function CHIP_EN 7 I VDD3P3_RTC High: on, enables the chip. Low: off, the chip powers off. Note: Do not leave the CHIP_EN pin floating. GPIO3 8 I/O/T VDD3P3_RTC GPIO3, ADC1_CH3 MTMS 9 I/O/T VDD3P3_RTC GPIO4, ADC1_CH4, FSPIHD, MTMS MTDI 10 I/O/T VDD3P3_RTC GPIO5, ADC2_CH0, FSPIWP, MTDI VDD3P3_RTC 11 PD — Input power supply for RTC MTCK 12 I/O/T VDD3P3_CPU GPIO6, FSPICLK, MTCK MTDO 13 I/O/T VDD3P3_CPU GPIO7, FSPID, MTDO GPIO8 14 I/O/T VDD3P3_CPU GPIO8 GPIO9 15 I/O/T VDD3P3_CPU GPIO9 GPIO10 16 I/O/T VDD3P3_CPU GPIO10, FSPICS0 VDD3P3_CPU 17 PD — Input power supply for CPU IO VDD_SPI 18 I/O/T/PD VDD3P3_CPU GPIO11, output power supply for flash SPIHD 19 I/O/T VDD3P3_CPU GPIO12, SPIHD SPIWP 20 I/O/T VDD3P3_CPU GPIO13, SPIWP SPICS0 21 I/O/T VDD3P3_CPU GPIO14, SPICS0 SPICLK 22 I/O/T VDD3P3_CPU GPIO15, SPICLK SPID 23 I/O/T VDD3P3_CPU GPIO16, SPID SPIQ 24 I/O/T VDD3P3_CPU GPIO17, SPIQ GPIO18 25 I/O/T VDD3P3_CPU GPIO18, USB_D GPIO19 26 I/O/T VDD3P3_CPU GPIO19, USB_D+ U0RXD 27 I/O/T VDD3P3_CPU GPIO20, U0RXD U0TXD 28 I/O/T VDD3P3_CPU GPIO21, U0TXD XTAL_N 29 — — External crystal output XTAL_P 30 — — External crystal input VDDA 31 PA — Analog power supply VDDA 32 PA — Analog power supply GND 33 G — Ground 1 PA: analog power supply; PD: power supply for RTC IO; I: input; O: output; T: high impedance. 2 Pin functions in bold font are the default pin functions in SPI boot mode.

3 Ports of embedded flash correspond to pins of ESP32-C3FN4 and ESP32-C3FH4 as follows:

CS# = SPICS0
IO0/DI = SPID
IO1/DO = SPIQ
CLK = SPICLK
IO2/WP# = SPIWP
IO3/HOLD# = SPIHD These pins are not recommended for other uses. 4 For the data port connection between ESP32-C3 and external flash please refer to Section3.4.2 Serial Peripheral Interface (SPI). 5 The pin function in this table refers only to some fixed settings and do not cover all cases for signals that can be input and output through the GPIO matrix. For more information on the GPIO matrix, please refer to Chapter IO MUX and GPIO Matrix (GPIO, IO_MUX) inESP32-C3 Technical Reference Manual. Espressif Systems 11 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

2.3 Power Scheme

ESP32-C3 has four input power pins:

VDDA1
VDDA2
VDD3P3_RTC
VDD3P3_CPU And one input/output power pin:
VDD_SPI VDDA1 and VDDA2 are the input power supply for the analog domain. When working as an output power supply, VDD_SPI can be powered by VDD3P3_CPU via RSPI (nominal 3.3 V). VDD_SPI can be powered off via software to minimize the current leakage of flash in Deep-sleep mode. RTC IO is powered from VDD3P3_RTC. The RTC domain is powered from Low Power Voltage Regulator, which is powered from VDD3P3_RTC. The Digital System domain is powered from Digital System Voltage Regulator, which is powered from VDD3P3_CPU and VDD3P3_RTC at the same time. Digital IO is powered from VDD3P3_CPU. The power scheme diagram is shown in Figure4. Figure 4: ESP32C3 Power Scheme Notes on CHIP_EN: Figure5 shows the power-up and reset timing of ESP32-C3. Details about the parameters are listed in Table Espressif Systems 12 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

VDDA, VDD3P3, VDD3P3_RTC, VDD3P3_CPU CHIP_EN t0 t1 VIL_nRST 2.8 V Figure 5: ESP32C3 Powerup and Reset Timing T able 3: Description of ESP32C3 Powerup and Reset Timing Parameters Min Parameter Description (µs) Time between bringing up the VDDA, VDD3P3, VDD3P3_RTC, and VDD3P3_CPU rails, and activating CHIP_EN 50 Duration of CHIP_EN signal level < VIL_nRST (refer to its value in Table14) to reset the chip 50

2.4 Strapping Pins

ESP32-C3 has three strapping pins:

GPIO2
GPIO8
GPIO9 Software can read the values of GPIO2, GPIO8 and GPIO9 from GPIO_STRAPPING field in GPIO_STRAP_REG register. For register description, please refer to Section GPIO Matrix Register Summary in ESP32-C3 Technical Reference Manual. During the chip’s system reset, the latches of the strapping pins sample the voltage level as strapping bits of ”0” or ”1”, and hold these bits until the chip is powered down or shut down. Types of system reset include:
power-on reset
RTC watchdog reset
brownout reset
analog super watchdog reset
crystal clock glitch detection reset By default, GPIO9 is connected to the internal weak pull-up resistor. If GPIO9 is not connected or connected to an external high-impedance circuit, the latched bit value will be ”1” Espressif Systems 13 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

To change the strapping bit values, you can apply the external pull-down/pull-up resistances, or use the host MCU’s GPIOs to control the voltage level of these pins when powering on ESP32-C3. After reset, the strapping pins work as normal-function pins. Table4 lists detailed booting configurations of the strapping pins. T able 4: Strapping Pins Booting Mode 1 Pin Default SPI Boot Download Boot GPIO2 N/A 1 1 GPIO8 N/A Don’t care 1 GPIO9 Internal weak pull-up 1 0 Enabling/Disabling ROM Messages Print During Booting Pin Default Functionality GPIO8 N/A When the value of eFuse field EFUSE_UART_PRINT_CONTROL is 0 (default), print is enabled and not controlled by GPIO8. 1, if GPIO8 is 0, print is enabled; if GPIO8 is 1, it is disabled. 2, if GPIO8 is 0, print is disabled; if GPIO8 is 1, it is enabled. 3, print is disabled and not controlled by GPIO8.

1 The strapping combination of GPIO8 = 0 and GPIO9 = 0 is invalid and will trigger unexpected be-

havior. Figure6 shows the setup and hold times for the strapping pins before and after the CHIP_EN signal goes high. Details about the parameters are listed in Table5. CHIP_EN t1t0 Strapping pin VIL_nRST VIH Figure 6: Setup and Hold Times for the Strapping Pins Espressif Systems 14 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

T able 5: Parameter Descriptions of Setup and Hold Times for the Strapping Pins Min Parameter Description (ms) t0 Setup time before CHIP_EN goes from low to high 0 t1 Hold time after CHIP_EN goes high 3 Espressif Systems 15 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

3 Functional Description

Functional Description This chapter describes the functions of ESP32-C3.

3.1 CPU and Memory

3.1.1 CPU

ESP32-C3 has a low-power 32-bit RISC-V single-core microprocessor with the following features:

four-stage pipeline that supports a clock frequency of up to 160 MHz
RV32IMC ISA
32-bit multiplier and 32-bit divider
up to 32 vectored interrupts at seven priority levels
up to 8 hardware breakpoints/watchpoints
up to 16 PMP regions
JTAG for debugging

3.1.2 Internal Memory

ESP32-C3’s internal memory includes:

384 KB of ROM: for booting and core functions.
400 KB of onchip SRAM: for data and instructions, running at a configurable frequency of up to 160 MHz. Of the 400 KB SRAM, 16 KB is configured for cache.
RTC FAST memory: 8 KB of SRAM that can be accessed by the main CPU. It can retain data in Deep-sleep mode.
4 Kbit of eFuse: 1792 bits are reserved for your data, such as encryption key and device ID.
Embedded flash : See details in Chapter1 ESP32-C3 Series Comparison.

3.1.3 External Flash

ESP32-C3 supports SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to multiple external flash. CPU’s instruction memory space and read-only data memory space can map into external flash of ESP32-C3, whose size can be 16 MB at most. ESP32-C3 supports hardware encryption/decryption based on XTS-AES to protect developers’ programs and data in flash. Through high-speed caches, ESP32-C3 can support at a time up to:

8 MB of instruction memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and 32-bit reads are supported.
8 MB of data memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and 32-bit reads are supported. Note: After ESP32-C3 is initialized, software can customize the mapping of external flash into the CPU address space. Espressif Systems 16 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

3.1.4 Address Mapping Structure

Figure 7: Address Mapping Structure Note: The memory space with gray background is not available for use.

3.1.5 Cache

ESP32-C3 has an eight-way set associative cache. This cache is read-only and has the following features:

size: 16 KB
block size: 32 bytes
pre-load function
lock function
critical word first and early restart Espressif Systems 17 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

3.2 System Clocks

3.2.1 CPU Clock

The CPU clock has three possible sources:

external main crystal clock
fast RC oscillator (typically about 17.5 MHz, and adjustable)
PLL clock The application can select the clock source from the three clocks above. The selected clock source drives the CPU clock directly, or after division, depending on the application. Once the CPU is reset, the default clock source would be the external main crystal clock divided by 2.

3.2.2 RTC Clock

The RTC slow clock is used for RTC counter, RTC watchdog and low-power controller. It has three possible sources:

external low-speed (32 kHz) crystal clock
internal slow RC oscillator (typically about 136 kHz, and adjustable)
internal fast RC oscillator divided clock (derived from the fast RC oscillator divided by 256) The RTC fast clock is used for RTC peripherals and sensor controllers. It has two possible sources:
external main crystal clock divided by 2
internal fast RC oscillator divide-by-N clock (typically about 17.5 MHz, and adjustable)

3.3 Analog Peripherals

3.3.1 AnalogtoDigital Converter (ADC)

ESP32-C3 integrates two 12-bit SAR ADCs.

ADC1 supports measurements on 5 channels, and is factory-calibrated.
ADC2 supports measurements on 1 channel, and is not factory-calibrated. For ADC characteristics, please refer to Table15.

3.3.2 T emperature Sensor

The temperature sensor generates a voltage that varies with temperature. The voltage is internally converted via an ADC into a digital value. The temperature sensor has a range of –40 °C to 125 °C. It is designed primarily to sense the temperature changes inside the chip. The temperature value depends on factors like microcontroller clock frequency or I/O load. Generally, the chip’s internal temperature is higher than the operating ambient temperature.

3.4 Digital Peripherals

3.4.1 General Purpose Input / Output Interface (GPIO)

ESP32-C3 has 22 GPIO pins which can be assigned various functions by configuring corresponding registers. Besides digital signals, some GPIOs can be also used for analog functions, such as ADC. Espressif Systems 18 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

All GPIOs have selectable internal pull-up or pull-down, or can be set to high impedance. When these GPIOs are configured as an input, the input value can be read by software through the register. Input GPIOs can also be set to generate edge-triggered or level-triggered CPU interrupts. All digital IO pins are bi-directional, non-inverting and tristate, including input and output buffers with tristate control. These pins can be multiplexed with other functions, such as the UART, SPI, etc. For low-power operations, the GPIOs can be set to holding state. The IO MUX and the GPIO matrix are used to route signals from peripherals to GPIO pins. Together they provide highly configurable I/O. Using GPIO Matrix, peripheral input signals can be configured from any IO pins while peripheral output signals can be configured to any IO pins. Table6 shows the IO MUX functions of each pin. For more information about IO MUX and GPIO matrix, please refer to Chapter IO MUX and GPIO Matrix (GPIO, IO_MUX) inESP32-C3 Technical Reference Manual. T able 6: IO MUX Pin Functions Name No. Function 0 Function 1 Function 2 Reset Notes XTAL_32K_P 4 GPIO0 GPIO0 — 0 R XTAL_32K_N 5 GPIO1 GPIO1 — 0 R GPIO2 6 GPIO2 GPIO2 FSPIQ 1 R GPIO3 8 GPIO3 GPIO3 — 1 R MTMS 9 MTMS GPIO4 FSPIHD 1 R MTDI 10 MTDI GPIO5 FSPIWP 1 R MTCK 12 MTCK GPIO6 FSPICLK 1* G MTDO 13 MTDO GPIO7 FSPID 1 G GPIO8 14 GPIO8 GPIO8 — 1 — GPIO9 15 GPIO9 GPIO9 — 3 — GPIO10 16 GPIO10 GPIO10 FSPICS0 1 G VDD_SPI 18 GPIO11 GPIO11 — 0 — SPIHD 19 SPIHD GPIO12 — 3 — SPIWP 20 SPIWP GPIO13 — 3 — SPICS0 21 SPICS0 GPIO14 — 3 — SPICLK 22 SPICLK GPIO15 — 3 — SPID 23 SPID GPIO16 — 3 — SPIQ 24 SPIQ GPIO17 — 3 — GPIO18 25 GPIO18 GPIO18 — 0 USB, G GPIO19 26 GPIO19 GPIO19 — 0* USB U0RXD 27 U0RXD GPIO20 — 3 G U0TXD 28 U0TXD GPIO21 — 4 — Reset The default configuration of each pin after reset:

0 - input disabled, in high impedance state (IE = 0)
1 - input enabled, in high impedance state (IE = 1)
2 - input enabled, pull-down resistor enabled (IE = 1, WPD = 1)
3 - input enabled, pull-up resistor enabled (IE = 1, WPU = 1)
4 - output enabled, pull-up resistor enabled (OE = 1, WPU = 1) Espressif Systems 19 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

0* - input disabled, pull-up resistor enabled (IE = 0, WPU = 0, USB_WPU = 1). See details in Notes
1* - When the value of eFuse bit EFUSE_DIS_PAD_JTAG is 0, input enabled, pull-up resistor enabled (IE = 1, WPU = 1) 1, input enabled, in high impedance state (IE = 1) We recommend pulling high or low GPIO pins in high impedance state to avoid unnecessary power consumption. You may add pull-up and pull-down resistors in your PCB design referring to Table14, or enable internal pull-up and pull-down resistors during software initialization. Notes
R - These pins have analog functions.
USB - GPIO18 and GPIO19 are USB pins. The pull-up value of a USB pin is controlled by the pin’s pull-up value together with USB pull-up value. If any of the two pull-up values is 1, the pin’s pull-up resistor will be enabled. The pull-up resistors of USB pins are controlled by USB_SERIAL_JTAG_DP_PULLUP bit.
G - These pins have glitches during power-up. See details in Table7. T able 7: PowerUp Glitches on Pins T ypical Time Period Pin Glitch1 (ns) MTCK Low-level glitch 5 MTDO Low-level glitch 5 GPIO10 Low-level glitch 5 U0RXD Low-level glitch 5 GPIO18 Pull-up glitch 50000

1 Low-level glitch: the pin is at a low level during the time period;

High-level glitch: the pin is at a high level during the time period; Pull-up glitch: the pin is pulled up during the time period; Pull-down glitch: the pin is pulled down during the time period.

3.4.2 Serial Peripheral Interface (SPI)

ESP32-C3 features three SPI interfaces (SPI0, SPI1, and SPI2). SPI0 and SPI1 can only be configured to operate in SPI memory mode, while SPI2 can be configured to operate in both SPI memory and general-purpose SPI modes.

SPI Memory mode In SPI memory mode, SPI0, SPI1 and SPI2 interface with external SPI memory. Data is transferred in bytes. Up to four-line STR reads and writes are supported. The clock frequency is configurable to a maximum of 120 MHz in STR mode.
SPI2 Generalpurpose SPI (GPSPI) mode When SPI2 acts as a general-purpose SPI, it can operate in master and slave modes. SPI2 supports two-line full-duplex communication and single-/two-/four-line half-duplex communication in both master and slave modes. The host’s clock frequency is configurable. Data is transferred in bytes. The clock polarity (CPOL) and phase (CPHA) are also configurable. The SPI2 interface can connect to GDMA. – In master mode, the clock frequency is 80 MHz at most, and the four modes of SPI transfer format are supported. Espressif Systems 20 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

– In slave mode, the clock frequency is 60 MHz at most, and the four modes of SPI transfer format are also supported. The mapping between SPI bus signals and GPIO pins is shown in Table8: T able 8: Mapping of SPI Signals and Chip Pads FullDuplex HalfDuplex Chip Pin Signal SPI Signal SPI Signal Pin Function FSPI Signals MOSI MOSI D FSPID MISO (MISO) Q FSPIQ CS CS CS FSPICS0 ~ 5 CLK CLK CLK FSPICLK — — WP FSPIWP — — HD FSPIHD In most cases, the data port connection between ESP32-C3 and external flash is as follows: T able 9: Connection Between ESP32C3 and External Flash External Flash Data Port Chip Pin SPI SingleLine Mode SPI T woLine Mode SPI FourLine Mode SPID (SPID) DI IO0 IO0 SPIQ (SPIQ) DO IO1 IO1 SPIWP (SPIWP) WP# — IO2 SPIHD (SPIHD) HOLD# — IO3

3.4.3 Universal Asynchronous Receiver T ransmitter (UART)

ESP32-C3 has two UART interfaces, i.e. UART0 and UART1, which support IrDA and asynchronous communication (RS232 and RS485) at a speed of up to 5 Mbps. The UART controller provides hardware flow control (CTS and RTS signals) and software flow control (XON and XOFF). Both UART interfaces connect to GDMA via UHCI0, and can be accessed by the GDMA controller or directly by the CPU.

3.4.4 I2C Interface

ESP32-C3 has an I2C bus interface which is used for I2C master mode or slave mode, depending on your configuration. The I2C interface supports:

standard mode (100 Kbit/s)
fast mode (400 Kbit/s)
up to 800 Kbit/s (constrained by SCL and SDA pull-up strength)
7-bit and 10-bit addressing mode
double addressing mode
7-bit broadcast address You can configure instruction registers to control the I2C interface for more flexibility. Espressif Systems 21 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

3.4.5 I2S Interface

ESP32-C3 includes a standard I2S interface. This interface can operate as a master or a slave in full-duplex mode or half-duplex mode, and can be configured for 8-bit, 16-bit, 24-bit, or 32-bit serial communication. BCK clock frequency, from 10 kHz up to 40 MHz, is supported. The I2S interface supports TDM PCM, TDM MSB alignment, TDM standard, and PDM TX interface. It connects to the GDMA controller.

3.4.6 Remote Control Peripheral

The Remote Control Peripheral (RMT) supports two channels of infrared remote transmission and two channels of infrared remote reception. By controlling pulse waveform through software, it supports various infrared and other single wire protocols. All four channels share a 192 × 32-bit memory block to store transmit or receive waveform.

3.4.7 LED PWM Controller

The LED PWM controller can generate independent digital waveform on six channels. The LED PWM controller:

can generate digital waveform with configurable periods and duty cycle. The accuracy of duty cycle can be up to 18 bits.
has multiple clock sources, including APB clock and external main crystal clock.
can operate when the CPU is in Light-sleep mode.
supports gradual increase or decrease of duty cycle, which is useful for the LED RGB color-gradient generator.

3.4.8 General DMA Controller

ESP32-C3 has a general DMA controller (GDMA) with six independent channels, i.e. three transmit channels and three receive channels. These six channels are shared by peripherals with DMA feature. The GDMA controller implements a fixed-priority scheme among these channels, whose priority can be configured. The GDMA controller controls data transfer using linked lists. It allows peripheral-to-memory and memory-to-memory data transfer at a high speed. All channels can access internal RAM. Peripherals on ESP32-C3 with DMA feature are SPI2, UHCI0, I2S, AES, SHA, and ADC.

3.4.9 USB Serial/JT AG Controller

ESP32-C3 integrates a USB Serial/JTAG controller. This controller has the following features:

USB 2.0 full speed compliant, capable of up to 12 Mbit/s transfer speed (Note that this controller does not support the faster 480 Mbit/s high-speed transfer mode)
CDC-ACM virtual serial port and JTAG adapter functionality
programming embedded/external flash
CPU debugging with compact JTAG instructions
a full-speed USB PHY integrated in the chip

3.4.10 TWAI® Controller

ESP32-C3 has a TWAI® controller with the following features: Espressif Systems 22 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

compatible with ISO 11898-1 protocol (CAN Specification 2.0)
standard frame format (11-bit ID) and extended frame format (29-bit ID)
bit rates from 1 Kbit/s to 1 Mbit/s
multiple modes of operation: Normal, Listen Only, and Self-Test (no acknowledgment required)
64-byte receive FIFO
acceptance filter (single and dual filter modes)
error detection and handling: error counters, configurable error interrupt threshold, error code capture, arbitration lost capture

3.5 Radio and WiFi

ESP32-C3 radio consists of the following blocks:

2.4 GHz receiver
2.4 GHz transmitter
bias and regulators
balun and transmit-receive switch
clock generator 3.5.1 2.4 GHz Receiver The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them to the digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions, ESP32-C3 integrates RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits, and baseband filters. 3.5.2 2.4 GHz T ransmitter The 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives the antenna with a high-powered CMOS power amplifier. The use of digital calibration further improves the linearity of the power amplifier. Additional calibrations are integrated to cancel any radio imperfections, such as:
carrier leakage
I/Q amplitude/phase matching
baseband nonlinearities
RF nonlinearities
antenna matching These built-in calibration routines reduce the cost, time, and specialized equipment required for product testing. Espressif Systems 23 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

3.5.3 Clock Generator

The clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. All components of the clock generator are integrated into the chip, including inductors, varactors, filters, regulators and dividers. The clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise are optimized on chip with patented calibration algorithms which ensure the best performance of the receiver and the transmitter.

3.5.4 WiFi Radio and Baseband

ESP32-C3 Wi-Fi radio and baseband support the following features:

802.11b/g/n
802.11n MCS0-7 that supports 20 MHz and 40 MHz bandwidth
802.11n MCS32
802.11n 0.4µs guard interval
data rate up to 150 Mbps
RX STBC (single spatial stream)
adjustable transmitting power
antenna diversity ESP32-C3 supports antenna diversity with an external RF switch. This switch is controlled by one or more GPIOs, and used to select the best antenna to minimize the effects of channel imperfections.

3.5.5 WiFi MAC

ESP32-C3 implements the full 802.11 b/g/n Wi-Fi MAC protocol. It supports the Basic Service Set (BSS) STA and SoftAP operations under the Distributed Control Function (DCF). Power management is handled automatically with minimal host interaction to minimize the active duty period. ESP32-C3 Wi-Fi MAC applies the following low-level protocol functions automatically:

4 × virtual Wi-Fi interfaces
infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode
RTS protection, CTS protection, Immediate Block ACK
fragmentation and defragmentation
TX/RX A-MPDU, TX/RX A-MSDU
transmit opportunity (TXOP)
Wi-Fi multimedia (WMM)
GCMP, CCMP, TKIP, WAPI, WEP, BIP, WPA2-PSK/WPA2-Enterprise, and WPA3-PSK/WPA3-Enterprise
automatic beacon monitoring (hardware TSF)
802.11mc FTM Espressif Systems 24 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

3.5.6 Networking Features

Espressif provides libraries for TCP/IP networking, ESP-WIFI-MESH networking, and other networking protocols

3.6 Bluetooth LE

ESP32-C3 includes a Bluetooth Low Energy subsystem that integrates a hardware link layer controller, an RF/modem block and a feature-rich software protocol stack. It supports the core features of Bluetooth 5 and Bluetooth mesh.

3.6.1 Bluetooth LE Radio and PHY

Bluetooth Low Energy radio and PHY in ESP32-C3 support:

1 Mbps PHY
2 Mbps PHY for higher data rates
coded PHY for longer range (125 Kbps and 500 Kbps)
listen before talk (LBT), implemented in hardware
antenna diversity with an external RF switch This switch is controlled by one or more GPIOs, and used to select the best antenna to minimize the effects of channel imperfections.

3.6.2 Bluetooth LE Link Layer Controller

Bluetooth Low Energy Link Layer Controller in ESP32-C3 supports:

LE advertising extensions, to enhance broadcasting capacity and broadcast more intelligent data
multiple advertisement sets
simultaneous advertising and scanning
multiple connections in simultaneous central and peripheral roles
adaptive frequency hopping and channel assessment
LE channel selection algorithm #2
connection parameter update
high duty cycle non-connectable advertising
LE privacy 1.2
LE data packet length extension
link layer extended scanner filter policies
low duty cycle directed advertising
link layer encryption
LE Ping Espressif Systems 25 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

3.7 Low Power Management

With the use of advanced power-management technologies, ESP32-C3 can switch between different power modes.

Active mode: CPU and chip radio are powered on. The chip can receive, transmit, or listen.
Modem-sleep mode: The CPU is operational and the clock speed can be reduced. Wi-Fi base band, Bluetooth LE base band, and radio are disabled, but Wi-Fi and Bluetooth LE connection can remain active.
Light-sleep mode: The CPU is paused. Any wake-up events (MAC, host, RTC timer, or external interrupts) will wake up the chip. Wi-Fi and Bluetooth LE connection can remain active.
Deep-sleep mode: CPU and most peripherals are powered down. Only the RTC memory is powered on. Wi-Fi connection data are stored in the RTC memory. For power consumption in different power modes, please refer to Table17.

3.8 Timers

3.8.1 General Purpose Timers

ESP32-C3 is embedded with two 54-bit general-purpose timers, which are based on 16-bit prescalers and 54-bit auto-reload-capable up/down-timers. The timers’ features are summarized as follows:

a 16-bit clock prescaler, from 1 to 65536
a 54-bit time-base counter programmable to be incrementing or decrementing
able to read real-time value of the time-base counter
halting and resuming the time-base counter
programmable alarm generation
level interrupt generation

3.8.2 System Timer

ESP32-C3 integrates a 52-bit system timer, which has two 52-bit counters and three comparators. The system timer has the following features:

counters with a fixed clock frequency of 16 MHz
three types of independent interrupts generated according to alarm value
two alarm modes: target mode and period mode
52-bit target alarm value and 26-bit periodic alarm value
automatic reload of counter value
counters can be stalled if the CPU is stalled or in OCD mode

3.8.3 Watchdog Timers

ESP32-C3 contains three watchdog timers: one in each of the two timer groups (called Main System Watchdog Timers, or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT). Espressif Systems 26 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

During the flash boot process, RWDT and the MWDT in timer group 0 (TIMG0) are enabled automatically in order to detect and recover from booting errors. Watchdog timers have the following features:

four stages, each with a programmable timeout value. Each stage can be configured, enabled and disabled separately
interrupt, CPU reset, or core reset for MWDT upon expiry of each stage; interrupt, CPU reset, core reset, or system reset for RWDT upon expiry of each stage
32-bit expiry counter
write protection, to prevent RWDT and MWDT configuration from being altered inadvertently
flash boot protection If the boot process from an SPI flash does not complete within a predetermined period of time, the watchdog will reboot the entire main system.

3.9 Cryptographic Hardware Accelerators

ESP32-C3 is equipped with hardware accelerators of general algorithms, such as AES-128/AES-256 (FIPS PUB 197), ECB/CBC/OFB/CFB/CTR (NIST SP 800-38A), SHA1/SHA224/SHA256 (FIPS PUB 180-4), and RSA3072. The chip also supports independent arithmetic, such as Big Integer Multiplication and Big Integer Modular Multiplication. The maximum operation length for RSA and Big Integer Modular Multiplication is 3072 bits. The maximum factor length for Big Integer Multiplication is 1536 bits.

3.10 Physical Security Features

Transparent external flash encryption (AES-XTS algorithm) with software inaccessible key prevents unauthorized readout of your application code or data.
Secure boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature) can be booted.
HMAC module can use a software inaccessible MAC key to generate MAC signatures for identity verification and other purposes.
Digital Signature module can use a software inaccessible secure key to generate RSA signatures for identity verification.
World Controller provides two running environments for software. All hardware and software resources are sorted to two groups, and placed in either secure or general world. The secure world cannot be accessed by hardware in the general world, thus establishing a security boundary.

3.11 Peripheral Pin Configurations

T able 10: Peripheral Pin Configurations Interface Signal Pin Function ADC ADC1_CH0 XTAL_32K_P Two 12-bit SAR ADCs ADC1_CH1 XTAL_32K_N ADC1_CH2 GPIO2 Espressif Systems 27 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

Interface Signal Pin Function ADC1_CH3 GPIO3 ADC1_CH4 MTMS ADC2_CH0 MTDI JTAG MTDI MTDI JTAG for software debugging MTCK MTCK MTMS MTMS MTDO MTDO UART U0RXD_in Any GPIO pins Two UART channels with hardware flow control and GDMAU0CTS_in U0DSR_in U0TXD_out U0RTS_out U0DTR_out U1RXD_in U1CTS_in U1DSR_in U1TXD_out U1RTS_out U1DTR_out I2C I2CEXT0_SCL_in Any GPIO pins One I2C channel in slave or master mode I2CEXT0_SDA_in I2CEXT1_SCL_in I2CEXT1_SDA_in I2CEXT0_SCL_out I2CEXT0_SDA_out I2CEXT1_SCL_out I2CEXT1_SDA_out LED PWM ledc_ls_sig_out0~5 Any GPIO pins Six independent PWM channels I2S I2S0O_BCK_in Any GPIO pins Stereo input and output from/to the audiocodec I2S_MCLK_in I2SO_WS_in I2SI_SD_in I2SI_BCK_in I2SI_WS_in I2SO_BCK_out I2S_MCLK_out I2SO_WS_out I2SO_SD_out I2SI_BCK_out I2SI_WS_out I2SO_SD1_out Remote Control Peripheral RMT_SIG_IN0~1 Any GPIO pins Two channels for an IR transceiver of various waveformsRMT_SIG_OUT0~1 Espressif Systems 28 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

Interface Signal Pin Function SPI0/1 SPICLK_out_mux SPICLK Support Standard SPI, Dual SPI, Quad SPI, and QPI that allow connection to external flashSPICS0_out SPICS0 SPICS1_out Any GPIO pins SPID_in/_out SPID SPIQ_in/_out SPIQ SPIWP_in/_out SPIWP SPIHD_in/_out SPIHD SPI2 FSPICLK_in/_out_mux Any GPIO pins • Master mode and slave mode of SPI, Dual SPI, Quad SPI, and QPI

Connection to external flash, RAM, and other SPI devices
Four modes of SPI transfer format
Configurable SPI frequency
64-byte FIFO or GDMA buffer FSPICS0_in/_out FSPICS1~5_out FSPID_in/_out FSPIQ_in/_out FSPIWP_in/_out FSPIHD_in/_out USB Serial/JTAG USB_D+ GPIO19 USB-to-serial converter, and USB-to-JTAG converterUSB_D- GPIO18 TWAI twai_rx Any GPIO pins Compatible with ISO 11898-1 protocol twai_tx twai_bus_off_on twai_clkout Espressif Systems 29 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

4 Electrical Characteristics

Electrical Characteristics

4.1 Absolute Maximum Ratings

Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the device. These are stress ratings only, and do not refer to the functional operation of the device. T able 11: Absolute Maximum Ratings Symbol Parameter Min Max Unit VDDA, VDD3P3, VDD3P3_RTC, VDD3P3_CPU, VDD_SPI Voltageappliedtopowersupplypins per power domain –0.3 3.6 V TSTORE Storage temperature –40 150 °C

4.2 Recommended Operating Conditions

T able 12: Recommended Operating Conditions Symbol Parameter Min T yp Max Unit VDDA, VDD3P3 Voltage applied to power supply pins per 3.0 3.3 3.6 VVDD3P3_RTC power domain VDD_SPI (working as input power supply)1 — 3.0 3.3 3.6 V VDD3P3_CPU2, 3 Voltage applied to power supply pin 3.0 3.3 3.6 V IV DD4 Current delivered by external power supply 0.5 — — A TA Operating ambient temperature ESP32-C3 –40 — 105 °CESP32-C3FN4 85 ESP32-C3FH4 105 1 For more information, please refer to Section2.3 Power Scheme.

2 When VDD_SPI is used to drive peripherals, VDD3P3_CPU should comply with the peripherals’ speci-

fications. For more information, please refer to Table13. 3 To write eFuse, VDD3P3_CPU should not be higher than 3.3 V. 4 If you use a single power supply, the recommended output current is 500 mA or more.

4.3 VDD_SPI Output Characteristics

T able 13: VDD_SPI Output Characteristics Symbol Parameter T yp Unit RSPI On-resistance in 3.3 V mode 7.5 Ω Espressif Systems 30 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

Note: In real-life applications, when VDD_SPI works in 3.3 V output mode, VDD3P3_CPU may be affected by RSPI . For example, when VDD3P3_CPU is used to drive a 3.3 V flash, it should comply with the following specifications: VDD3P3_CPU > VDD_flash_min + I_flash_max*RSPI Among which, VDD_flash_min is the minimum operating voltage of the flash, and I_flash_max the maximum current. For more information, please refer to section2.3 Power Scheme. 4.4 DC Characteristics (3.3 V , 25 °C) T able 14: DC Characteristics (3.3 V , 25 °C) Symbol Parameter Min T yp Max Unit CIN Pin capacitance — 2 — pF VIH High-level input voltage 0.75 × VDD1 — VDD1+ 0.3 V VIL Low-level input voltage –0.3 — 0.25 × VDD1 V IIH High-level input current — — 50 nA IIL Low-level input current — — 50 nA VOH 2 High-level output voltage 0.8 × VDD1 — — V VOL2 Low-level output voltage — — 0.1 × VDD1 V IOH High-level source current (VDD1= 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3) — 40 — mA IOL Low-level sink current (VDD1= 3.3 V, VOL =

0.495 V, PAD_DRIVER = 3) — 28 — mA

RPU Pull-up resistor — 45 — kΩ RPD Pull-down resistor — 45 — kΩ VIH_nRST Chip reset release voltage 0.75 × VDD1 — VDD1+ 0.3 V VIL_nRST Chip reset voltage –0.3 — 0.25 × VDD1 V 1 VDD is the I/O voltage for a particular power domain of pins. 2 VOH and VOL are measured using high-impedance load.

4.5 ADC Characteristics

T able 15: ADC Characteristics Symbol Parameter Min Max Unit DNL (Differential nonlinearity)1 ADC connected to an external –7 7 LSB100 nF capacitor; DC signal input; INL (Integral nonlinearity) ambient temperature at 25 °C; –12 12 LSBWi-Fi off Sampling rate — — 100 kSPS 2 Effective Range ATTEN0 0 750 mV ATTEN1 0 1050 mV ATTEN2 0 1300 mV ATTEN3 0 2500 mV Espressif Systems 31 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

1 TogetbetterDNLresults,youcansamplemultipletimesandapplyafilter,orcalculatetheaveragevalue. 2 kSPS means kilo samples-per-second.

4.6 Current Consumption

The current consumption measurements are taken with a 3.3 V supply at 25 °C of ambient temperature at the RF port. All transmitters’ measurements are based on a 100% duty cycle. T able 16: Current Consumption Depending on RF Modes Work mode Description Peak (mA) Active (RF working) TX 802.11b, 1 Mbps, @21 dBm 335 802.11g, 54 Mbps, @19 dBm 285 802.11n, HT20, MCS7, @18.5 dBm 276 802.11n, HT40, MCS7, @18.5 dBm 278 RX 802.11b/g/n, HT20 84 802.11n, HT40 87 T able 17: Current Consumption Depending on Work Modes Work mode Description T yp Unit Modem-sleep1, 2 The CPU is powered on3

160 MHz 20 mA

80 MHz 15 mA

Light-sleep — 130 µA Deep-sleep RTC timer + RTC memory 5 µA Power off CHIP_PU is set to low level, the chip is powered off 1 µA

1 The current consumption figures in Modem-sleep mode are for cases where the CPU is powered on and

the cache idle. 2 When Wi-Fi is enabled, the chip switches between Active and Modem-sleep modes. Therefore, current consumption changes accordingly. 3 In Modem-sleep mode, the CPU frequency changes automatically. The frequency depends on the CPU load and the peripherals used.

4.7 Reliability

T able 18: Reliability Qualifications T est Item T est Conditions T est Standard HTOL (High Temperature Operating Life) 125 °C, 1000 hours JESD22-A108 ESD (Electro-Static Discharge Sensitivity) HBM (Human Body Mode)1± 2000 V JS-001 CDM (Charge Device Mode)2± 1000 V JS-002 Latch up Current trigger ± 200 mA JESD78Voltage trigger 1.5 × VDDmax Cont’d on next page Espressif Systems 32 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

T able 18 – cont’d from previous page T est Item T est Conditions T est Standard Preconditioning Bake 24 hours @125 °C Moisture soak (level 3: 192 hours @30 °C, 60% RH) IR reflow solder: 260 + 0 °C, 20 seconds, three times J-STD-020, JESD47, JESD22-A113 TCT (Temperature Cycling Test) –65 °C / 150 °C, 500 cycles JESD22-A104 uHAST (Highly Accelerated Stress Test, unbiased) 130 °C, 85% RH, 96 hours JESD22-A118 HTSL (High Temperature Storage Life) 150 °C, 1000 hours JESD22-A103 LTSL (Low Temperature Storage Life) – 40 °C, 1000 hours JESD22-A119 1 JEDECdocumentJEP155statesthat500VHBMallowssafemanufacturingwithastandardESDcontrolprocess. 2 JEDECdocumentJEP157statesthat250VCDMallowssafemanufacturingwithastandardESDcontrolprocess.

4.8 WiFi Radio

T able 19: WiFi Frequency Min T yp Max Parameter (MHz) (MHz) (MHz) Center frequency of operating channel 2412 — 2484

4.8.1 WiFi RF T ransmitter (TX) Specifications

T able 20: TX Power with Spectral Mask and EVM Meeting 802.11 Standards Min T yp Max Rate (dBm) (dBm) (dBm) 802.11b, 1 Mbps — 21.0 — 802.11b, 11 Mbps — 21.0 — 802.11g, 6 Mbps — 21.0 — 802.11g, 54 Mbps — 19.0 — 802.11n, HT20, MCS0 — 20.0 — 802.11n, HT20, MCS7 — 18.5 — 802.11n, HT40, MCS0 — 20.0 — 802.11n, HT40, MCS7 — 18.5 — Espressif Systems 33 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

T able 21: TX EVM T est Min T yp SL1 Rate (dB) (dB) (dB) 802.11b, 1 Mbps, @21 dBm — –24.5 –10 802.11b, 11 Mbps, @21 dBm — –25.0 –10 802.11g, 6 Mbps, @21 dBm — –23.0 –5 802.11g, 54 Mbps, @19 dBm — –27.5 –25 802.11n, HT20, MSC0, @20 dBm — –22.5 –5 802.11n, HT20, MSC7, @18.5 dBm — –29.0 –27 802.11n, HT40, MSC0, @20 dBm — –22.5 –5 802.11n, HT40, MSC7, @18.5 dBm — –28.0 –27 1 SL stands for standard limit value.

4.8.2 WiFi RF Receiver (RX) Specifications

T able 22: RX Sensitivity Min T yp Max Rate (dBm) (dBm) (dBm) 802.11b, 1 Mbps — –98.4 — 802.11b, 2 Mbps — –96.0 — 802.11b, 11 Mbps — –88.6 — 802.11g, 6 Mbps — –93.8 — 802.11g, 9 Mbps — –92.2 — 802.11g, 12 Mbps — –91.0 — 802.11g, 18 Mbps — –88.4 — 802.11g, 24 Mbps — –85.8 — 802.11g, 36 Mbps — –82.0 — 802.11g, 48 Mbps — –78.0 — 802.11g, 54 Mbps — –76.6 — 802.11n, HT20, MCS0 — –93.6 — 802.11n, HT20, MCS1 — –90.8 — 802.11n, HT20, MCS2 — –88.4 — 802.11n, HT20, MCS3 — –85.0 — 802.11n, HT20, MCS4 — –81.8 — 802.11n, HT20, MCS5 — –77.8 — 802.11n, HT20, MCS6 — –76.0 — 802.11n, HT20, MCS7 — –74.8 — 802.11n, HT40, MCS0 — –90.0 — 802.11n, HT40, MCS1 — –88.0 — 802.11n, HT40, MCS2 — –85.2 — 802.11n, HT40, MCS3 — –82.0 — 802.11n, HT40, MCS4 — –78.8 — Cont’d on next page Espressif Systems 34 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

T able 22 – cont’d from previous page Min T yp Max Rate (dBm) (dBm) (dBm) 802.11n, HT40, MCS5 — –74.6 — 802.11n, HT40, MCS6 — –73.0 — 802.11n, HT40, MCS7 — –71.4 — T able 23: Maximum RX Level Min T yp Max Rate (dBm) (dBm) (dBm) 802.11b, 1 Mbps — 5 — 802.11b, 11 Mbps — 5 — 802.11g, 6 Mbps — 5 — 802.11g, 54 Mbps — 0 — 802.11n, HT20, MCS0 — 5 — 802.11n, HT20, MCS7 — 0 — 802.11n, HT40, MCS0 — 5 — 802.11n, HT40, MCS7 — 0 — T able 24: RX Adjacent Channel Rejection Min T yp Max Rate (dB) (dB) (dB) 802.11b, 1 Mbps — 35 — 802.11b, 11 Mbps — 35 — 802.11g, 6 Mbps — 31 — 802.11g, 54 Mbps — 20 — 802.11n, HT20, MSC0 — 31 — 802.11n, HT20, MSC7 — 16 — 802.11n, HT40, MSC0 — 25 — 802.11n, HT40, MSC7 — 11 —

4.9 Bluetooth LE Radio

T able 25: Bluetooth LE Frequency Min T yp MaxParameter (MHz) (MHz) (MHz) Center frequency of operating channel 2402 — 2480 Espressif Systems 35 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

4.9.1 Bluetooth LE RF T ransmitter (TX) Specifications

T able 26: T ransmitter Characteristics Bluetooth LE 1 Mbps Parameter Description Min T yp Max Unit RF transmit power RF power control range –27.00 0 18.00 dBm Gain control step — 3.00 — dB Carrier frequency offset and drift Max |fn|n=0, 1, 2, ..k — 17.00 — kHz Max |f0 − fn| — 1.75 — kHz Modulation characteristics ∆ f1avg — 250.00 — kHz Min ∆ f2max (for at least 99.9% of all∆ f2max) — 190.00 — kHz ∆ f2avg/∆ f1avg — 0.83 — — In-band spurious emissions ± 2 MHz offset — –37.62 — dBm ± 3 MHz offset — –41.95 — dBm ± > 3 MHz offset — –44.48 — dBm T able 27: T ransmitter Characteristics Bluetooth LE 2 Mbps Parameter Description Min T yp Max Unit RF transmit power RF power control range –27.00 0 18.00 dBm Gain control step — 3.00 — dB Carrier frequency offset and drift Max |fn|n=0, 1, 2, ..k — 20.80 — kHz Max |f0 − fn| — 1.30 — kHz Modulation characteristics ∆ f1avg — 498.00 — kHz Min ∆ f2max (for at least 99.9% of all∆ f2max) — 430.00 — kHz ∆ f2avg/∆ f1avg — 0.93 — — In-band spurious emissions ± 4 MHz offset — –43.55 — dBm ± 5 MHz offset — –45.26 — dBm ± > 5 MHz offset — –45.26 — dBm T able 28: T ransmitter Characteristics Bluetooth LE 125 Kbps Parameter Description Min T yp Max Unit RF transmit power RF power control range –27.00 0 18.00 dBm Gain control step — 3.00 — dB Carrier frequency offset and drift Max |fn|n=0, 1, 2, ..k — 17.50 — kHz Max |f0 − fn| — 0.45 — kHz Cont’d on next page Espressif Systems 36 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

T able 28 – cont’d from previous page Parameter Description Min T yp Max Unit Modulation characteristics ∆ f1avg — 250.00 — kHz Min ∆ f1max (for at least 99.9% of all∆ f2max) — 235.00 — kHz In-band spurious emissions ± 2 MHz offset — –37.90 — dBm ± 3 MHz offset — –41.00 — dBm ± > 3 MHz offset — –42.50 — dBm T able 29: T ransmitter Characteristics Bluetooth LE 500 Kbps Parameter Description Min T yp Max Unit RF transmit power RF power control range –27.00 0 18.00 dBm Gain control step — 3.00 — dB Carrier frequency offset and drift Max |fn|n=0, 1, 2, ..k — 17.00 — kHz Max |f0 − fn| — 0.88 — kHz Modulation characteristics ∆ f2avg — 208.00 — kHz Min ∆ f2max (for at least 99.9% of all∆ f2max) — 190.00 — kHz In-band spurious emissions ± 2 MHz offset — –37.90 — dBm ± 3 MHz offset — –41.30 — dBm ± > 3 MHz offset — –42.80 — dBm

4.9.2 Bluetooth LE RF Receiver (RX) Specifications

T able 30: Receiver Characteristics Bluetooth LE 1 Mbps Parameter Description Min T yp Max Unit Sensitivity @30.8% PER — — –97 — dBm Maximum received signal @30.8% PER — — 5 — dBm Co-channel C/I — — 8 — dB Adjacent channel selectivity C/I F = F0 + 1 MHz — –3 — dB F = F0 – 1 MHz — –4 — dB F = F0 + 2 MHz — –29 — dB F = F0 – 2 MHz — –31 — dB F = F0 + 3 MHz — –33 — dB F = F0 – 3 MHz — –27 — dB F ≥ F0 + 4 MHz — –29 — dB F ≤ F0 – 4 MHz — –38 — dB Image frequency — — –29 — dB Adjacent channel to image frequency F = Fimage + 1 MHz — –41 — dB F = Fimage – 1 MHz — –33 — dB Cont’d on next page Espressif Systems 37 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

T able 30 – cont’d from previous page Parameter Description Min T yp Max Unit Out-of-band blocking performance

30 MHz~ 2000 MHz — –5 — dBm

2003 MHz~ 2399 MHz — –18 — dBm

2484 MHz~ 2997 MHz — –15 — dBm

3000 MHz~ 12.75 GHz — –5 — dBm Intermodulation — — –30 — dBm T able 31: Receiver Characteristics Bluetooth LE 2 Mbps Parameter Description Min T yp Max Unit Sensitivity @30.8% PER — — –93 — dBm Maximum received signal @30.8% PER — — 3 — dBm Co-channel C/I — — 10 — dB Adjacent channel selectivity C/I F = F0 + 2 MHz — –7 — dB F = F0 – 2 MHz — –7 — dB F = F0 + 4 MHz — –28 — dB F = F0 – 4 MHz — –26 — dB F = F0 + 6 MHz — –26 — dB F = F0 – 6 MHz — –27 — dB F ≥ F0 + 8 MHz — –29 — dB F ≤ F0 – 8 MHz — –28 — dB Image frequency — — –28 — dB Adjacent channel to image frequency F = Fimage + 2 MHz — –26 — dB F = Fimage – 2 MHz — –7 — dB Out-of-band blocking performance

2003 MHz~ 2399 MHz — –19 — dBm

2484 MHz~ 2997 MHz — –16 — dBm

3000 MHz~ 12.75 GHz — –5 — dBm Intermodulation — — –29 — dBm T able 32: Receiver Characteristics Bluetooth LE 125 Kbps Parameter Description Min T yp Max Unit Sensitivity @30.8% PER — — –105 — dBm Maximum received signal @30.8% PER — — 5 — dBm Co-channel C/I — — 3 — dB Adjacent channel selectivity C/I F = F0 + 1 MHz — –6 — dB F = F0 – 1 MHz — –6 — dB F = F0 + 2 MHz — –33 — dB F = F0 – 2 MHz — –43 — dB F = F0 + 3 MHz — –37 — dB F = F0 – 3 MHz — –47 — dB F ≥ F0 + 4 MHz — –40 — dB F ≤ F0 – 4 MHz — –50 — dB Cont’d on next page Espressif Systems 38 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

T able 32 – cont’d from previous page Parameter Description Min T yp Max Unit Image frequency — — –40 — dB Adjacent channel to image frequency F = Fimage + 1 MHz — –50 — dB F = Fimage – 1 MHz — –37 — dB T able 33: Receiver Characteristics Bluetooth LE 500 Kbps Parameter Description Min T yp Max Unit Sensitivity @30.8% PER — — –100 — dBm Maximum received signal @30.8% PER — — 5 — dBm Co-channel C/I — — 3 — dB Adjacent channel selectivity C/I F = F0 + 1 MHz — –2 — dB F = F0 – 1 MHz — –3 — dB F = F0 + 2 MHz — –32 — dB F = F0 – 2 MHz — –33 — dB F = F0 + 3 MHz — –23 — dB F = F0 – 3 MHz — –40 — dB F ≥ F0 + 4 MHz — –34 — dB F ≤ F0 – 4 MHz — –44 — dB Image frequency — — –34 — dB Adjacent channel to image frequency F = Fimage + 1 MHz — –46 — dB F = Fimage – 1 MHz — –23 — dB Espressif Systems 39 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

5 Package Information

Package Information Figure 8: QFN32 (5×5 mm) Package Note:

For the source file ofrecommendedPCB land pattern (dxf), you can view it withAutodesk Viewer;
For information about tape, reel, and product marking, please refer toEspressif Chip-Packing Information. Espressif Systems 40 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

6 Related Documentation and Resources

Related Documentation and Resources Related Documentation

ESP32-C3TechnicalReferenceManual–DetailedinformationonhowtousetheESP32-C3memoryandperipherals.
Certificates http://espressif.com/en/support/documents/certificates
Documentation Updates and Update Notification Subscription http://espressif.com/en/support/download/documents Developer Zone
ESP-IDF ProgrammingGuide for ESP32-C3 – Extensive documentation for the ESP-IDF development framework.
ESP-IDF and other development frameworks on GitHub. http://github.com/espressif
ESP32 BBS Forum– Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions, share knowledge, explore ideas, and help solve problems with fellow engineers. http://esp32.com/
The ESP Journal– Best Practices, Articles, and Notes from Espressif folks. http://blog.espressif.com/
See the tabsSDKs and Demos, Apps, Tools, AT Firmware. http://espressif.com/en/support/download/sdks-demos Products
ESP32-C3 Series SoCs– Browse through all ESP32-C3 SoCs. http://espressif.com/en/products/socs?id=ESP32-C3
ESP32-C3 Series Modules– Browse through all ESP32-C3-based modules. http://espressif.com/en/products/modules?id=ESP32-C3
ESP32-C3 Series DevKits– Browse through all ESP32-C3-based devkits. http://espressif.com/en/products/devkits?id=ESP32-C3
ESP Product Selector– Find an Espressif hardware product suitable for your needs by comparing or applying filters. http://products.espressif.com/#/product-selector?language=en Contact Us
See the tabsSales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples (Online stores),Become Our Supplier, Comments & Suggestions. http://espressif.com/en/contact-us/sales-questions Espressif Systems 41 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

Revision History

Date Version Release Notes 2021-10-26 v1.1

Updated FigureBlock Diagram of ESP32-C3to show power modes;
Added CoreMark score in Features;
Updated TablePin Descriptionto show default pin functions;
Updated FigureESP32-C3 Power Schemeand related descriptions;
Added TableMapping of SPI Signals and Chip Pads;
Added note 3 to TableRecommended Operating Conditions;
Other updates to wording. 2021-05-28 v1.0
Updated power modes;
Updated Section2.4 Strapping Pins;
UpdatedsomeclocknamesandtheirfrequenciesinSection 3.2System Clocks;
Added clarification about ADC1 and ADC2 in Section3.3.1 Analog-to- Digital Converter (ADC);
Updated the default configuration of U0RXD andU0TXD after reset in TableIO MUX Pin Functions;
Updated sampling rate in TableADC Characteristics;
Updated TableReliability Qualifications;
AddedthelinktorecommendedPCBlandpatterninChapter 5Package Information. 2021-04-23 v0.8 Updated Wi-Fi Radioand Bluetooth LE Radiodata. 2021-04-07 v0.7
Updated information aboutUSB Serial/JTAG Controller;
Added GPIO2 to Section2.4 Strapping Pins;
Updated FigureAddress Mapping Structure;
AddedTable IO MUX Pin FunctionsandTable Power-Up Glitches on Pins in Section3.4.1 General Purpose Input / Output Interface (GPIO);
Updated information about SPI2 in Section3.4.2 Serial Peripheral Inter- face (SPI);
Updated fixed-priority channel scheme in Section3.4.8 General DMA Controller;
Updated TableReliability Qualifications. 2021-01-18 v0.6
Clarified that of the 400 KB SRAM, 16 KB is configured as cache;
UpdatedmaximumvaluetostandardlimitvalueinTable TX EVM Testin Section 4.8.1 Wi-Fi RF Transmitter (TX) Specifications. Espressif Systems 42 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

Date Version Release Notes 2021-01-13 v0.5

Updated information about Wi-Fi;
Added connection between embedded flash ports and chip pins to ta- ble notes in Section2.2 Pin Description;
Updated Figure ESP32-C3 Power Scheme, added FigureESP32-C3 Power-up and Reset Timingand TableDescription of ESP32-C3 Power- up and Reset Timing Parametersin Section2.3 Power Scheme;
Added FigureSetup and Hold Times for the Strapping Pinsand Table Parameter Descriptions of Setup and Hold Times for the Strapping Pinsin Section 2.4 Strapping Pins;
Updated TablePeripheral Pin Configurationsin Section3.11 Peripheral Pin Configurations;
Added Chapter4 Electrical Characteristics;
Added Chapter5 Package Information. 2020-11-27 v0.4 Preliminary version. Espressif Systems 43 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.1

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