DS1302 SYC | Alldatasheet
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Trickle-Charge Timekeeping Chip 1 of 13 REV: 120208
FEATURES
Real-Time Clock Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the Week, and Year with Leap-Year Compensation Valid Up to 2100 31 x 8 Battery-Backed General-Purpose RAM Serial I/O for Minimum Pin Count 2.0V to 5.5V Full Operation Uses Less than 300nA at 2.0V Single-Byte or Multiple-Byte (Burst Mode) Data Transfer for Read or Write of Clock or RAM Data 8-Pin DIP or Optional 8-Pin SO for Surface Mount Simple 3-Wire Interface TTL-Compatible (VCC = 5V) Optional Industrial Temperature Range: -40°C to +85°C DS1202 Compatible Underwriters Laboratories (UL®) Recognized PIN CONFIGURATIONS
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE TOP MARK* DS1302+ 0°C to +70°C 8 PDIP (300 mils) DS1302 DS1302N+ -40°C to +85°C 8 PDIP (300 mils) DS1302 DS1302S+ 0°C to +70°C 8 SO (208 mils) DS1302S DS1302SN+ -40°C to +85°C 8 SO (208 mils) DS1302S DS1302Z+ 0°C to +70°C 8 SO (150 mils) DS1302Z DS1302ZN+ -40°C to +85°C 8 SO (150 mils) DS1302ZN +Denotes a lead-free/RoHS-compliant package. *An N anywhere on the top mark indicates an industrial temperature grade device. A + anywhere on the top mark indicates a lead- free device. UL is a registered trademark of Underwriters Laboratories, Inc. VCC1 SCLK I/O CE VCC2 GND DIP (300 mils) DS1302 VCC2 GND VCC1 SCLK I/O CE SO (208 mils/150 mils) DS1302 TOP VIEW
DS1302 Trickle-Charge Timekeeping Chip 2 of 13 DETAILED DESCRIPTION The DS1302 trickle-charge timekeeping chip contains a real-time clock/cale ndar and 31 bytes of static RAM. It communicates with a microprocessor via a simple serial inte rface. The real-time clock/ca lendar provides seconds, minutes, hours, day, date, month, and y ear information. The end of the mont h date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. Interfacing the DS1302 with a microprocessor is simplifi ed by using synchronous serial communication. Only three wires are required to communicate with the clock/RAM: CE, I/O (data line), and SCLK (serial clock). Data can be transferred to and from the clock/RAM 1 byte at a time or in a burst of up to 31 bytes. The DS1302 is designed to operate on very low power and retain data and clock information on less than 1μW. The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the DS1202, the DS1302 has the additional features of dual power pins for primary and backup power supplies, programmable trickle charger for VCC1, and seven additional bytes of scratchpad memory. OPERATION Figure 1 shows the main elements of the serial timekeeper: shi ft register, control logic, oscillator, real-time clock, and RAM. TYPICAL OPERATING CIRCUIT DS1302 CPU VCC V CC2 SCLK CE GND X2 X1 VCC I/O V CC1
Figure 1. Block Diagram
31 X 8 RAM
DS1302 Trickle-Charge Timekeeping Chip 4 of 13 PIN DESCRIPTION PIN NAME FUNCTION
1 VCC2
Primary Power-Supply Pin in Dual Supply Configuration. VCC1 is connected to a backup source to maintain the time and date in the absence of primary power. The DS1302 operates from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 + 0.2V, VCC2 powers the DS1302. When VCC2 is less than VCC1, VCC1 powers the DS1302. 2 X1 3 X2 Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pF. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. The DS1302 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
4 GND Ground
Input. CE signal must be asserted high during a read or a write. This pin has an internal 40kΩ (typ) pulldown resistor to ground. Note: Previous data sheet revisions referred to CE as RST. The functionality of the pin has not changed. 6 I/O Input/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wire interface. This pin has an internal 40kΩ (typ) pulldown resistor to ground. 7 SCLK Input. SCLK is used to synchronize data movement on the serial interface. This pin has an internal 40kΩ (typ) pulldown resistor to ground.
8 VCC1
Low-Power Operation in Single Supply and Battery-Operated Systems and Low- Power Battery Backup. In systems using the trickle charger, the rechargeable energy source is connected to this pin. UL recognized to ensure against reverse charging current when used with a lithium battery. Go to www.maxim- ic.com/TechSupport/QA/ntrl.htm.
DS1302 Trickle-Charge Timekeeping Chip 6 of 13 CE AND CLOCK CONTROL Driving the CE input high initiates all data transfers. T he CE input serves two functions. First, CE turns on the control logic that allows access to the shift register for the address/command sequence. Second, the CE signal provides a method of terminating either single-byte or multiple-byte CE data transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on t he falling edge of clock. If the CE input is low, all data transfer terminates and the I/O pin goes to a high-impedance state. Figure 4 shows data transfer. At power-up, CE must be a logic 0 until VCC > 2.0V. Also, SCLK must be at a logic 0 when CE is driven to a logic 1 state. DATA INPUT Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0. DATA OUTPUT Following the eight SCLK cycles that in put a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be tr ansmitted occurs on the first falling edge after the last bit of the command byte is written. Additi onal SCLK cycles retransmit the data bytes should they inadvertently occur so long as CE remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tri- stated upon each rising edge of SCLK. Data is output starting with bit 0. BURST MODE Burst mode can be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0. When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not. CLOCK/CALENDAR The time and calendar information is obtained by reading the appropriate register bytes. Table 3 illustrates the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, seco ndary (user) buffers are used to prevent errors when the internal registers update. When reading the time and dat e registers, the user buffers are synchronized to the internal registers the rising edge of CE. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the falling edge of CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second. The DS1302 can be run in either 12-hour or 24-hour mode. Bit 7 of the hours register is defined as the 12- or 24- hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours ). The hours data must be re-initialized whenever the 12/24 bit is changed.
this bit is written to logic 0, the clock will start. The initial power-on state is not defined. should be cleared before attempting to write to the device. resistor and diodes are selected by the RS and DS bits as shown in Table 2. Table 2. Trickle Charger Resistor and Diode Select super cap charging. The maximum charging current can be calculated as illustrated in the following example.
registers can be consecutively read or written (see Table 3) starting with bit 0 of address 0. re-read the registers in case of an update of the main registers during a read. The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space. read or written (see Table 3) starting with bit 0 of address 0. A register data format summary is shown in Table 3. layout consideration, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. Figure 4. Data Transfer Summary NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST.
Table 3. Register Address/Definition Figure 5. Programmable Trickle Charger
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DS1302 Trickle-Charge Timekeeping Chip 10 of 13 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC1, VCC2 VCC1, VCC2 (Notes 2, 10) 2.0 3.3 5.5 V Logic 1 Input VIH (Note 2) 2.0 VCC + 0.3 V VCC = 2.0V -0.3 +0.3 Logic 0 Input VIL VCC = 5V (Note 2) -0.3 +0.8 V DC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage ILI (Notes 5, 13) 85 500 μA I/O Leakage ILO (Notes 5, 13) 85 500 μA Logic 1 Output (IOH = -0.4mA) VCC = 2.0V 1.6 Logic 1 Output (IOH = -1.0mA) VOH VCC = 5V (Note 2) 2.4 V Logic 0 Output (IOL = 1.5mA) VCC = 2.0V 0.4 Logic 0 Output (IOL = 4.0mA) VOL VCC = 5V (Note 2) 0.4 V VCC1 = 2.0V 0.4 Active Supply Current (Oscillator Enabled) ICC1A VCC1 = 5V CH = 0 (Notes 4, 11) 1.2 mA VCC1 = 2.0V 0.2 0.3 Timekeeping Current (Oscillator Enabled) ICC1T VCC1 = 5V CH = 0 (Notes 3, 11,13) 0.45 1 μA VCC1 = 2.0V 1 100 VCC1 = 5V 1 100 Standby Current (Oscillator Disabled) ICC1S IND CH = 1 (Notes 9, 11, 13) 5 200 nA VCC2 = 2.0V 0.425 Active Supply Current (Oscillator Enabled) ICC2A VCC2 = 5V CH = 0 (Notes 4, 12) 1.28 mA VCC2 = 2.0V 25.3 Timekeeping Current (Oscillator Enabled) ICC2T VCC2 = 5V CH = 0 (Notes 3, 12) 81 μA VCC2 = 2.0V CH = 1 (Notes 9, 12) 25 Standby Current (Oscillator Disabled) ICC2S VCC2 = 5V 80 μA R1 2 R2 4 Trickle-Charge Resistors R3 8 kΩ Trickle-Charge Diode Voltage Drop VTD 0.7 V
DS1302 Trickle-Charge Timekeeping Chip 11 of 13 CAPACITANCE (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS Input Capacitance CI 10 pF I/O Capacitance CI/O 15 pF AC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC = 2.0V 200 Data to CLK Setup tDC VCC = 5V (Note 6) 50 ns VCC = 2.0V 280 CLK to Data Hold tCDH VCC = 5V (Note 6) 70 ns VCC = 2.0V 800 CLK to Data Delay tCDD VCC = 5V (Notes 6, 7, 8) 200 ns VCC = 2.0V 1000 CLK Low Time tCL VCC = 5V (Note 6) 250 ns VCC = 2.0V 1000 CLK High Time tCH VCC = 5V (Note 6) 250 ns VCC = 2.0V 0.5 CLK Frequency tCLK VCC = 5V (Note 6) DC 2.0 MHz VCC = 2.0V 2000 CLK Rise and Fall tR, tF VCC = 5V 500 ns VCC = 2.0V 4 CE to CLK Setup tCC VCC = 5V (Note 6) 1 μs VCC = 2.0V 240 CLK to CE Hold tCCH VCC = 5V (Note 6) 60 ns VCC = 2.0V 4 CE Inactive Time tCWH VCC = 5V (Note 6) 1 μs VCC = 2.0V 280 CE to I/O High Impedance tCDZ VCC = 5V (Note 6) 70 ns VCC = 2.0V 280 SCLK to I/O High Impedance tCCZ VCC = 5V (Note 6) 70 ns Note 1: Limits at -40°C are guaranteed by design and are not production tested. Note 2: All voltages are referenced to ground. Note 3: ICC1T and ICC2T are specified with I/O open, CE and SCLK set to a logic 0. Note 4: ICC1A and ICC2A are specified with the I/O pin open, CE high, SCLK = 2MHz at VCC = 5V; SCLK = 500kHz, VCC = 2.0V. Note 5: CE, SCLK, and I/O all have 40kΩ pulldown resistors to ground. Note 6: Measured at VIH = 2.0V or VIL = 0.8V and 10ns maximum rise and fall time. Note 7: Measured at VOH = 2.4V or VOL = 0.4V. Note 8: Load capacitance = 50pF. Note 9: ICC1S and ICC2S are specified with CE, I/O, and SCLK open. Note 10: VCC = VCC2, when VCC2 > VCC1 + 0.2V; VCC = VCC1, when VCC1 > VCC2. Note 11: VCC2 = 0V. Note 12: VCC1 = 0V. Note 13: Typical values are at +25°C.
Figure 6. Timing Diagram: Read Data Transfer Figure 7. Timing Diagram: Write Data Transfer
8 DIP 110 40
8 SO (150 mils) 170 40
DS1302 Trickle-Charge Timekeeping Chip 13 of 13
REVISION HISTORY
Removed the leaded parts and references to the 16-pin SO package. 1, 4, 12 In the Features section, changed the 31 x 8 RAM feature to indicate that it is battery backed. 1 Updated Figure 1 and removed original Figure 2 (oscillator circuit). 3, 5 Added a new Table 2 for the trickle charger resistor and diode select. 7 Replaced the timing diagrams (Figures 6 and 7). 12 120208 Added Package Information table. 12