74LS195 SYC | Alldatasheet

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/C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0057/C0053/C0065 /C0085/C0110/C0105/C0118/C0101/C0114/C0115/C0097/C0108 /C0052/C0045/C0066/C0105/C0116 /C0083/C0104/C0105/C0102/C0116 /C0082/C0101/C0103/C0105/C0115/C0116/C0101/C0114 The SN74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products.

  • Typical Shift Right Frequency of 39 MHz
  • Asynchronous Master Reset
  • J, K Inputs to First Stage
  • Fully Synchronous Serial or Parallel Data Transfers
  • Input Clamp Diodes Limit High Speed Termination Effects GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 4.75 5.0 5.25 V TA Operating Ambient Temperature Range 0 25 70 °C IOH Output Current – High –0.4 mA IOL Output Current – Low 8.0 mA LOW POWER SCHOTTKY Device Package SN74LS195AN 16 Pin DIP SN74LS195AD 16 Pin SOIC D SUFFIX CASE 751B PLASTIC N SUFFIX CASE 648 74LS195

CONNECTION DIAGRAM DIP (TOP VIEW) Parallel Enable (Active LOW) Input Parallel Data Inputs First Stage J (Active HIGH) Input First Stage K (Active LOW) Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs Complementary Last Stage Output PE P0 – P3 J K CP MR Q0 – Q3 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 /C0109A HIGH/1.6 mA LOW. HIGH LOW (Note a)LOADING PIN NAMES LOGIC SYMBOL 456 7 121314151 J PE CP K MR P0 P1 P2 P3 Q0 Q1 Q2 Q3 VCC = PIN 16 GND = PIN 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 14 13 12 11 10 9 12345 6 7 16 15 VCC MR Q0 Q1 Q2 Q3 CPQ3 PE JK P0 P1 P2 P3 GND www.sycelectronica.com.ar

R CP S CD Q2 Q3 126 7 3 4 59 1112 1315VCC = PIN 16 GND = PIN 8 = PIN NUMBERS R CP S CD R CP S CD Q3R CP S CD FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional characteristics of the LS195A 4-Bit Shift Register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The LS195A has two primary modes of operation, shift right (Q 0 /C0179 Q1) and parallel load which are controlled by the state of the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the first flip-flop Q0 via the J and K inputs and is shifted one bit in the direction Q0 /C0179 Q1 /C0179 Q 2 /C0179Q 3 following each LOW to HIGH clock transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple D type input for general applications by tying the two pins together. When the PE input is LOW, the LS195A appears as four common clocked D flip-flops. The data on the parallel inputs P 0, P1, P2, P3 is transferred to the respective Q0, Q1, Q2, Q3 outputs following the LOW to HIGH clock transition. Shift left operations (Q 3 /C0179Q 2) can be achieved by tying the Qn Outputs to the Pn–1 inputs and holding the PE input LOW. All serial and parallel data transfers are synchronous, occurring after each LOW to HIGH clock transition. Since the LS195A utilizes edge-triggering, there is no restriction on the activity of the J, K , Pn and PE inputs for logic operation — except for the set-up and release time requirements. A LOW on the asynchronous Master Reset (MR ) input sets all Q outputs LOW, independent of any other input condition. MODE SELECT — TRUTH TABLE OPERATING MODES INPUTS OUTPUTS OPERATING MODES MR PE J K Pn Q 0 Q 1 Q 2 Q 3 Q 3 Asynchronous Reset L X X X X L L L L H Shift, Set First Stage H h h h X H q0 q1 q2 q2 Shift, Reset First H h I I X L q0 q1 q2 q2 Shift, Toggle First StageH h h I X q0 q0 q1 q2 q2 Shift, Retain First StageH h I h X q0 q0 q1 q2 q2 Parallel Load H I X X pn p0 p1 p2 p3 p3 L = LOW voltage levels H = HIGH voltage levels X = Don’t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition. h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition. p n (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition. www.sycelectronica.com.ar

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VO Output LOW Voltage 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, VIN =V ILor VIHVOL O utput LOW Voltage 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table I Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V IIH Input HIGH C urrent 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX ICC Power Supply Current 21 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions fMAX Maximum Clock Frequency 30 39 MHz tPLH tPHL Propagation Delay, Clock to Output ns VCC = 5.0 V C L = 15 pF tPHL Propagation Delay, MR to Output 19 30 ns C L 15 F AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions tW CP Clock Pulse Width 16 ns tW MR Pulse Width 12 ns ts PE Setup Time 25 ns ts Data Setup Time 15 ns VCC = 5.0 V trec Recovery Time 25 ns trel PE Release Time 10 ns th Data Hold Time 0 ns www.sycelectronica.com.ar

CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– B F C S H G D J L M 16 PL SEATING 916 K PLANE–T– MAM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01 /C0095/C0095/C0095/C0095 www.sycelectronica.com.ar

CASE 751B–05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 16 9 SEATING PLANE F JM R X 45/C0095 G

8 PLP–B–

–A– M0.25 (0.010) B S –T– D K C 16 PL SBM0.25 (0.010) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 www.sycelectronica.com.ar