74LS377 SYC | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 6

Technical content

/C0083/C0078/C0055/C0052/C0076/C0083/C0051/C0055/C0055 /C0079/C0099/C0116/C0097/C0108 /C0068 /C0070/C0108/C0105/C0112/C0045/C0070/C0108/C0111/C0112 /C0119/C0105/C0116/C0104 /C0069/C0110/C0097/C0098/C0108/C0101 The SN74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable.

  • 8-Bit High Speed Parallel Registers
  • Positive Edge-Triggered D-Type Flip Flops
  • Fully Buffered Common Clock and Enable Inputs
  • True and Complement Outputs
  • Input Clamp Diodes Limit High Speed Termination Effects GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 4.75 5.0 5.25 V TA Operating Ambient Temperature Range 0 25 70 °C IOH Output Current – High –0.4 mA IOL Output Current – Low 8.0 mA LOW POWER SCHOTTKY Device Package

ORDERING INFORMATION

www.sycelectronica.com.ar

CONNECTION DIAGRAM DIP (TOP VIEW) Enable (Active LOW) Input Data Inputs Clock (Active HIGH Going Edge) Input True Outputs Complemented Outputs E D0 – D3 CP Q0 – Q3 Q0 – Q3 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 /C0109A HIGH/1.6 mA LOW. HIGH LOW (Note a)LOADING PIN NAMES NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 18 17 16 15 14 13 1234 56 7 20 19 VCC E Q7 D7 D6 Q6 D5Q5 D4 Q0 D0 D1 Q1 Q2 D2 D3 91 0 Q3 GND 12 11 Q4 CP LOGIC DIAGRAM E ENABLE D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP CLOCK CP D Q 73 84 5 9 12 16 13 17 CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q 15 19 www.sycelectronica.com.ar

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VO Output LOW Voltage 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, V V or VVOL O utput LOW Voltage 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table I Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V IIH Input HIGH C urrent 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1)–20 –100 mA VCC = MAX ICC Power Supply Current 28 mA VCC = MAX, NOTE 1 NOTE: With all inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock. Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions fMAX Maximum Clock Frequency 30 40 MHz VCC =50V tPLH tPHL Propagation Delay, Clock to Output ns VCC = 5.0 V C L = 15 pF AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions tW Any Pulse Width 20 ns ts Data Setup Time 20 ns t Enable Setup Inactive — State 10 ns VCC = 5.0 V ts Time Active — State 25 ns th Any Hold Time 5.0 ns DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (t h) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. www.sycelectronica.com.ar

CASE 738–03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. M L J 20 PL MBM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 25.66 27.171.010 1.070 B 6.10 6.600.240 0.260 C 3.81 4.570.150 0.180 D 0.39 0.550.015 0.022 G 2.54 BSC0.100 BSC J 0.21 0.380.008 0.015 K 2.80 3.550.110 0.140 L 7.62 BSC0.300 BSC M 0 15 0 15 N 0.51 1.010.020 0.040 /C0095/C0095/C0095/C0095 E 1.27 1.770.050 0.070 –A– SEATING PLANE K N FG D 20 PL –T– MAM0.25 (0.010) T E B C F 1.27 BSC0.050 BSC www.sycelectronica.com.ar

CASE 751D–05 ISSUE F B20X H10X C L 18X A1 A SEATING PLANE /C0113 h X 45/C0095 E D M0.25 MB M0.25 SA SBT e T B A DIM MIN MAX MILLIMETERS A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 /C0113 0 7 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION./C0095/C0095 www.sycelectronica.com.ar