DFE201210U-1R0MP2

RS9116 SILABS | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 82

Technical content

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 1 | Page RS9116 n-Link™ and WiSeConnect™ Wi-Fi® and Dual-Mode Bluetooth® 5 Wireless Connectivity B00 Module Solution Overview

1.1 Features

• Compliant to single-spatial stream IEEE 802.11 b/g/n with single band support
• Support for 20 MHz channel bandwidth
• Transmit power up to +18 dBm with integrated PA
• Receive sensitivity as low as -96 dBm
• Data Rates: 802.11b: Up to 11 Mbps; 802.11g: Up to 54 Mbps; 802.11n: MCS0 to MCS7
• Operating Frequency Range: 2412 MHz – 2484 MHz Bluetooth
• Transmit power up to +16 dBm with integrated PA
• Receive sensitivity:- LE: -92 dBm, LR 125 Kbps: - 102 dBm
• Compliant to dual-mode Bluetooth 5
• <8 mA transmit current in Bluetooth 5 mode, 2 Mbps data rate
• Data rates: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps,

3 Mbps

• Operating Frequency Range: 2.402 GHz - 2.480 GHz
• Bluetooth 2.1 + EDR, Bluetooth Low Energy 4.0 / 4.1 / 4.2 / 5.0
• Bluetooth Low Energy 1 Mbps, 2 Mbps and Long Range modes
• Bluetooth Low Energy Secure connections
• Bluetooth Low Energy supports central role and peripheral role concurrently
• Bluetooth auto rate and auto TX power adaptation
• Scatternet* with two secondary roles while still being visible RF Features
• Integrated baseband processor with calibration memory, RF transceiver, high-power amplifier, balun and T/R switch Power Consumption
• Wi-Fi Standby Associated mode current: 55 uA @ 1 second beacon listen interval
• Wi-Fi 1 Mbps Listen current: 14 mA
• Wi-Fi LP chain Rx current: 19 mA
• Deep sleep current <1 uA, Standby current (RAM retention) < 10 uA Operating Conditions
• Wide operating supply range: 1.75 V to 3.63 V
• Operating temperature: -40 ºC to +85 ºC (Industrial grade) Size
• Small Form Factor: 7.90 x 4.63 x 0.9 mm Evaluation Kit
• Single Band EVK: RS9116X-SB-EVK2 Software Operating Modes
• Hosted mode (n-Link™): Wi-Fi stack, Bluetooth stack and profiles and all network stacks reside on the host processor
• Embedded mode (WiSeConnect™): Wi-Fi stack, TCP/IP stack, IP modules, Bluetooth stack and some profiles reside in RS9116; Some of the Bluetooth profiles reside in the host processor Hosted Mode (n-Link™)
• Available host interfaces: SDIO 2.0 and USB HS
• Application data throughput up to 50 Mbps (Hosted Mode) in 802.11n with 20MHz bandwidth.
• Host drivers for Linux
• Support for Client mode, Access point mode (Up to 16 clients), Concurrent Client and Access Point mode, Enterprise Security
• Support for concurrent Wi-Fi, dual-mode Bluetooth 5 Embedded Mode (WiSeConnect™)
• Available host interface: UART, SPI, and USB CDC
• Support for Embedded Client mode, Access Point mode (Up to 8 clients), Concurrent Client and Access Point mode, and Enterprise Security
• Supports advanced security features: WPA/WPA2- Personal and Enterprise

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 2 | Page

• Integrated TCP/IP stack, HTTP/HTTPS, SSL/TLS, MQTT
• Bluetooth inbuilt stack support for L2CAP, RFCOMM, SDP, SPP, GAP
• Bluetooth profile support for GAP, SDP, SPP, GATT, L2CAP, RFCOMM
• Wireless firmware update and provisioning
• Support for concurrent Wi-Fi, dual-mode Bluetooth 5 Security
• Accelerators: AES128/256 in Embedded Mode
• WPA/WPA2-Personal, WPA/WPA2 Enterprise for Client Software and Regulatory Certification
• Wi-Fi Alliance*
• Bluetooth Qualification*
• Regulatory certifications (FCC, IC, CE/ETSI, TELEC, UKCA)* * For a detailed list of software features and available profiles, refer to the Software Reference Manuals or contact Silicon Labs for availability. All power and performance numbers are under ideal conditions.

1.2 Applications

Smart Watches, Wristbands, Fitness Monitors, Smart Glasses, etc. Smart Home Smart Locks, Motion/Entrance Sensors, Water Leak sensors, Smart plugs/switches, LED lights, Door-bell cameras, Washers/Dryers, Refrigerators, Thermostats, Consumer Security cameras, Voice Assistants, etc. Other Consumer Applications Toys, Anti-theft tags, Smart dispensers, Weighing scales, Blood pressure monitors, Blood sugar monitors, Portable cameras, etc. Other Applications (Medical, Industrial, Retail, Agricultural, Smart City, etc.) Healthcare Tags, Medical patches/pills, Infusion pumps, Sensors/actuators in Manufacturing, Electronic Shelf labels, Agricultural sensors, Product tracking tags, Smart Meters, Parking sensors, Street LED lighting, Automotive After- market, Security Cameras, etc.

1.3 Description

Silicon Labs' RS9116 single band B00 module provides a comprehensive multi-protocol wireless connectivity solution including 802.11 b/g/n (2.4 GHz), 802.11j, dual-mode Bluetooth 5. The modules offer high throughput, extended range with power-optimized performance. The modules are FCC, IC, ETSI/CE (including EN 300 328 v2.2.2), TELEC, and UKCA certified.

1.4 Block Diagrams

Figure 1. B00 Module Block Diagram with Internal Flash Figure 2. RS9116 Connectivity Hardware Block Diagram

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 5 | Page Table of Contents

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 6 | Page

2 RS9116 B00 Module Pinout and Pin Description

2.1 Pin Diagram

Figure 5. RS9116 B00 Pin Diagram

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 8 | Page

2.2 Pin Description

2.2.1 RF & Control Interfaces

Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset)

Description

RF_PORT1 A18 NA Inout NA Connect to Antenna with a 50 Ω impedance as per the Reference Schematics. RESET_N J1 UULP_VBATT_1 Input NA Active-low reset asynchronous reset signal. POC_OUT G5 UULP_VBATT_1 Ouput NA Power On Control Output. POC_IN G3 UULP_VBATT_1 Input NA Power On Control Input. Table 1. RF & Control Interfaces

2.2.2 Power & Ground Pins

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 9 | Page Pin Name Type Pin Number Direction Description IO_VDD_1 Power G9 Input I/O Supply for GPIOs.Refer to the GPIOs section for details on which GPIOs have this as the I/O supply. IO_VDD_2 Power J15, K5 Input I/O Supply for GPIOs. Refer to the GPIOs section for details on which GPIOs have this as the I/O supply. IO_VDD_3 Power D10 Input I/O Supply for GPIOs. Refer to the GPIOs section for details on which GPIOs have this as the I/O supply. SDIO_IO_VDD Power B14 Input I/O Supply for SDIO I/Os. Refer to the GPIOs section for details on which GPIOs have this as the I/O supply. ULP_IO_VDD Power B7 Input I/O Supply for ULP GPIOs PA2G_AVDD Power H16 Input Power supply for the 2.4 GHz RF Power Amplifier RF_AVDD Power H14, L12 Input Power supply for the 2.4 GHz RF and AFE.Connect to VOUTBCKDC as per the Reference Schematics RF_AVDD_BTTX Power J18 Input Power supply for Bluetooth Transmit circuit.Connect to VOUTLDOAFE as per the Reference Schematics. AVDD_1P3 Power K14 Input Power supply for the 2.4 GHz RF.Connect to VOUTBCKDC as per the Reference Schematics. UULP_VOUTSCDC Power D2 Output UULP Switched Cap DCDC Output UULP_VOUTSCDC_RE TN Power B1 Output UULP Retention Supply Output UULP_AVDD Power C1 Input Power supply for the always-on digital and ULP peripherals.Connect to UULP_VOUTSCDC as per the Reference Schematics. C_VDD Power E9, J5, K8 Input Power supply for the digital core .Connect to the VOUTLDOSOC as per the Reference Schematics. USB_AVDD_3P3 Power A10 Input Power Supply for the USB interface USB_AVDD_1P1 Power C9 Input Power supply for the USB core GND Ground A16, B6, B15, B16, B17, B18, C7, C15, C17, C18, D4, D16, E5, E15, E17, E18, F2, F8, G1, G7, G18, H12, H17, J11, GND Common ground pins

Table 2. Power and Ground Pins

2.2.3 Host & Peripheral Interfaces

• I2S_DOUT - I2S interface output data.
• PCM_DOUT - PCM interface output data. GPIO_7 D17 IO_VDD_1 Inout HighZ Default : HighZ Sleep: HighZ This pin can be configured by software to be any of the following
• I2S_CLK - I2S interface clock.
• PCM_CLK - PCM interface clock. GPIO_8/UART1_RX G15 IO_VDD_1 Inout HighZ Host Default Sleep UART UART1_RX - UART Host interface serial input. HighZ Non UART HighZ HighZ The UART interface is supported only in WiSeConnect™.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 11 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 GPIO_9/UART1_TX F17 IO_VDD_1 Inout HighZ Host Default Sleep UART UART1_TX - UART Host interface serial output. HighZ Non UART HighZ HighZ The UART interface is supported only in WiSeConnect™. GPIO_10 F14 IO_VDD_1 Inout HighZ Default : HighZ Sleep: HighZ This pin can be configured by software to be any of the following

• I2S_DIN: I2S interface input data.
• PCM_DIN - PCM interface input data. GPIO_11 G17 IO_VDD_3 Inout HighZ Default : HighZ. Sleep: HighZ This pin can be configured by software to be any of the following
• I2S_WS: I2S interface Word Select.
• PCM_FSYNC: PCM interface Frame Synchronization signal. GPIO_12 F16 IO_VDD_1 Inout HighZ Default : HighZ Sleep: HighZ This pin can be configured by software to be any of the following
• UART1_RTS - UART interface Request to Send, if UART Host Interface flow control is enabled.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 12 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 The UART interface is supported only in WiSeConnect™. GPIO_13 L8 IO_VDD_3 Inout HighZ Default : HighZ Sleep: HighZ This pin can be configured by software to be any of the following

• EXT_FLASH_RESET - Reset signal to an external Flash IC, if connected GPIO_15 A12 IO_VDD_1 Inout HighZ Default : HighZ Sleep: HighZ This pin can be configured by software to be any of the following
• UART1_CTS - UART interface Clear to Send, if UART Host Interface flow control is enabled.
• UART1_TRANSPARENT_MODE - UART Host interface Transparent Mode, Indication that module has entered into TRANSPERENT_MODE
• TSF_SYNC - Transmit Synchronization Function signal to indicate to the Host when a packet is transmitted. The signal is toggled once at the end of every transmitted packet. The UART interface is supported only in WiSeConnect™. SDIO_CLK/SPI_CLK D12 SDIO_IO_VDD Inout HighZ Host Default Sleep SDIO SDIO_CLK - SDIO HighZ

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 13 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 interface clock SPI SPI_CLK - SPI Secondary interface clock HighZ Non SDIO,SPI HighZ HighZ The SPI interface is supported only in WiSeConnect™. SDIO_CMD/SPI_CSN B13 SDIO_IO_VDD Inout HighZ Host Default Sleep SDIO SDIO_CMD - SDIO interface CMD signal HighZ SPI SPI_CSN - Active-low Chip Select signal of SPI Secondary interface HighZ Non SDIO,SPI HighZ HighZ The SPI interface is supported only in WiSeConnect™. SDIO_D0/SPI_MOSI C13 SDIO_IO_VDD Inout HighZ Host Default Sleep SDIO SDIO_D0 - SDIO interface Data0 signal HighZ

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 14 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 SPI SPI_MOSI - SPI Secondary interface Main-Out- Secondary-In signal HighZ Non SDIO,SPI HighZ HighZ The SPI interface is supported only in WiSeConnect™. SDIO_D1/SPI_MISO B12 SDIO_IO_VDD Inout HighZ Host Default Sleep SDIO SDIO_D1 - SDIO interface Data1 signal HighZ SPI SPI_MISO - SPI Secondary interface Main-In- Secondary- Out signal HighZ Non SDIO,SPI HighZ HighZ The SPI interface is supported only in WiSeConnect™. SDIO_D2/SPI_INTR B11 SDIO_IO_VDD Inout HighZ Host Default Sleep SDIO SDIO_D2 - SDIO interface Data2 signal HighZ

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 15 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 SPI SPI_INTR - SPI Secondary interface Interrupt Signal to the Host HighZ Non SDIO,SPI HighZ HighZ The SPI interface is supported only in WiSeConnect™. SDIO_D3/SPI_ERR_INT R/USB_CDC_DIS C11 SDIO_IO_VDD Inout Pullup Host Default Sleep SDIO SDIO_D3 - SDIO interface Data3 signal HighZ SPI SPI_ERR_IN TR - SPI Bus Error Interrupt Signals HighZ USB USB_CDC_ DIS - USB- CDC Active- High Disable Signal HighZ Non SDIO, SPI, USB HighZ HighZ The SPI interface is supported only in WiSeConnect™.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 16 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 GPIO_46 L10 IO_VDD_1 Inout HighZ Part Number Default Sleep RS9116W- SB00-B00- ABC HighZ HighZ GPIO_47 K10 IO_VDD_1 Inout HighZ Part Number Default Sleep RS9116W- SB00-B00- ABC HighZ HighZ GPIO_48 H8 IO_VDD_1 Inout HighZ Part Number Default Sleep RS9116W- SB00-B00- ABC HighZ HighZ GPIO_49 J9 IO_VDD_1 Inout HighZ Part Number Default Sleep RS9116W- SB00-B00- ABC HighZ HighZ GPIO_50 K9 IO_VDD_1 Inout HighZ Part Number Default Sleep RS9116W- SB00-B00- ABC HighZ HighZ

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 17 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 GPIO_51 H10 IO_VDD_1 Inout HighZ Part Number Default Sleep RS9116W- SB00-B00- ABC HighZ HighZ GPIO_52 G11 IO_VDD_1 Inout HighZ Default : HighZ Sleep: HighZ GPIO_53 G13 IO_VDD_1 Inout HighZ Default : HighZ Sleep: HighZ GPIO_54 F10 IO_VDD_1 Inout HighZ Default : HighZ Sleep: HighZ GPIO_55 E13 IO_VDD_1 Inout HighZ Default : HighZ Sleep: HighZ GPIO_56 E11 IO_VDD_1 Inout HighZ Default : HighZ Sleep: HighZ GPIO_57 F12 IO_VDD_1 Inout HighZ Default : HighZ Sleep: HighZ ULP_GPIO_0 A2 ULP_IO_VDD Inout HighZ Default : HighZ Sleep: HighZ This pin can be configured by software to be any of the following

• WLAN_ACTIVE*: Active-High signal to indicate to an external Bluetooth IC that WLAN transmission is active. Part of the 3-wire coexistence interface. *This pin is intended to act as WLAN_ACTIVE for wireless coexistence. It is however not available in the current

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 18 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 firmware. Please contact Silicon Labs to learn about availability in the future versions. ULP_GPIO_1 B4 ULP_IO_VDD Inout HighZ Default : HighZ Sleep: HighZ This pin can be configured by software to be any of the following

• BT_ACTIVE*: Active-High signal from an external Bluetooth IC that it is transmitting. Part of the 3-wire coexistence interface. *This pin is intended to act as BT_ACTIVE for Bluetooth coexistence. It is however not available in the current firmware. Please contact Silicon Labs to learn about availability in the future versions. ULP_GPIO_4 L2 ULP_IO_VDD Inout HighZ Default : HighZ ULP_GPIO_5 K3 ULP_IO_VDD Inout HighZ Default : LP_WAKEUP_IN This is LP Powersave Wakeup indication from Device Sleep: HighZ This pin can be configured by software to be any of the following
• LP_WAKEUP_IN : This is LP Powersave Wakeup indication to Device from HOST
• HOST_WAKEUP_INDICATION : This is used as indication from Host to dev that host is ready to take the packet and Device can transfer the packet to host. This is supported only in UART host mode.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 19 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 The UART interface is supported only in WiSeConnect™. ULP_GPIO_6 H4 ULP_IO_VDD Inout HighZ Default : HighZ Sleep: HighZ This pin can be configured by software to be any of the following

• WAKEUP_FROM_Dev* - Used as a wakeup indication to host from device
• BT_PRIORITY**: Active-high signal from an external Bluetooth IC that indicates that the Bluetooth transmissions are a higher priority. *For Wake-on-Wireless, it is recommended to use an external weak pull-down or pull-up resistor. It is recommended to use weak pull-down resistor in new designs. Software has to be configured suitably for using either pull- down or pull-up resistor. **This pin is intended to act as BT_PRIORITY for Bluetooth coexistence. It is however not available in the current firmware. Please contact Silicon Labs to learn about availability in the future versions. ULP_GPIO_7 A1 ULP_IO_VDD Inout HighZ Default : HighZ ULP_GPIO_8 C5 ULP_IO_VDD Inout HighZ Default : HighZ Sleep: HighZ This pin can be configured by software to be any of the following
• LED0: Control signal to an external LED.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 20 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4

• (* LED0 functionality currently not available in WiSeConnect™ modules) ULP_GPIO_9/ UART2_TX E7 ULP_IO_VDD Inout HighZ Default : UART2_TX- Debug UART Interface serial output Sleep: HighZ UART2_TX : Debug UART interface serial output. ULP_GPIO_10 A4 ULP_IO_VDD Inout HighZ Default : HighZ Sleep: HighZ This pin can be configured by software to be any of the following
• I2C_SCL: I2C interface clock. ULP_GPIO_11 J3 ULP_IO_VDD Inout HighZ Default : HighZ Sleep: HighZ This pin can be configured by software to be any of the following
• I2C_SDA: I2C interface data. UULP_VBAT_GPIO_0 J2 UULP_VBATT_1 Output High Default : EXT_PG_EN Sleep: SLEEP_IND_FROM_DEV / EXT_PG_EN This pin can be configured by software to be any of the following
• SLEEP_IND_FROM_DEV: This signal is used to send an indication to the Host processor. An indication is sent when the chip enters (logic low) and exits (logic high) the ULP Sleep mode.
• EXT_PG_EN: Active-high enable signal to an external power gate which can be used to control the power supplies other than Always-ON

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 21 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 VBATT Power Supplies in ULP Sleep mode. UULP_VBAT_GPIO_2/ HOST_BYP_ULP_WAK EUP K2 UULP_VBATT_1 Input HighZ Default : HOST_BYP Sleep: ULP_WAKEUP This signal has two functionalities – one during the bootloading process and one after the bootloading. During bootloading, this signal is an active-high input to indicate that the bootloader should bypass any inputs from the Host processor and continue to load the default firmware from Flash. After bootloading, this signal is an active-high input to indicate that the module should wakeup from its Ultra Low Power (ULP) sleep mode. The bootloader bypass functionality is supported only in WiSeConnect™. UULP_VBAT_GPIO_3 K4 UULP_VBATT_1 Inout HighZ Default : HighZ Sleep: XTAL_32KHZ_IN / SLEEP_IND_FROM_DEV This pin can be configured by software to be any of the following

• XTAL_32KHZ_IN: This pin can be used to feed external clock from a host processor or from external crystal oscillator
• SLEEP_IND_FROM_DEV: This signal is used to send an indication to the Host processor. An indication is sent when the chip enters (logic low) and exits (logic high) the ULP Sleep mode. UULP_VBAT_GPIO_4 E3 UULP_VBATT_1 Inout HighZ Default : HighZ Sleep: HighZ

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 22 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 This pin can be configured by software to be any of the following

• XTAL_32KHZ_IN: This pin can be used to feed external clock from a host processor or from external crystal oscillator JP0 L4 VIN_3P3 Input Pullup Default : JP0 Sleep: HighZ JP0 - Reserved. Connect to a test point for debug purposes. JP1 L6 VIN_3P3 Input Pullup Default : JP1 Sleep: HighZ JP1 - Reserved. Connect to a test point for debug purposes. JP2 K6 VIN_3P3 Input Pullup Default : JP2 Sleep: HighZ JP2 - Reserved. Connect to a test point for debug purposes. JNC K7 VIN_3P3 NC Pullup Default : JNC Sleep: HighZ JNC - Reserved. Connect to a test point for debug purposes. USB_DP B9 USB_AVDD_3P3 Inout NA Positive data channel from the USB connector. USB_DM B10 USB_AVDD_3P3 Inout NA Negative data channel from the USB connector. USB_ID B8 USB_AVDD_3P3 Input NA ID signal from the USB connector.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 23 | Page Pin Name Pin Number I/O Supply Domain Direction Initial State (Power up, Active Reset) Description 1,2,3,4 USB_VBUS D8 USB_AVDD_3P3 Input NA 5V USB VBUS signal from the USB connector. This pin is used just for detecting USB. USB_TXRTUNE A8 USB_AVDD_3P3 Input NA USB Transmitter resistor tune analog signal which needs to be connected to an external 200 Ω resistor to adjusts the USB's high-speed source impedance Table 3. Host and Peripheral Interfaces

1. "Default" state refers to the state of the device after initial boot loading and firmware loading is complete.
2. "Sleep" state refers to the state of the device after entering Sleep state which is indicated by Active-Low "SLEEP_IND_FROM_DEV" signal.
3. Please refer to "RS9116 nLink Technical Reference Manual" for software programming information in hosted mode.
4. Please refer to "RS9116 Wireless SAPI Manual" for software programming information in embedded mode.
5. There are some functionalities, such as SLEEP_IND_FROM_DEV, that are available on multiple pins. However, these pins have other multiplexed functionalities.

Any pin can be used based on the required functionality. Customer has to note the default states before using appropriate pin.

2.2.4 Miscellaneous Pins

NC A14, D6, E1, E2, H2, H6, G2, J7, K1 NA NA NA No connect. Table 4. Miscellaneous Pins

3 RS9116 B00 Module Specifications

3.1 Absolute Maximum Ratings

rating conditions for extended periods may affect device reliability. Table 5. Absolute Maximum Ratings

3.2 Recommended Operating Conditions

Table 6. Recommended Operating Conditions

3.3 DC Characteristics

3.3.1 Reset Pin

Table 7. Reset Pin All numbers are at typical operating conditions unless otherwise stated.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 27 | Page

3.3.2 Power Sequence

The POC_IN and RESET_N signals should be controlled from external sources such as R/C circuits, and/or other MCU's GPIOs. However, POC_OUT can be connected to POC_IN, if the supply voltage is 3.3 V. Below waveforms show power sequence (Up & Down) requirements under various application needs. Note that below waveforms are not to scale. 3.3.2.1 Power-Up and Down Sequence with External 1.4 V Supply and POC_IN The diagram below shows connections of various power supply voltages, POC_IN and RESET_N. These connections can be used when:

• System PMU (outside RS9116) can provide 1.4 V supply, and hence the internal Buck regulator in RS9116 can be disabled.
• The 1.1 V supply is still derived from LDO SoC (internal to RS9116).
• POC_IN is controlled externally. NOTE: 1. Above shown is a typical connection diagram. Some of the supply pins shown above may or may not be present in the IC/Module. Check the Pinout table in this datasheet and connect accordingly. 2. * = Provide the supply voltages as per the specifications mentioned in this datasheet. 3. ** = USB power supply input connection is required if USB interface is present and used. Else, follow the connection as shown in Reference Schematics.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 28 | Page NOTE: 2. Above POC_IN waveform is applicable if it is externally driven. Else, that particular waveform can be ignored, and the RESET_N timing can be considered after/before external power supplies ramp-up/down.

3.3.2.2 Power-Up and Down Sequence with External POC_IN

The diagram below shows connections of various power supply voltages, POC_IN and RESET_N. These connections can be used when:

• System PMU cannot provide 1.4 V or 1.1 V supplies and the internal buck and LDO of RS9116 are used.
• POC_IN is controlled externally. NOTE: 1. Above shown is a typical connection diagram. Check the Reference Schematics for connections of other power supplies.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 29 | Page NOTE:

3.3.2.3 Power-Up and Down Sequence with POC_IN Connected Internally

The diagram below shows connections of various power supply voltages, POC_IN and RESET_N. The typical applications of this connection can be as follows. This connection is Not Recommended for New Design.

• System cannot provide external 1.4 V & 1.1 V supplies and the internal buck and LDO of RS9116 are used.
• POC_IN is looped back from POC_OUT. NOTE: 1. Above shown is a typical connection diagram. Check the Reference Schematics for connections of other power supplies. 2. POC_OUT can be connected to POC_IN if the supply voltage is 3.3V only. Else, POC_IN has to be driven externally. 3. This connection is Not Recommended for New Design, and it is recommended to drive POC_IN externally as shown in the above section. If POC_IN cannot be driven externally, then an RC circuit delay can be provided in between POC_IN and POC_OUT, for delaying the POC_OUT signal reaching POC_IN.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 30 | Page NOTE:

3.3.3 Digital Input Output Signals

Table 8. Digital I/O Signals All numbers are at typical operating conditions unless otherwise stated.

3.3.4 USB

Table 9. USB

3.3.5 Pin Capacitances

Table 10. Pin Capacitances

3.4 AC Characteristics

3.4.1 Clock Specifications

• Low frequency 32 kHz clock for sleep manager and RTC o Internal 32 kHz RC clock is used for applications with low timing accuracy requirements o 32 kHz crystal clock is used for applications with high timing accuracy requirements
• High frequency 40 MHz clock for the ThreadArch® processor, baseband subsystem and the radio o 40 MHz clock is integrated inside the module, and no external clock needs to be provided The chipsets have integrated internal oscillators including crystal oscillators to generate the required clocks. Integrated crystal oscillators enable the use of low-cost passive crystal components. Additionally, in a system where

32 kHz XTAL Oscillator clock is optional. Streaming operation (A2DP Source). applications and can increase system current consumption in duty-cycled power modes.

3.4.1.1.1 RC Oscillator

Table 11. 32 kHz RC Oscillator An external 32 kHz low-frequency clock can be fed through the XTAL_32KHZ_IN functionality. Figure 6. External 32 kHz Oscillator - Rail to Rail

Table 12. 32 kHz External Oscillator Specifications

3.4.2.1 Full Speed Mode

Table 13. AC Characteristics - SDIO 2.0 Secondary Full Speed Mode Figure 7. Interface Timing Diagram for SDIO 2.0 Secondary Full Speed Mode

3.4.2.2 High Speed Mode

Table 14. AC Characteristics - SDIO 2.0 Secondary High Speed Mode

Figure 8. Interface Timing Diagram for SDIO 2.0 Secondary High Speed Mode

3.4.3 SPI Secondary

3.4.3.1 Low Speed Mode

Table 15. AC Characteristics - SPI Secondary Low Speed Mode Figure 9. Interface Timing Diagram for SPI Secondary Low Speed Mode

3.4.3.2 High Speed Mode

Table 16. AC Characteristics - SPI Secondary High Speed Mode Figure 10. Interface Timing Diagram for SPI Secondary High Speed Mode

3.4.3.3 Ultra-High Speed Mode

Table 17. AC Characteristics - SPI Secondary Ultra High Speed Mode Figure 11. Interface Timing Diagram for SPI Secondary Ultra High Speed Mode

3.4.4 USB

3.4.4.1 Low Speed Mode

Table 18. AC Characteristics - USB Low Speed Mode

3.4.4.2 Full Speed Mode

Table 19. AC Characteristics - USB Full Speed Mode

3.4.4.3 High Speed Mode

Table 20. AC Characteristics - USB High Speed Mode

3.4.5 UART

Table 21. AC Characteristics - UART

3.4.6 I2C Main and Secondary

3.4.6.1 Fast Speed Mode

Table 22. AC Characteristics - I2C Fast Speed Mode Figure 12. Interface Timing Diagram for I2C Fast Speed Mode

3.4.6.2 High Speed Mode

Table 23. AC Characteristics - I2C High Speed Mode Figure 13. Interface Timing Diagram for I2C High Speed Mode

3.4.7 I2S/PCM Main and Secondary

3.4.7.1 Main Mode

Table 24. AC Characteristics – I2S/PCM Main Mode Figure 14. Interface Timing Diagram for I2S Main Mode

3.4.7.2 Secondary Mode

Table 25. AC Characteristics - I2S/PCM Secondary Mode

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 39 | Page Figure 15. Interface Timing Diagram for I2S Secondary Mode

3.4.8 GPIO Pins

Conditions Min Typ Max Unit Trf Rise time Pin configured as output; SLEW = 1(fast mode) 1.0 - 2.5 ns Tff Fall time Pin configured as output; SLEW = 1(fast mode) 0.9 - 2.5 ns Trs Rise time Pin configured as output; SLEW = 0(standard mode) 1.9 - 4.3 ns Tfs Fall time Pin configured as output; SLEW = 0(standard mode) 1.9 - 4.0 ns Tr Rise time Pin configured as input 0.3 - 1.3 ns Tf Fall time Pin configured as input 0.2 - 1.2 ns Table 26. AC Characteristics - GPIO Pins

3.5 RF Characteristics

All specifications are subject to change. Contact Silicon Labs for final numbers.

• All numbers are measured at typical operating conditions unless otherwise stated. 3.5.1 WLAN 2.4 GHz Transmitter Characteristics 3.5.1.1 Transmitter characteristics with 3.3 V Supply
• TA = 25 °C, PA2G_AVDD/VINBCKDC = 3.3 V. Remaining supplies are at typical operating conditions.
• The transmit power numbers are based on average performance across all channels.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 40 | Page Parameter Condition Notes Min Typ Max Units Transmit Power for 20 MHz Bandwidth, compliant with IEEE mask and EVM DSSS - 1 Mbps EVM< -9 dB - 17 - dBm DSSS - 2 Mbps EVM< -9 dB - 16.5 - dBm CCK- 5.5 Mbps EVM< -9 dB - 16.5 - dBm CCK - 11 Mbps EVM< -9 dB - 16.5 - dBm OFDM - 6 Mbps EVM< -5 dB - 17.5 - dBm OFDM - 9 Mbps EVM< -8 dB - 17.5 - dBm OFDM - 12 Mbps EVM< -10 dB - 17.5 - dBm OFDM - 18 Mbps EVM< -13 dB - 16.5 - dBm OFDM - 24 Mbps EVM< -16 dB - 15.5 - dBm OFDM - 36 Mbps EVM< -19 dB - 13.5 - dBm OFDM - 48 Mbps EVM< -22 dB - 13.5 - dBm OFDM - 54 Mbps EVM< -25 dB (see note section) - 13.5 - dBm MCS0 Mixed Mode EVM< -5 dB - 16.5 - dBm MCS1 Mixed Mode EVM< -10 dB - 16.5 - dBm MCS2 Mixed Mode EVM< -13 dB - 16.5 - dBm MCS3 Mixed Mode EVM< -16 dB - 15.5 - dBm MCS4 Mixed Mode EVM< -19 dB - 14 - dBm MCS5 Mixed Mode EVM< -22 dB - 13 - dBm MCS6 Mixed Mode EVM< -25 dB (see note section) - 13 - dBm MCS7 Mixed Mode EVM< -27 dB (see note section) - 10.5 - dBm Transmitter Emissions (6 Mbps @ Maximum Power) 776-794 MHz CDMA2000 - -158 - dBm/Hz 869–960 MHz CDMAOne, GSM850 - -158 - dBm/Hz 1450–1495 MHz DAB - -158 - dBm/Hz 1570–1580 MHz GPS - -145 - dBm/Hz

Table 27. WLAN 2.4 GHz Transmitter Characteristics (3.3V)

1. There is a variation of up to 2 dB in power across channels.
2. To meet FCC emission limits, band edge channels (1 and 11) TX power has to be reduced up to 6 dB in

the antenna properties. Refer to the AN1337 application note for more details on the certifications.

1. Across the temperature range of -40 °C to +85 °C, the output power may degrade by up to 2 dB at -40 °C

and by up to 5 dB at +85 °C.

1. There may be a reduction in EVM of up to 1 dB in 54 Mbps data rate, 2 dB in MCS6 data rate, and 4 dB in
2. IEEE spectral mask limits may be crossed in lower data rates in some channels, and if required power may

• All WLAN receiver sensitivity numbers and adjacent channel numbers are at < 10% PER limit. Packet sizes are 1024 bytes for 802.11 b/g data rates and 4096 bytes for 802.11 n data rates.
• For WLAN ACI cases, the desired signal power is 3 dB above standard defined sensitivity level.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 42 | Page Parameter Condition/Notes Min Typ Max Units Sensitivity for 20 MHz Bandwidth(1)

1 Mbps DSSS - -95 - dBm

2 Mbps DSSS - -89.5 - dBm 5.5 Mbps CCK - -87.5 - dBm 11 Mbps CCK - -85.5 - dBm

6 Mbps OFDM - -89 - dBm

9 Mbps OFDM - -88 - dBm

12 Mbps OFDM - -88.5 - dBm 18 Mbps OFDM - -86.5 - dBm 24 Mbps OFDM - -82.5 - dBm 36 Mbps OFDM - -78.5 - dBm

48 Mbps OFDM - -75 - dBm

54 Mbps OFDM - -73 - dBm

MCS0 Mixed Mode - -88 - dBm MCS1 Mixed Mode - -85.5 - dBm MCS2 Mixed Mode - -83 - dBm MCS3 Mixed Mode - -80.5 - dBm MCS4 Mixed Mode - -77 - dBm MCS5 Mixed Mode - -72 - dBm MCS6 Mixed Mode - -70 - dBm MCS7 Mixed Mode - -69.5 - dBm Maximum Input Level for PER below 10% 802.11 b - 0 - dBm 802.11g - -10 - dBm 802.11n - -10 - dBm RSSI Accuracy Range -3 - 3 dB Blocking level for 3 dB RX Sensitivity Degradation(Data rate

6 Mbps OFDM, Desired signal at -

79 dBm) 776–794 MHz - -4 - dBm 824–849 MHz - -4 - dBm 880–915 MHz - -4 - dBm 1710–1785 MHz - -14 - dBm 1850–1910 MHz - -13 - dBm 1920–1980 MHz - -15 - dBm 2300–2400 MHz - -60 - dBm 2570–2620 MHz - -23 - dBm 2545–2575 MHz - -22 - dBm Return Loss -10 - - dB Adjacent Channel Interference 1 Mbps DSSS - 36 - dB

11 Mbps DSSS - 37 - dB

6 Mbps OFDM - 38 - dB

54 Mbps OFDM - 22 - dB

1 Mbps DSSS - 44 - dB

11 Mbps DSSS - 35 - dB

6 Mbps OFDM - 46 - dB

54 Mbps OFDM - 30 - dB

Table 28. WLAN 2.4 GHz Receiver Characteristics on HP RF Chain

1. Receiver sensitivity may be degraded by up to 6.5 dB for channels 5,6,7,8,13 & 14 due to the desensitization

of the receiver by harmonics of the system clock (40 MHz).

1. There may be a degradation of up to 2 dB across the operating temperature range of -40 °C to +85 °C.

1 Mbps DSSS - -93 - dBm

9 Mbps OFDM - -86 - dBm

18 Mbps OFDM - -83 - dBm

1 Mbps DSSS - 40 - dB

11 Mbps DSSS - 36 - dB

6 Mbps OFDM - 42 - dB

36 Mbps OFDM - 30 - dB

1 Mbps DSSS - 50 - dB

11 Mbps DSSS - 38 - dB

6 Mbps OFDM - 48 - dB

36 Mbps OFDM - 38 - dB

Table 29. WLAN 2.4 GHz Receiver Characteristics on LP RF Chain

1. Receiver sensitivity may be degraded by up to 6.5 dB for channels 5,6,7,8,13 & 14 due to the desensitization

of the receiver by harmonics of the system clock (40 MHz).

1. There may be a degradation of up to 2 dB across the operating temperature range of -40 °C to +85 °C.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 45 | Page

3.5.4 Bluetooth Transmitter Characteristics on High-Performance (HP) RF Chain

3.5.4.1 Transmitter characteristics with 3.3 V Supply TA = 25 °C, PA2G_AVDD/VINBCKDC = 3.3 V. Remaining supplies are at typical operating conditions. Parameters are measured at antenna port.(1)

• For Bluetooth C/I cases, the desired signal power is 3 dB above standard defined sensitivity level. Parameter Condition/Notes Min Typ Max Units Transmit Power BR - 12 - dBm EDR 2Mbps - 12 - dBm EDR 3Mbps - 11 - dBm LE 1Mbps - 18 - dBm LE 2Mbps - 18 - dBm LR 500 Kbps - 18 - dBm LR 125 Kbps - 18 - dBm Power Control Step BR, EDR - 3 - dB Adjacent Channel Power |M-N| = 2 BR - - -20 dBm EDR - - -20 dBm LE - - -20 dBm LR - - -20 dBm Adjacent Channel Power |M-N| > 2 BR - - -40 dBm EDR - - -40 dBm LE - - -30 dBm LR - - -30 dBm BR Modulation Characteristics DH1 -25 - 25 kHz DH3 -40 - 40 kHz DH5 -40 - 40 kHz Drift Rate -20 - 20 kHz/50 us Δf1 Avg 140 - 175 kHz Δf2 Max 115 - kHz EDR Modulation Characteristics RMS DEVM, EDR2 - 10 - % RMS DEVM, EDR3 - 6 - % 99% DEVM, EDR2 - 17 - % 99% DEVM, EDR3 - 12 - %

Table 30. Bluetooth Transmitter Characteristics on HP RF Chain 3.3V

1. There is a variation of up to 2 dB in power across channels.
2. Noise-floor is -160 dBm/Hz with spurious tone power of -66 dBm at 1601.33 MHz when transmitted signal is
3. Across the temperature range of -40 °C to +85 °C, the output power may degrade by up to 2 dB at -40 °C

and by up to 5 dB at +85 °C.

3.5.5 Bluetooth Transmitter Characteristics on Low-Power (LP) 0 dBm RF Chain

• For Bluetooth C/I cases, the desired signal power is 3 dB above standard defined sensitivity level. Parameter Condition/Notes Min Typ Max Units Transmit Power LE 1Mbps - - -3.5 dBm LE 2Mbps - - -3.5 dBm LR 500 Kbps - - -3.5 dBm LR 125 kbps - - -3.5 dBm Adjacent Channel Power |M-N| = 2 LE - - -20 dBm LR - - -20 dBm Adjacent Channel Power |M-N| > 2 LE - - -30 dBm LR - - -30 dBm BR Modulation Characteristics DH1 -25 - 25 kHz DH3 -40 - 40 kHz DH5 -40 - 40 kHz Drift Rate -20 - 20 kHz Δf1 Avg 140 - 175 kHz Δf2 Max 115 - - kHz BLE Modulation Characteristics Δf1 Avg 225 - 275 kHz Δf2 Max 185 - - kHz Δf2 Avg/Δf1 Avg 0.8 - - -

Table 31. Bluetooth Transmitter Characteristics on LP 0 dBm RF Chain

1. There is a variation of up to 2 dB in power across channels.
2. Noise-floor is -160 dBm/Hz with spurious tone power of -66 dBm at 1601.33 MHz when transmitted signal is
3. Across the temperature range of -40 °C to +85 °C, the output power may degrade by up to 2 dB at -40 °C and

3.5.6 Bluetooth Receiver Characteristics on High-Performance (HP) RF Chain

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 48 | Page Parameter Condition/Notes Min Typ Max Units EDR2 (2 Mbps), 679 bytes, 2-DH5 Packet, BER= 0.01% - -91 - dBm EDR3 (3 Mbps), 1020 bytes, 3- DH5 Packet, BER= 0.01% - -85 - dBm LE (1 Mbps), 37 bytes, PER=30.8% - -92 - dBm LE (2 Mbps), 37 bytes, PER=30.8% - -90 - dBm LR (500 Kbps), 37 bytes, PER=30.8% - -99 - dBm LR (125 Kbps), 37 bytes, PER=30.8% - -103 - dBm Maximum Input Level BR, EDR2, EDR3,BER= 0.1% - -16 - dBm LE 1Mbps, 2Mbps,PER=30.8% - 10 - dBm LR 500kps, 125kbps,PER=30.8% - 10 - dBm C/I Performance BR, co-channel, BER=0.1% 9 - - dB BR, adjacent +1/-1 MHz, BER=0.1% -2 - - dB BR, adjacent +2/-2 MHz BER=0.1% -19 - - dB BR, adjacent >=|±3| MHz BER=0.1% -19 - - dB BR, Image channel BER=0.1% -11 - - dB BR, adjacent to Image channel BER=0.1% -22 - - dB EDR2, co-channel BER=0.1% 11 - - dB EDR2, adjacent +1/-1 MHz BER=0.1% -2 - - dB EDR2, adjacent +2/-2 MHz BER=0.1% -17 - - dB EDR2, adjacent >=|±3| MHz BER=0.1% -17 - - dB EDR2, Image channel BER=0.1% -9 - - dB EDR2, adjacent to Image channel BER=0.1% -22 - - dB EDR3, co-channel BER=0.1% 19 - - dB EDR3, adjacent +1/- MHz BER=0.1% 3 - - dB EDR3, adjacent +2/-2 MHz BER=0.1% -12 - - dB EDR3, adjacent >=|±3| MHz BER=0.1% -12 - - dB EDR3, Image channel BER=0.1% -2 - - dB

Table 32. Bluetooth Receiver Characteristics on HP RF Chain

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 50 | Page 1. BR,EDR: Receiver sensitivity is degraded by up to 9 dB for channels 38,78 due to the desensitization of the receiver by harmonics of the system clock (40MHz) 2. BLE,LR: Receiver sensitivity is degraded by up to 11.5 dB for channels 19,29,30,39 due to the desensitization of the receiver by harmonics of the system clock (40MHz) 3. There may be a degradation of up to 2 dB across the operating temperature range of -40 °C to +85 °C.

3.5.7 Bluetooth Receiver Characteristics on Low-Power (LP) RF Chain

TA = 25 °C. Parameters are measured at antenna port and applicable to PA2G_AVDD/VINBCKDC=3.3 V Parameter Condition/Notes Min Typ Max Units Sensitivity, Dirty TX off(1),(2) BR (1 Mbps), 339 bytes, DH5 Packet BER= 0.1% - -85 - dBm EDR2 (2 Mbps), 679 bytes, 2-DH5 Packet, BER= 0.01% - -83 - dBm LE (1 Mbps), 37 bytes, PER=30.8% - -89 - dBm LE (2 Mbps), 37 bytes, PER=30.8% - -87 - dBm LR (500 Kbps), 37 bytes, PER=30.8% - -97 - dBm LR (125 Kbps), 37 bytes, PER=30.8% - -101 - dBm Maximum Input Level BR, EDR2 BER= 0.1% - -16 - dBm LE 1Mbps, 2Mbps PER=30.8% - 3 - dBm LR 500kps, 125kbps PER=30.8% - 10 - dBm BER Floor - 1e-4 - % C/I Performance BR, co-channel BER= 0.1% 9 - - dB BR, adjacent +1/-1 MHz, BER=0.1% -2 - - dB BR, adjacent +2/-2 MHz BER=0.1% -19 - - dB BR, adjacent >=|±3| MHz BER=0.1% -19 - - dB BR, Image channel BER=0.1% -11 - - dB BR, adjacent to Image channel BER=0.1% -22 - - dB EDR2, co-channel BER=0.1% 11 - - dB EDR2, adjacent +1/-1 MHz BER=0.1% -2 - - dB EDR2, adjacent +2/-2 MHz BER=0.1% -17 - - dB

Table 33. Bluetooth Receiver Characteristics on LP RF Chain

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 52 | Page 1. BR,EDR: Receiver sensitivity is degraded by up to 9 dB for channels 38,78 due to the desensitization of the receiver by harmonics of the system clock (40MHz) 2. BLE,LR: Receive sensitivity is degraded by up to 11.5 dB for channels 19,29,30,39 due to the desensitization of the receiver by harmonics of the system clock (40MHz) 3. There may be a degradation of up to 2 dB across the operating temperature range of -40 °C to +85 °C.

3.6 Typical Current Consumption

3.6.1 3.3 V

3.6.1.1 WLAN

Parameter Description Value Units

1 Mbps Listen LP Chain

13.82 mA 1 Mbps RX Active LP Chain 19.67 mA

6 Mbps RX Active HP Chain

48.2 mA 72 Mbps RX Active HP Chain 48.2 mA

11 Mbps TX Active Tx Power = Maximum (18dBm)

Tx Power = 8dBm 270 130 mA mA

6 Mbps TX Active Tx Power = Maximum (18dBm)

Tx Power = 8dBm 285 130 mA mA

54 Mbps TX Active Tx Power = Maximum (15dBm)

Tx Power = 8dBm 200 130 mA mA

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 53 | Page Parameter Description Value Units

72 Mbps TX Active Tx Power = Maximum (12dBm)

Tx Power = 8dBm 180 130 mA mA Deep Sleep GPIO Wake up 0.9 uA Standby State retained 13.1 uA Standby Associated, DTIM = 1 293 uA Standby Associated, DTIM = 3 119 uA Standby Associated, DTIM = 10 51 uA

3.6.1.2 Bluetooth BR and EDR

Parameter Description Value Units TX Active Current, 1 Mbps BR LP chain, Tx Power = -2 dBm HP chain, Tx Power = Maximum (12 dBm) 9.9 130 mA mA RX Active Current, 1 Mbps BR LP chain HP chain 10.2 26.7 mA mA TX Active Current, 2 Mbps EDR HP chain, Tx Power = Maximum (12 dBm) 130 mA RX Active Current, 2 Mbps EDR LP chain HP chain 10.2 26.7 mA mA TX Active Current, 3 Mbps EDR HP chain, Tx Power = Maximum (12 dBm) 140 mA RX Active Current, 3 Mbps EDR HP chain 26.7 mA Deep Sleep GPIO Wake up 0.9 uA Standby State RAM retained 13.1 uA

3.6.1.3 Bluetooth LE

Parameter Description Value Units TX Active Current LP chain, Tx Power = -2 dBm LP Chain, Tx Power = 2 dBm HP Chain, Tx Power = Maximum (18 dBm) 8.9 190 mA mA mA RX Active Current LP chain HP chain 10.9 26.7 mA mA Deep Sleep GPIO Wakeup 0.9 uA Standby State retained 13.1 uA Advertising, Unconnectable Advertising on all 3 channels 22.4 uA

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 54 | Page Parameter Description Value Units Advertising Interval = 1.28s Tx Power = -2 dBm, LP chain Advertising, Connectable Advertising on all 3 channels Advertising Interval = 1.28s Tx Power = -2 dBm, LP chain 30.1 uA Connected Connection Interval = 1.28s No Data Tx Power = -2 dBm, LP chain 21.8 uA Connected Connection Interval = 200ms No Data Tx Power = -2 dBm, LP chain 72 uA

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 55 | Page

4 RS9116 B00 Module Detailed Description

4.1 Overview

RS9116 B00 module is based on Silicon Labs’ RS9116 ultra-low-power, single spatial stream, 802.11n + BT/BLE5.0 Convergence SoC. The RS9116 B00 module provides low-cost CMOS integration of a multi-threaded MAC processor (ThreadArch®), baseband digital signal processing, analog front-end, crystal oscillator, calibration eFuse, 2.4GHz RF transceiver, integrated power amplifier, match, bandpass filters(BPF), antenna diversity switch (DPDT) and Quad-SPI Flash thus providing a fully-integrated solution for a range of hosted and embedded wireless applications. With Silicon Labs' embedded four-threaded processor and on-chip ROM and RAM, these chipsets enable integration into low- cost and zero host load applications. With an integrated PMU and support for a variety of digital peripherals, RS9116 enables very low-cost implementations for wireless hosted and embedded applications. It can be connected to a host processor through SDIO, USB, SPI or UART interfaces. Wireless firmware upgrades and provisioning are supported.

4.2 Module Features

4.2.1 WLAN

• Compliant to single-spatial stream IEEE 802.11 b/g/n with single band support
• Support for 20 MHz channel bandwidth
• Transmit power up to +18 dBm with integrated PA
• Receive sensitivity as low as -96 dBm
• Data Rates: 802.11b: Up to 11 Mbps; 802.11g: Up to 54 Mbps; 802.11n: MCS0 to MCS7
• Operating Frequency Range: 2412 MHz – 2484 MHz

4.2.1.1 MAC

• Conforms to IEEE 802.11b/g/n/j standards for MAC
• Dynamic selection of fragment threshold, data rate, and antenna depending on the channel statistics
• Hardware accelerators for WEP 64/128-bit and AES
• WPA, WPA2, and WMM support
• AMPDU and AMSDU aggregation for high performance
• Firmware downloaded from host based on application
• Hardware accelerators for DH (for WPS)

4.2.1.2 Baseband Processing

• Supports DSSS for 1, 2 Mbps and CCK for 5.5, 11 Mbps
• Supports all OFDM data rates (6, 9, 12, 18, 24, 36, 48, 54 Mbps, MCS0 to MCS7), and Short GI in Hosted mode
• Supports IEEE 802.11n single-stream modes with data rates up to 150 Mbps
• Supports long, short, and HT preamble modes
• High-performance multipath compensation in OFDM, DSSS, and CCK modes

4.2.2 Bluetooth

• Transmit power up to +16 dBm with integrated PA
• Receive sensitivity:- LE: -92 dBm, LR 125 Kbps: -102 dBm
• Compliant to dual-mode Bluetooth 5
• <8 mA transmit current in Bluetooth 5 mode, 2 Mbps data rate
• Data rates: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps, 3 Mbps
• Operating Frequency Range: 2.402 GHz - 2.480 GHz

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 56 | Page

• Bluetooth Low Energy 1 Mbps, 2 Mbps and Long Range modes
• Bluetooth Low Energy Secure connections
• Bluetooth Low Energy supports central role and peripheral role concurrently
• Bluetooth auto rate and auto TX power adaptation
• Scatternet* with two secondary roles while still being visible * For a detailed list of software features and available profiles, refer to the Software Reference Manuals or contact Silicon Labs for availability.

4.2.2.1 MAC

4.2.2.1.1 Link Manager

• Creation, modification & release of logical links
• Connection establishment between Link managers of two Bluetooth devices
• Link supervision is implemented in Link Manager
• Link power control is done depending on the inputs from Link Controller
• Enabling & disabling of encryption & decryption on logical links
• Services the data transport requests from L2CAP and provides required QOS
• Support for security using ECDH hardware accelerator

4.2.2.1.2 Link Controller

• Encodes and decodes header of BT packets
• Manages flow control, acknowledgment, retransmission requests, etc.
• Stores the last packet status for all logical transports
• Chooses between SCO & ACL buffers depending on the control information coming from BBP resource manager
• Indicates the success status of packet transmission to upper layers
• Indicates the link quality to the LMP layer

4.2.2.1.3 Host Controller

• Receives & decodes commands received from the Bluetooth Host.
• Propagates the decoded commands to respective modules
• Responsible for transmitting and receiving packets from and to Host
• Formats the responses coming from other modules of Bluetooth Controller as events and sends them to the Host.

4.2.2.1.4 Device Manager

• Controls Scan & Connection processes
• Controls all BT Device operations except data transport operations
• Storing link keys
• BT Controller state transition management
• Slot synchronization & management
• Access contract management
• Scheduler

4.2.2.2 Baseband Processing

• Supports GFSK (1 Mbps), EDR-DQPSK, EDR-D8PSK

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 57 | Page

• Supports BLE and Bluetooth long range
• Supports Data rates up to 3 Mbps

4.2.3 RF Transceiver

• Integrated 2.4 GHz transceiver with highly programmable operating modes
• Internal oscillator with 40 MHz crystal
• Inbuilt automatic boot up and periodic calibration enables ease of integration

4.2.4 Host Interfaces

• SDIO o Version 2.0-compatible o Supports SD-SPI, 1-bit, and 4-bit SDIO modes o Operation up to a maximum clock speed of 50 MHz
• SPI Interface o Operation up to a maximum clock speed of 100 MHz
• USB 2.0 o Supports 480Mbps “High Speed” (HS), 12Mbps “Full Speed” (FS) and 1.5Mbps “Low Speed” (LS) serial data transmission o Support USB CDC and device mode
• UART o Supports variable baud rates between 9600 and 3686400 bps o AT command interface for configuration and data transmission/reception NOTE: Hosted mode (n-Link) supports USB 2.0 and SDIO. Embedded Mode (WiSeConnect) supports SPI, USB CDC, and UART.

4.2.4.1 Auto Host Detection

RS9116 detects the host interface automatically after connecting to respective host controllers like SDIO, SPI, UART, USB and USB-CDC. SDIO/SPI host interface is detected through the hardware packet exchanges. UART host interface is detected through the software based-on the received packets on the UART interface. USB-Device mode interface is detected through the hardware based-on VBUS signal level. The host interface detection between USB & USB-CDC will be taken care by the firmware based on the USB_CDC_DIS GPIO. This Host configuration is stored in always-on domain registers after detection (on power up) and reused this information at each wakeup.

4.2.5 Wireless Coexistence Manager

• Arbitration between Wi-Fi, Bluetooth, and Bluetooth Low Energy
• Application aware arbitration
• Adaptive frequency hopping (AFH) in Bluetooth is based on WLAN channel usage
• Pre inter thread interrupts generation for radio switching
• QoS assurance across different traffics

4.2.6 Software

The RS9116 software package supports 802.11 b/g/n Client, Access Point (Up to 16 clients), Concurrent Client and Access Point mode, Enterprise Security, dual-mode BT 5.0 functionality on a variety of host platforms and operating systems. The software package includes complete firmware, reference drivers, application profiles and configuration graphical user interface (GUI) for Linux operating systems. The Wi-Fi driver has support for a simultaneous access point, and client mode. Bluetooth host driver utilizes Opensource host stacks like BlueZ for Linux. The application layer supports all profiles supported by BlueZ on Linux. It has a wireless coexistence manager to arbitrate between protocols. The RS9116 software package is available in two flavors

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 58 | Page

• Hosted mode (n-Link™): Wi-Fi stack, Bluetooth stack and profiles, and all network stacks reside on the host processor. Support for multiple Virtual Access Points available.
• Embedded mode (WiSeConnect™): Wi-Fi stack, TCP/IP stack, IP modules, Bluetooth stack and some profiles reside in RS9116; Some of the Bluetooth profiles reside in the host processor NOTE: Please refer to the Software Manuals (TRM and PRM) in RS9116 Document Library for more details.

4.2.6.1 Hosted Mode (n-Link™)

• Available host interfaces: SDIO 2.0 and USB HS
• Application data throughput up to 50 Mbps (Hosted Mode) in 802.11n with 20MHz bandwidth.
• Host drivers for Linux
• Support for Client mode, Access point mode (Up to 16 clients), Concurrent Client and Access Point mode, Enterprise Security
• Support for concurrent Wi-Fi, dual-mode Bluetooth 5

4.2.6.2 Embedded Mode (WiSeConnect™)

• Available host interface: UART, SPI, and USB CDC
• Support for Embedded Client mode, Access Point mode (Up to 8 clients), Concurrent Client and Access Point mode, and Enterprise Security
• Supports advanced security features: WPA/WPA2-Personal and Enterprise
• Integrated TCP/IP stack, HTTP/HTTPS, SSL/TLS, MQTT
• Bluetooth inbuilt stack support for L2CAP, RFCOMM, SDP, SPP, GAP
• Bluetooth profile support for GAP, SDP, SPP, GATT, L2CAP, RFCOMM
• Wireless firmware update and provisioning
• Support for concurrent Wi-Fi, dual-mode Bluetooth 5 * For a detailed list of software features and available profiles, refer to the Software Reference Manuals or contact Silicon Labs for availability.

4.2.7 Security

RS9116 supports multiple levels of security capabilities available for the development of IoT devices.

• Accelerators: AES128/256 in Embedded Mode
• WPA/WPA2-Personal, WPA/WPA2 Enterprise for Client * For a detailed list of software features and available profiles, refer to the Software Reference Manuals or contact Silicon Labs for availability.

4.2.8 Power Management

The RS9116 chipsets have an internal power management subsystem, including DC-DC converters and linear regulators. This subsystem generates all the voltages required by the chipset to operate from a wide variety of input sources.

• LC DC-DC switching converter for RF and Digital blocks o Wide input voltage range (1.85 to 3.6 V) on pin VINBCKDC o Output - 1.4 V and 300 mA maximum load on pin VOUTBCKDC
• SC DC-DC - Switching converter for Always-ON core logic domain o Wide input voltage range (1.85 to 3.6 V) on pin UULP_VBATT_1 and UULP_VBATT_2

• LDO SOC - Linear regulator for digital blocks o Input - 1.4 V from LC DC-DC or external regulated supply on pin VINLDOSOC o Output - 1.15 V and 300mA maximum load on pin VOUTLDOSOC
• LDO RF and AFE - Linear regulator for RF and AFE o Input - 1.4 V from LC DC-DC or external regulated supply on pin RF_AVDD o Output - 1.1 V and 20 mA maximum load on pin VOUTLDOAFE

4.2.8.1 Output Voltage Ranges

Table 34. Min and Max Specifications of Various Output Voltages The output voltages from the IC/module will be reflected as per specifications only after the firmware is loaded.

4.2.9 Low Power Modes

It supports Ultra-low power consumption with multiple power modes to reduce the system energy consumption.

• Dynamic Voltage and Frequency Scaling
• Low Power (LP) mode with only the host interface active
• Deep sleep (ULP) mode with only the sleep timer active – with and without RAM retention
• Wi-Fi standby associated mode with automatic periodic wake-up
• Automatic clock gating of the unused blocks or transit the system from Normal to LP or ULP modes

4.2.9.1 ULP Mode

• Timeout wakeup - Exit sleep state after programmed timeout value.
• GPIO Based Wakeup: Exit sleep state when GPIO goes High/Low based on programmed polarity.
• Analog Comparator Based wakeup - Exit sleep state on an event at the analog comparator.
• RTC Timer wakeup - Exit Sleep state on timeout of RTC timer
• WatchDog Interrupt based wakeup - Exit Sleep state upon watchdog interrupt timeout. ULP mode is not supported in the USB interface mode

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 60 | Page

4.2.9.2 LP Mode

In Low Power mode, Network processor maintains system state and gate all internal high frequency clocks. But host interface is ready to accept any command from host controller. The LP mode supports the following wake-up options:

• Host Request - Exit sleep state on a command from HOST controller. whenever a command from the host is received, the processor serves the request with minimum latency and the clock is gated immediately after the completion of the operation to reduce power consumption
• GPIO based wakeup - Wakeup can be initiated through a GPIO pin
• Timeout wakeup - Exit sleep state after the programmed timeout value

4.2.10 Memory

4.2.10.1 On-chip Memory

The ThreadArch® processor has the following memory:

• On-chip SRAM for the wireless stack.
• 512Kbytes of ROM which holds the Secure primary bootloader, Network Stack, Wireless stacks, and security functions.
• 16Kbytes of Instruction cache enabling eXecute In Place (XIP) with quad SPI flash memory.
• eFuse of 512 bytes (used to store primary boot configuration, security, and calibration parameters)

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 61 | Page

5 RS9116 B00 Module Reference Schematics, BOM and Layout Guidelines

1. Customers should include provision for programming or updating the firmware at manufacturing. 2. If using UART, we recommend bringing out the SPI lines to test points, so designers could use the faster interface for programming the firmware as needed. 3. If using SPI as host interface, then firmware programming or update can be done through the host MCU, or if designer prefers to program standalone at manufacturing, then it is recommended to have test points on the SPI signals.

5.1 SDIO/SPI/UART

5.1.1 Schematics

The below diagram shows the typical schematic with SDIO/SPI/UART Host Interface and Internal Flash.

Figure 16. Schematics with SDIO/SPI/UART Host Interface

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 63 | Page 4. PA2G_AVDD can be driven by 3.3V source irrespective of other sources for Maximum Transmit Output power. 5. The supplies can be driven by different voltage sources within the recommended operating conditions specified in Specifications section. 6. SDIO_IO_VDD can be driven by a different source irrespective of other sources to support different interfaces. 7. In SDIO mode, pull-up resistors should be present on SDIO_CMD & SDIO Data lines as per the SDIO physical layer specification, version 2.0. 8. In SPI mode, ensure that the input signals, SPI_CS and SPI_CLK are not floating when the device is powered up and reset is deasserted. This can be done by ensuring that the host processor configures its signals (outputs) before deasserting the reset. SPI_INTR is the interrupt signal driven by the secondary device. This signal may be configured as Active-high or Active-low. If it is active-high, an external pull-down resistor is required. If it is active-low, an external pull-up resistor is required. The following action can be carried out by the host processor during power-up of the device, and before/after ULP Sleep mode. a. To use the signal in the Active-high or Active-low mode, ensure that, during the power up of the device, the Interrupt is disabled in the Host processor before deasserting the reset. After deasserting the reset, the Interrupt needs to be enabled only after the SPI initialization is done and the Interrupt mode is programmed to either Active-high or Active-low mode as required. b. The Host processor needs to be disable the interrupt before the ULP Sleep mode is entered and enable it after SPI interface is reinitialized upon wakeup from ULP Sleep. 9. In UART mode, ensure that the input signals, UART_RX and UART_CTS are not floating when the device is powered up and reset is deasserted. This can be done by ensuring that the host processor configures its signals (outputs) before deasserting the reset. 10. Resistor "R1" should not be populated if UART is used as Host Interface.

5.1.2 Bill of Materials

S.No. Quantity Reference Value Description JEDEC Manufacturer Part Number 1 2 C2,C3 10uF CAP CER 10UF 10V X5R 0805

0805 Murata GRM21BR61A106KE19L

2 3 C4,C5,C10 1uF CAP CER 1UF 10V 10% X5R 0402

0402 Murata GRM155R61A105KE15D

3 6 C1,C6,C7,C8,C9,C11 0.1uF CAP CER 0.1UF 10V X5R 0402

0402 Murata GRM155R61A104KA01D

4 1 Z1 8.2pF CER CHP 8.2P +/-0.25P C0G 0201 25V

0201 Murata GRM0335C1E8R2CD01D

5 1 J1 Antenna/U.FL

0805 Murata DFE201210U-1R0M=P2

Table 35. Bill of Materials with SDIO/SPI/UART Host Interface

5.2 USB/USB-CDC

5.2.1 Schematics

The below diagram shows the typical schematic with USB/USB-CDC Host Interface and Internal Flash.

Figure 17. Schematics with USB/USB-CDC Host Interface

50 Ohm RF line

90 Ohm Differential Lines

1. PA2G_AVDD can be driven by 3.3V source irrespective of other sources for Maximum Transmit Output power.
2. The supplies can be driven by different voltage sources within the recommended operating conditions specified in Specifications section.
3. Ensure that the pin USB_CDC_DIS is left unconnected to ensure normal USB functionality.
4. Resistor "R1" should not be populated if normal USB is used as Host Interface.

5.2.2 Bill of Materials

0402 Yageo RC0402FR-074K7L

0201 Yageo RC0201FR-07200RL

Table 36. Bill of Materials with USB/USB-CDC Host Interface

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 67 | Page

5.3 Layout Guidelines

1. The following Supply Pins needs to be STAR routed from the Supply Source a. VINBCKDC b. UULP_VBATT_1 c. UULP_VBATT_2 d. RF_VBATT e. VINLDO1P8 f. PA2G_AVDD g. ULP_IO_VDD h. SDIO_IO_VDD i. IO_VDD_1, IO_VDD_2, IO_VDD_3 2. The RF_PORT1 (Module Pin No. A18) signal may be directly connected to an on-board chip antenna or terminated in an RF connector of any form factor for enabling the use of external antennas. 3. There need to be DC blocking capacitors (8.2pF) on RF_PORT1 if they are connected to Antenna 4. The RF trace on RF_PORT1 should have a characteristic impedance of 50 Ohms. Any standard 50 Ohms RF trace (Microstrip or Coplanar wave guide) may be used. The width of the 50 Ohms line depends on the PCB stack, e.g., the dielectric of the PCB, thickness of the copper, thickness of the dielectric and other factors. Consult the PCB fabrication unit to get these factors right. 5. To evaluate transmit and receive performance like Tx Power and EVM, Rx sensitivity and the like, an RF connector would be required. A suggestion is to place a ‘microwave coaxial connector with switch’ between RF_PORT1 and the antenna. 6. The layout Guidelines for the BUCK are as follows:- a. Minimize the loop area formed by inductor switching node, output capacitors & input capacitors. This helps keep high current paths as short as possible. Keeping high current paths shorter and wider would help decrease trace inductance & resistance. This would significantly help increase the efficiency in high current applications. This reduced loop area would also help in reducing the radiated EMI that may affect nearby components. b. VINBCKDC Capacitor should be very close to the Module Pin & the Ground Pad of the capacitor should have direct vias to the Ground Plane underneath. c. Buck Inductor should be close to Module VOUTBCKDC pin and buck capacitor should be placed closed to the Inductor; the Ground Pad of the capacitor should have direct vias to the Ground Plane underneath. d. The Ground Plane underneath the Buck Inductor in the Top Layer should be made as an isolated copper patch and should descend down to the Second Layer (Main Ground) through multiple Vias. e. The path from VOUTBCKDC to VINLDOSOC is a high current path. The Trace should be as short & wide as possible and is recommended to run a Grounded Shield Traces on either side of this High Current Trace f. The Capacitor on VINLDOSOC should be very close to the Module Pin & the Ground Pad of the capacitor should have direct vias to the Ground Plane underneath. 7. For USB, it is recommended that the components and their values in the BoM be adhered to. 8. It is highly recommended that the two USB differential signals (USB_DP and USB_DN) be routed in parallel with a spacing (say, a) which achieves 90 Ω of differential impedances, 45 Ω for each trace.

1. All decoupling capacitors placement must be as much close as possible to the corresponding power pins, and the

trace lengths as short as possible.

1. Ensure all power supply traces widths are sufficient enough to carry corresponding currents.
2. Add GND copper pour underneath IC/Module in all layers, for better thermal dissipation.

Figure 21. Antenna Layout Recommendations

• The above figure shows the antenna footprint details for 0.8 mm thickness FR4 PCB.
• This layout guidelines are as per antenna part guidelines. For more details, please refer to the antenna datasheet. The recommended Chip Antennas are λ/4 antennas. They require an external ground plane for proper functioning. The length of the ground plane behind the antenna (from the feed point of antenna to backwards) should be at least 25mm – the longer the ground plane the better the performance. It is recommended to characterize the antenna portion using a Network Analyzer. Electrical performance of any chip antenna is influenced by the physical characteristics of the surrounding ground plane, feed line, other devices, and materials. This can be used as an advantage by manipulating certain parameters to affect resonant frequency and matching. These parameters are listed below: 1. Ground plane configuration 2. Distance from antenna 3. Topology around antenna 4. Feed point transmission line impedance 5. Trace width 6. Trace length

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 70 | Page 7. Matching Network 8. PCB substrate thickness 9. PCB substrate dielectric constant.

6 RS9116 B00 Module Package Description

6.1 Dimensions

Table 37. Module Dimensions

6.2 Package Outline

6.3 Pin Locations

All coordinates in the table below are in millimeters, and in TOP VIEW.

Table 38. Pin Locations

6.3.1 PCB Landing Pattern

Figure 23. PCB Landing Pattern

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 74 | Page

7 RS9116 B00 Module Certification and Ordering Information

7.1 Certification Information

This section will outline the regulatory certification information for the RS9116 modules for the countries listed below. This information will be updated when available. 1. United States 2. Canada 3. Europe 4. Japan 5. United Kingdom 6. Other Regulatory Jurisdictions The RS9116 single band B00 module from Silicon Labs has undergone modular certification for FCC, IC and CE/ETSI (including EN 300 328 v2.2.2), TELEC, and UKCA. Note that any changes to the module’s configuration including (but not limited to) the programming values of the RF Transceiver and Baseband can cause the performance to change beyond the scope of the certification. These changes, if made, may result in the module having to be certified afresh.

7.2 Compliance and Certification

RS9116 - B0014 module is FCC/IC/CE/MIC/TELEC/UKCA certified. This section outlines the regulatory information for the RS9116 - B0014 module. This allows integrating the module in an end product without the need to obtain subsequent and separate approvals from these regulatory agencies. This is valid in the case no other intentional or un-intentional radiator components are incorporated into the product and no change in the module circuitry. Without these certifications, an end product cannot be marketed in the relevant regions. RF Testing Software is provided for any end product certification requirements.

7.2.1 Federal Communication Commission Statement

This device complies with FCC Rules Part 15. Operation is subject to the following two conditions:

• This device may not cause harmful interference.
• This device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a class B digital device, pursuant to Part 15 of the Federal Communications Commission (FCC) rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by doing one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.

7.2.1.1 FCC Caution

Any changes or modifications not expressly approved by the party responsible for compliance could void the user‘s authority to operate the equipment. The antenna(s) used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 75 | Page

7.2.1.2 Radiation Exposure Statements

This equipment must be installed and operated in accordance with provided instructions and the antenna(s) used for this transmitter must be installed to provide a separation distance of at least 20 cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter.

7.2.1.3 FCC Label Instructions

The outside of final products that contains this module device must display a label referring to the enclosed module. This exterior label can use wording such as: “Contains Transmitter Module FCC ID: XF6-B001P4V2P1”,or “Contains FCC ID: XF6-B001P4V2P1”, Any similar wording that expresses the same meaning may be used.

7.2.2 Industry Canada / ISED Statement

This product meets the applicable Innovation, Science and Economic Development Canada technical specifications. Ce produit repond aux specifications techniques applicables a l'innovation, Science et Developpement economique Canada.

7.2.2.1 Radiation Exposure Statement

This equipment complies with IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body. Déclaration d’exposition aux radiations: Cet équipement est conforme aux limites d’exposition aux rayonnements IC établies pour un environnement non contrôlé. Cet équipement doit être installé et utilisé avec un minimum de 20 cm de distance entre la source de rayonnement et votre corps. This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions: 1) This device may not cause interference, and 2) This device must accept any interference, including interference that may cause undesired operation of the device. Le present appareil est conforme aux CNR d’Industrie Canada applicables aux appareils radio exempts de licence. L’exploitation est autorisee aux deux conditions suivantes : 1) l’appareil ne doit pas produire de brouillage; 2) l’utilisateur de l’appareil doit accepter tout brouillage radioelectrique subi, meme si le brouillage est susceptible d’en compromettre le fonctionnement.

7.2.2.2 Labeling and User Information

Innovation, Science and Economic Development Canada ICES003 Compliance Label: CAN ICES-3 (B)/NMB- 3(B) The RS9116 - B0014 module has been labeled with its own IC ID number (8407A-B001P4V2P1) and if the IC ID is not visible when the module is installed inside another device, then the outside of the finished product into which the module is installed must also display a label referring to the enclosed module. This exterior label can use following wording: Contains Transmitter Module IC : 8407A-B001P4V2P1 or Contains IC : 8407A-B001P4V2P1 User manuals for license-exempt radio apparatus shall contain the above mentioned statement or equivalent notice in a conspicuous location in the user manual or alternatively on the device or both Le module RS9116 - B0014 a été étiqueté avec son propre numéro d’ID IC (8407A-B001P4V2P1) et si l’ID IC n’est pas visible lorsque le module est installé dans un autre périphérique, alors l’extérieur du produit fini dans lequel le module est installé doit également afficher une étiquette faisant référence au module inclus. Cette étiquette extérieure peut être libellée comme suit: Contient le module émetteur IC: 8407A-B001P4V2P1 ou contient IC: 8407A- B001P4V2P1. Les manuels d'utilisation d'appareils radio exemptés de licence doivent contenir l'énoncé susmentionné ou une notification équivalente à un endroit bien en évidence dans le manuel d'utilisation. ou alternativement sur l'appareil ou les deux

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 76 | Page

7.2.3 Regulatory Module Integration Instructions

7.2.3.1 List of Applicable FCC Rules

This device complies with part 15.247 of the FCC Rules.

7.2.3.2 Summarize the specific operational use conditions

This module can be used in household electrical appliances as well as lighting equipment(s). The input voltage to the module should be nominally 1.8-3.3 Vdc, typical and the ambient temperature of the module should not exceed 85℃. This module using two kinds of antennas, PCB antenna with maximum gain is 1.00 dBi. Other antenna arrangement is not covered

7.2.3.3 Limited Module Procedures

7.2.3.4 Trace Antenna Designs

7.2.3.5 RF Exposure Considerations

This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator and your body. If the device built into a host as a portable usage, the additional RF exposure evaluation may be required as specified by§ 2.1093.by this certification. The antenna is not field replaceable. If the antenna needs to be changed, the certification should be re-applied.

7.2.3.6 Antennas

Provision for Chip Antenna or other Antennae

7.2.3.7 Label and Compliance Information

7.2.3.8 Information on Test Modes and Additional Testing Requirements

a) The modular transmitter has been fully tested by the module grantee on the required number of channels, modulation types, and modes, it should not be necessary for the host installer to re-test all the available transmitter modes or settings. It is recommended that the host product manufacturer, installing the modular transmitter, perform some investigative measurements to confirm that the resulting composite system does not exceed the spurious emissions limits or band edge limits (e.g., where a different antenna may be causing additional emissions). b) The testing should check for emissions that may occur due to the intermixing of emissions with the other transmitters, digital circuitry, or due to physical properties of the host product (enclosure). This investigation is especially important when integrating multiple modular transmitters where the certification is based on testing each of them in a stand-alone configuration. It is important to note that host product manufacturers should not assume that because the modular transmitter is certified that they do not have any responsibility for final product compliance. c) If the investigation indicates a compliance concern the host product manufacturer is obligated to mitigate the issue. Host products using a modular transmitter are subject to all the applicable individual technical rules as well as to the general conditions of operation in Sections 15.5, 15.15, and 15.29 to not cause interference. The operator of the host product will be obligated to stop operating the device until the interference has been corrected

7.2.3.9 Additional testing, Part 15 sub part B disclaimer

The final host / module combination needs to be evaluated against the FCC Part 15Bcriteria for unintentional radiators in order to be properly authorized for operation as a Part15 digital device.

7.2.3.10 Steps for TX Verification

7.2.3.11 Other in User Manual

The host integrator installing this module into their product must ensure that the final composite product complies with the FCC requirements by a technical assessment or evaluation to the FCC rules, including the transmitter operation and should refer to guidance in KDB 996369.

7.2.3.12 Frequency Spectrum to be Investigated

Section 15.33(b)(1), whichever is the higher frequency range of investigation.

7.2.3.13 Operating the Host Product

emissions from the unintentional radiator, the transmitter shall be placed in the receive mode or idle mode, if possible. C63.26 for further general testing details.

7.2.4 Qualified Antenna Types

an antenna of a different type or gain more than certified gain will require additional testing. Table 39. Qualified Antenna Types for B00 module

7.3 Module Package

Table 40. B00 Module Package

7.4 Ordering Information

Table 41. Part Ordering Options

• SBW: Single Band Wi-Fi (2.4 GHz).
• Customer should include provision for programming or updating the firmware at manufacturing.

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 78 | Page

8 RS9116 B00 Module Documentation and Support

Silicon Labs offers a set of documents which provide further information required for evaluating, and developing products and applications using RS9116. These documents are available in RS9116 Document Library on the Silicon Labs website. The documents include information related to Software releases, Evaluation Kits, User Guides, Programming Reference Manuals, Application Notes, and others. For further assistance, you can contact Silicon Labs Technical Support here.

8.1 Resource Location

RS9116 Document Library : https://docs.silabs.com/rs9116/ Technical Support : http://www.silabs.com/support/

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 79 | Page

9 RS9116 B00 Module Revision History

No. Version No. Date Changes 1 1.0 April, 2019 Initial version 2 1.0.1 May, 2019 • Updated host based schematics. Combined SDIO, SPI & UART host interfaces into one schematic. Combined USB and USB-CDC host interfaces into one schematic

• Updated 32 Khz external oscillator specifications
• Updated antenna layout recommendations for single band antenna
• Updated the Schematics for UART_RTS and UART_CTS Pin correction. 3 1.0.2 May, 2019 Renamed VOUTLDO1P8 as VINLDO1P8 in Pinout Description Removed 32KHz XTAL Pins and used UULP GPIO for feeding in the External Clock. Updated the below sections for the same
• Pinout Description.
• Specifications
• Reference Schematics 4 1.0.3 July, 2019 • Corrected the description of 32KHz external clock in Specifications section
• Added external control for POC_IN in Specifications
• Renamed LP_WAKEUP to LP_WAKEUP_IN and changed its description in Pinout table.
• Added host detection details and updated network processor memory details in Detailed description.
• Updated PCB landing pattern in Package Description
• Removed PLL_AVDD from Absolute Maximum Ratings and Recommended Operating conditions section
• Corrected the initial state of SDIO_D3 to pullup and SDIO_D2 to HighZ. 5 1.0.4 November, 2019 Bluetooth ACI specs corrected (earlier version shows under Typ - should have been under “Min”) 6 1.0.5 July, 2020 • Added note about voltage applied on external Buck Regulator for Typical Current Consumption at 1.85V.
• Updated Applications section.
• Updated 40 MHz Clock specifications.
• Updated LED0 software configuration note for ULP_GPIO_8 under Pin Description.
• Mentioned need for weak pull up resistor under Pin Description to use Wake-on-Wireless feature on ULP_GPIO_6.
• Updated "Digital Input Output Signals" to separate readings at 3.3V and 1.8V.
• Wireless Updated Co-Existence modes in Features list.
• The number of center roles supported by BLE changed from 8 to 6.
• Added a note under Pin Description regarding functionalities that are available on multiple Pins, and their proper usage, e.g., SLEEP_IND_FROM_DEV

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 80 | Page Revision No. Version No. Date Changes

• Updated Generic PCB Layout Guidelines.
• Updated Power Sequence Diagrams under DC Characteristics for POC_IN and POC_OUT.
• Features list updated.
• Reflow profile diagram updated.
• Updated Typical values for BLE ACI characteristics.
• Updated GPIO pin descriptions.
• Updated Bluetooth EDR 2 Mbps LP Chain Receiver specification.
• Removed Legacy Bluetooth Tx on LP Chain.
• Updated WLAN 2.4 GHz 3.3V/1.85V Transmitter specifications. 7 1.0.6 August, 2020 • Updated Features List, removed redundant information.
• Updated Applications, and Software Architecture Diagrams.
• Updated pin descriptions - ULP_GPIO_0 and ULP_GPIO_6.
• Updated Software section with latest information.
• Rebranded to Silicon Labs. 8 1.0.7 September, 2020 • Updated Device Information with new nomenclature to include Silicon revision, and firmware version.
• Updated nomenclature in Pinout diagram, and Pin descriptions.
• Updated schematics to include the new nomenclature.
• SoC Ordering information updated with new OPNs; Device Nomenclature diagram updated. 9 1.0.8 June, 2021 • Module image updated with Silicon Labs logo.
• Added note under Software Architecture diagram on connecting and using multiple hosts at the same time.
• Included EN 300 328-v2.2.2 certification info.
• Removed redundant section ‘Device Information’. Same information is available in section ‘Ordering Information’.
• Pin names updated for consistency; included actual pin names along with signals; updated pins: UART1_RX, UART1_TX, UART2_TX, HOST_BYP_ULP_WAKEUP
• ULP_GPIOs in Pin Description referenced to ULP_IO_VDD instead of IO_VDD_1.
• Updated note on Wake-on-Wireless feature, under Description for pin ULP_GPIO_6.
• Removed ESD and Latch Up information from Absolute Ratings table.
• Updated Min and Max values for RF related pins to reflect only 3.3 V in Recommended Operating Conditions.
• Updated Min and Max values for IO pins to reflect both 1.8 V and in Recommended Operating Conditions.
• Power-Up and Down Sequence with POC_IN connected internally. Included statement that this connection is NRND.

• Updated VIH, VOH to show only Min values; VIL, VOL to show only Max values; IOL, IOH to show only Typ values.
• Updated 32 kHz External Crystal Oscillator specifications to reflect correct Min and Max values for Vac.
• Removed 40 MHz crystal specification because the crystal is integrated inside the module. Added a note under Clock Specifications.
• Timing data included for SDIO_CMD.
• Recommended Operating Conditions for PA2G_AVDD pin updated.
• Added caveats to the RF Characteristics.
• Updated RF Specification section to include numbers at 3.3 V only.
• Updated Note for IEEE spectral mask effects. Added mention of AN1337 application note for certification details.
• Included output voltage power ranges under Power Management.
• Typical Current Consumption section updated to include values at 3.3 V only.
• Removed section on Serial Flash; B00 does not support External Flash.
• Schematics updated to reflect correct voltage for PA2G_AVDD pin.
• Reference Schematics updated to show DC Resistance at 95mohm max (from 70), and Isat at 1.0A min (from 1.5).
• Updated Murata's 1uH inductor part in Schematics and BOM from DFE201210S-1R0M=P2 to DFE201210U-1R0M=P2.
• Updated description for DFE201210S-1R0M=P2 in BOM to FIXED IND 1UH 2.0A 95 MOHM SMD (from 2.3A 70 MOHM SMD).
• Updated Reference Schematics to reflect only 3.3 V input to RF pins.
• Removed External Flash Reference schematics.
• Updated Antenna Layout guidelines for Fractus FR05-S1-N-0-102.
• Removed Device Nomenclature.
• Appended B0014 Certification information.
• Removed Reflow Profile, Soldering and Baking instructions. Information available through the web based RFI system.
• Datasheet updated from Preliminary to Full Production. 10 1.0.9 December, 2022 • Added UKCA certification details

Table 42. Revision History

RS9116 B00 Connectivity Module Datasheet v1.0.9, December 2022 silabs.com | Building a more connected world. Rev 1.0.9 82 | Page