CP2201

CP2200 SILABS | Alldatasheet

Document overview

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Technical content

Figure 1. Example System Diagram

20 MHz

2 Rev. 1.0

Rev. 1.0 3 TABLE OF CONTENTS Section Page

4 Rev. 1.0

Rev. 1.0 5 1. System Overview The CP2200/1 is a single-chip Ether net controller containing an integr ated IEEE 802.3 Ethernet Media Access Controller (MAC), 10BASE-T Ph ysical Layer (PHY), and 8 kB Non-Volatile Flash Memory available in a compact 5 x 5 mm QFN-28 package (sometimes called “MLF” or “MLP”) and a 48-pin TQFP package. The CP2200/1 can add Ethernet connectivity to any microc ontroller or host processor with 11 or more Port I/O pins. The 8-bit parallel interface bus supports both Intel and Motorola bus formats in multiplexed and non-multiplexed mode. The data transfer rate in non-multiplexed mode can exceed 30 Mbps. The on-chip Flash memory may be used to store user cons tants, web server content, or as general purpose non- volatile memory. The Flash is factory preprogrammed wit h a unique 48-bit MAC address stored in the last six memory locations. Having a unique MAC address stored in the CP2200/1 often removes the serialization step from the product manufacturing process of most embedded systems. The CP2200/1 has four power modes with varying levels of functionality that allow the host processor to manage the overall system power consumption. The optional interrupt pin also allows the host to enter a “sleep” mode and awaken when a packet is received or when the CP2200/1 is plugged into a network. Auto-negotiation allows the device to automatically detect the most efficient duplex mode (half/full duplex) supported by the network. The Ethernet Development Kit (Ethernet-DK) bundles a C8051F120 MCU Target Board, CP2200 Ethernet Development Board ( AB4), the Silicon Lab oratories IDE, all necessary debug hardware, and a TCP/IP Configuration Wizard. The Ethernet Development Kit incl udes all hardware, software, and examples necessary to design an embedded system using the CP2200. The CP2200 Ethernet Development Board is also compatible with the C8051F020TB and C8051F340TB. Individual targ et boards may be purc hased online by visiting www.silabs.com.

1. Typical Connection Diagram

Figure 2 and Figure 3 show typical connection diagrams for the 48-pin CP2200 and 28-pin CP2201. Figure 2. Typical Connection Diagram (Non-Multiplexed)

20 MHz 10 MΩ

Note: The CP220x should be placed within 1 inch of the transformer for optimal performance.

Figure 3. Typical Connection Diagram (Multiplexed) Note: The CP220x should be placed within 1 inch of the transformer for optimal performance.

Table 1. Absolute Maximum Ratings operation of the devices at or exceeding the conditions in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

1. Electrical Characteristics

Table 2. Global DC Electrical Characteristics VDD = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified. Table 3. Digital I/O DC Electrical Characteristics VDD = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified.

1. Pinout and Package Definitions

Table 4. CP2200/1 Pin Definitions AV+ 5 3 Power In 3.1–3.6 V Analog Power Supply Voltage Input. VDD1 13 8 Power In 3.1–3.6 V Digital Power Supply Voltage Input. VDD2 30 19 Power In 3.1–3.6 V Digital Power Supply Voltage Input. RST 15 10 D I/O Device Reset. Open-drain output of internal POR and V DD monitor. 10BASE-T link pulses are not detected (Link Fail). packet is transmitted or received and driven low all other times. then returns to its original state after 50 ms. XTAL1 46 28 A In Crystal Input. This pin is the return for the external oscillator driver. This pin can be overdriven by an external CMOS clock. XTAL2 45* 27* A Out Crystal Output. This pin is the excitation driver for a quartz crystal. TX+ 9 6 A Out 10BASE-T Transmit, Dif ferential Output (Positive). TX– 10 7 A Out 10BASE-T Transmit, Dif ferential Output (Negative). RX+ 7 5 A In 10BASE-T Receive, Dif ferential Input (Positive). RX– 6 4 A In 10BASE-T Receive, Dif ferential Input (Negative). for Motorola bus format or directly to GND for Intel bus format. INT 42 25 D Out Interrupt Service Request. This pin provides notification to the host. *Note: Pins can be left unconnected when not used.

CS 41 24 D In Device Chip Select. Table 4. CP2200/1 Pin Definitions (Continued) *Note: Pins can be left unconnected when not used.

Figure 4. 48-pin TQFP Pinout Diagram

Figure 5. 48-pin TQFP Package Dimensions Table 5. TQFP-48 Package

Figure 6. QFN-28 Pinout Diagram (Top View)

Figure 7. QFN-28 Package Drawing Table 6. QFN-28 Package

Figure 8. Typical QFN-28 Landing Diagram

Figure 9. Typical QFN-28 Solder Paste Diagram

18 Rev. 1.0 6. Functional Description 6.1. Overview In most systems, the CP2200/1 is used for transmitting and receiving Ethernet packets, non-volatile data storage, and controlling Link and Activity LEDs. The device is co ntrolled using direct and in direct internal registers accessible through the parallel host interface. All digital pins on the device are 5 V tolerant. 6.2. Reset Initialization After every CP2200/1 reset, the fo llowing initialization procedure is recommended to ensure proper device operation: Step 1: Wait for the reset pin to rise. This step takes the longest during a power-on reset. Step 2: Wait for Oscillator Initialization to complete. The host processor will receive notification through the interrupt request signal once the oscillator has stabilized. Step 3: Wait for Self Initialization to complete. The INT0 interrupt status register on page 31 should be checked to determine when Self Initialization completes. Step 4: Disable interrupts (using INT0EN and INT1EN on page 33 and page 36) for events that will not be monitored or handled by the host processor. By default, all interrupts are enabled after every reset. Step 5: Initialize the physical layer. See “15.7. Initializing the Physical Layer” on page 90 for a detailed physical layer initialization procedure. Step 6: Enable the desired Activity, Link, or Activity/Link LEDs using the IOPWR register on page 45. Step 7: Initialize the media access controller (MAC). See “14.1. Initializing the MAC” on page 78 for a detailed MAC initialization procedure. Step 8: Configure the receive filter. See “12.4. Initializing the Receive Buffer, Filter and Hash Table” on page 59 for a detailed initialization procedure. Step 9: The CP2200/1 is ready to transmit and receive packets. 6.3. Interrupt Request Signal The CP2200/1 has an interrupt request signal (INT ) that can be used to notify the host processor of pending interrupts. The INT signal is asserted upon detection of any enabl ed interrupt event. Host processors that cannot dedicate a port pin to the INT signal can periodically poll the interrupt status registers to see if any interrupt generating events have occurred. If the /INT signal is not used, pending interrupts such a Receive FIFO Full must still be serviced. The 14 interrupt sources are listed below. Interrupts are enabled on reset and can be disabled by software. Pending interrupts can be cleared (allowing the INT signal to de-assert) by reading the self-clearing interrupt registers. See “8. Interrupt Sources” on page 30 for a complete description of the CP2200/1 interrupts. „ End of Packet Reached „ Packet Received „ Receive FIFO Empty „ “Wake-on-LAN” Wakeup Event „ Receive FIFO Full „ Link Status Changed „ Oscillator Initialization Complete „ Jabber Detected „ Self Initialization Complete „ Auto-Negotiation Failed „ Flash Write/Erase Complete „ Remote Fault Notification „ Packet Transmitted „ Auto-Negotiation Complete

Figure 10. Crystal Oscillator Example and shielded with a ground plane from any other traces that could introduce noise or interference. Figure 11. External CMOS Clock Example

10 M Ω20 MHz

Table 7. Clocking Requirements VDD = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified. Table 8. Input Clock Pin (XTAL1) DC Electrical Characteristics VDD = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified.

22 Rev. 1.0 6.6. Sending and Receiving Packets After reset initialization is complete , the CP2200/1 is ready to send and receive packets. Packets are sent by loading data into the transmit buffer using the AutoWrite register and writing ‘1’ to TXGO. See “11.2. Transmitting a Packet” on page 48 for detailed information on how to tr ansmit a packet using the transmit interface. A Packet Transmitted interrupt will be generated once transmission is complete. Packet reception occurs automa tically when reception is enabled in th e MAC and the receive buffer is not full. Once a packet is received, the host processor is notified by generating a Packet Received interrupt. The host may read the packet using the AutoRead interface. See “12.2. Reading a Packet Using the Autoread Interface” on page 58 and “12.4. Initializing the Receive Buffer, Filter and Hash Table” on page 59 for additional information on using and initializing the receive interface.

24 Rev. 1.0 Register 1. RAMADDRH: RAM Address Pointer High Byte Register 2. RAMADDRL: RAM Address Pointer Low Byte Register 3. RAMTXDATA: RAM Transmit Buffer Data Register Register 4. RAMRXDATA: RAM Receive Buffer Data Register Bits7–0: RAMADDRH: RAM A ddress Register High Byte Holds the most significant eight bits of the target RAM address. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x08 Bits7–0: RAMADDRL: RAM Address Register Low Byte Holds the least significant eight bits of the target RAM address. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x09 Bits7–0: RAMTXDATA: Transmit Buffer Data Register Read: Returns data in the transmit buffer at location RAMADDRH:RAMADDRL. Write: Writes data to the transmit buffer at location RAMADDRH:RAMADDRL. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x04 Bits7–0: RAMRXDATA: Receive Buffer Data Register Read: Returns data in the receive buffer at location RAMADDRH:RAMADDRL. Write: Writes data to the receive buffer at location RAMADDRH:RAMADDRL. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x02

descriptions for each group. Table 11 lists all direct registers available on the device. Table 10. CP2200/1 Register Groups Table 11. Direct Registers Register Address Description Page No.

Register Address Description Page No.

Register Address Description Page No.

Register Address Description Page No.

Register Address Description Page No.

INT1. Interrupts can be disabled by clearing the corresponding bits in INT0EN and INT1EN. of checking for interrupts without clearing the interrupt status registers. Table 12. Interrupt Source Events receive buffer using the AutoRead interface. Self Initialization Complete Th e device is ready for Reset Initialization. See “6.2. Reset Initialization” on page 18. status register to determine the receive buffer status. check for a valid link and re-try auto-negotiation. one that completes without failure.

Rev. 1.0 31 Register 5. INT0: Interrupt Status Register 0 (Self-Clearing) Note: Reading this register will clear all INT0 interrupt flags. Bit 7: EOPINT: End of Packet Interrupt Flag 0: The last byte of a packet has not been read since the last time EOPINT was cleared. 1: The last byte of a packet has been read. Bit 6: RXEINT: Receive FIFO Empty Interrupt Flag 0: The receive FIFO has not been empty since the last time RXEINT was cleared. 1: The receive FIFO is empty. Bit 5: SELFINT: Self Initializat ion Complete Interrupt Flag 0: Self Initialization has not completed since the last time SELFINT was cleared. 1: Self Initialization has completed. Bit 4: OSCINT: Oscillator Initializ ation Complete Interrupt Flag 0: Oscillator Initialization has not completed since the last time OSCINT was cleared. 1: Oscillator Initialization has completed. Bit 3: FLWEINT: Flash Write/Erase Operation Complete Interrupt Flag 0: A Flash write or erase operation has not completed since the last time FLWEINT was cleared. 1: A Flash write or erase operation has completed. Bit 2: TXINT: Packet Transmitted Interrupt Flag 0: A packet transmission has not completed since the last time TXINT was cleared. 1: A packet has been transmitted. Bit 1: RXFINT: Receive FIFO Full Interrupt Flag 0: The receive FIFO has not been full since the last time RXFINT was cleared. 1: The receive FIFO is full. Bit 0: RXINT: Packet Received Interrupt Flag 0: A packet has not been added to the receive buffer since the last time RXINT was cleared. 1: A packet has been added to the receive buffer. RC RC RC RC RC RC RC RC Reset Value EOPINT RXEINT SELFINT OSCINT FLWEINT TXINT RXFINT RXINT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x63

32 Rev. 1.0 Register 6. INT0RD: Interrupt Status Register 0 (Read-Only) Note: Reading this register will not clear INT0 interrupt flags. Bit 7: EOPINTR: End of Packet Read-Only Interrupt Flag 0: The last byte of a packet has not been read since the last time EOPIF was cleared. 1: The last byte of a packet has been read. Bit 6: RXEINTR: Receive FIFO Empty Read-Only Interrupt Flag 0: The receive FIFO has not been empty since the last time RXFIFOE was cleared. 1: The receive FIFO is empty. Bit 5: SELFINTR: Self In itialization Complete Read-Only Interrupt Flag 0: Self Initialization has not completed since the last time SELFINT was cleared. 1: Self Initialization has completed. Bit 4: OSCINTR: Oscillator Initialization Complete Read-Only Interrupt Flag 0: Oscillator Initialization has not completed since the last time OSCINT was cleared. 1: Oscillator Initialization has completed. Bit 3: FLWEINTR: Flash Write/Erase Operation Complete Read-Only Interrupt Flag 0: A Flash write or erase operation has not completed since the last time FLWEINT was cleared. 1: A Flash write or erase operation has completed. Bit 2: TXINTR: Packet Transmitted Read-Only Interrupt Flag 0: A packet transmission has not completed since the last time TXINT was cleared. 1: A packet has been transmitted. Bit 1: RXFINTR: Receive FIFO Full Read-Only Interrupt Flag 0: The receive FIFO has not been full since the last time RXFINT was cleared. 1: The receive FIFO is full. Bit 0: RXINTR: Packet Receiv ed Read-Only Interrupt Flag 0: A packet has not been added to the receive buffer since the last time RXINT was cleared. 1: A packet has been added to the receive buffer. R RRRRR R R R e s e t V a l u e EOPINTR RXEINTR SELFINTR OSCINTR FLWE INTR TXINTR RXFINTR RXINTR 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x76

Rev. 1.0 33 Register 7. INT0EN: Interrupt Enable Register 0 Bit 7: EEOPINT: Enable End of Packet Interrupt 0: Disable End of Packet Interrupt. 1: Enable End of Packet Interrupt. Bit 6: ERXEINT: Enable Rece ive FIFO Empty Interrupt 0: Disable Receive FIFO Empty Interrupt. 1: Enable Receive FIFO Empty Interrupt. Bit 5: ESELFINT: Enable Self Init ialization Complete Interrupt 0: Disable Self Initialization Complete Interrupt. 1: Enable Self Initialization Complete Interrupt. Bit 4: EOSCINT: Enable Oscillator In itialization Complete Interrupt 0: Disable Oscillator Initialization Complete Interrupt. 1: Enable Oscillator Initialization Complete Interrupt. Bit 3: EFLWEINT: Enable Flash Write/Erase Operation Complete Interrupt 0: Disable Flash Write/Erase Operation Complete Interrupt. 1: Enable Flash Write/Erase Operation Complete Interrupt. Bit 2: ETXINT: Enable Packe t Transmitted Interrupt 0: Disable Packet Transmitted Interrupt. 1: Enable Packet Transmitted Interrupt. Bit 1: ERXFINT: Enable Receive FIFO Full Interrupt 0: Disable Receive FIFO Full Interrupt. 1: Enable Receive FIFO Full Interrupt. Bit 0: ERXINT: Enable Pa cket Received Interrupt 0: Disable Packet Received Interrupt. 1: Enable Packet Received Interrupt. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EEOPINT ERXEINT ESELFINT EOSCINT EFLWE INT ETXINT ERXFINT ERXINT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x64

34 Rev. 1.0 Register 8. INT1: Interrupt Status Register 1 (Self-Clearing) Note: Reading this register will clear all INT1 interrupt flags. Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: WAKEINT: “Wake-on- Lan” Interrupt Flag 0: The device has not been connected to a network since the last time WAKEINT was cleared. 1: The device has been connected to a network since the last time WAKEINT was cleared. Bit 4: LINKINT: Link Status Changed Interrupt Flag 0: The link status has not changed since the last time LINKINT was cleared. 1: The link status has changed (device has been connected or removed from a network). Bit 3: JABINT: Jabber Detected Interrupt Flag 0: A jabber condition has not been detected since the last time JABINT was cleared. 1: A jabber condition has been detected. Bit 2: ANFINT: Auto-Negotiation Failed Interrupt Flag 0: Auto-Negotiation has not failed since the last time ANFINT was cleared. 1: Auto-Negotiation has failed. Bit 1: Reserved: Read = 0. Bit 0: ANCINT: Auto-Negotiat ion Complete Interrupt 0: Auto-Negotiation has not completed since the last time ANCINT was cleared. 1: Auto-Negotiation has completed. R/W R/W RC RC RC RC RC RC Reset Value — — WAKEINT LINKINT JABINT Reserved RFINT ANCINT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x7F

Rev. 1.0 35 Register 9. INT1RD: Interrupt Status Register 1 (Read-Only) Note: Reading this register will not clear INT1 interrupt flags. Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: WAKEINTR: “Wake-on-Lan” Read-Only Interrupt Flag 0: The device has not been connected to a network since the last time WAKEINT was cleared. 1: The device has been connected to a network since the last time WAKEINT was cleared. Bit 4: LINKINTR: Link Status Changed Read-Only Interrupt Flag 0: The link status has not changed since the last time LINKINT was cleared. 1: The link status has changed (device has been connected or removed from a network). Bit 3: JABINTR: Jabber Detected Read-Only Interrupt Flag 0: A jabber condition has not been detected since the last time JABINT was cleared. 1: A jabber condition has been detected. Bit 2: ANFINTR: Auto-Negotiation Failed Read-Only Interrupt Flag 0: Auto-Negotiation has not failed since the last time ANFINT was cleared. 1: Auto-Negotiation has failed. Bit 1: Reserved: Read = 0b. Bit 0: ANCINTR: Auto-Neg otiation Complete Read-Only Interrupt Flag 0: Auto-Negotiation has not completed since the last time ANCINT was cleared. 1: Auto-Negotiation has completed. R / W R / W R RRRRR R e s e t V a l u e — — WAKEINTR LINKINTR JABINTR ANFIN TR Reserved ANCINTR 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x7E

36 Rev. 1.0 Register 10. INT1EN: Interrupt Enable Register 1 Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: EWAKEINT: Enable “Wake-on-Lan” Interrupt 0: Disable “Wake-on-Lan” Interrupt. 1: Enable “Wake-on-Lan” Interrupt. Bit 4: ELINKINT: Enable Link Status Changed Interrupt 0: Disable Link Status Changed Interrupt. 1: Enable Link Status Changed Interrupt. Bit 3: EJABINT: Enable Jab ber Detected Interrupt 0: Disable Jabber Detected Interrupt. 1: Enable Jabber Detected Interrupt. Bit 2: EANFINT: Enable Auto-Negotiation Failed Interrupt 0: Disable Auto-Negotiation Failed Interrupt. 1: Enable Auto-Negotiation Failed Interrupt. Bit 1: Reserved: Read = 0b. Must write 0b. Bit 0: EANCINT: Enable Auto-Nego tiation Complete Interrupt 0: Disable Auto-Negotiation Complete Interrupt. 1: Enable Auto-Negotiation Complete Interrupt. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value — — EWAKEINT ELINKINT EJABINT EAN FINT Reserved EANCINT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x7D

Rev. 1.0 37 9. Reset Sources Reset circuitry allows the CP2200/1 to be easily placed in a predefined default condition. Upon entry to this reset state, the following events occur: „ All direct and indirect registers are initialized to their defined reset values. „ Digital pins (except /RST) are forced into a high impedance state with a weak pull-up to VDD. „ Analog pins (TX+/TX–, RX+/RX–) are forced into a high impedance state without a weak pull-up. „ The external oscillator is stopped and /RST driven low (except on a software reset). „ All interrupts are enabled. The contents of the transmit and receive buffers are unaf fected by a reset as long as the device has maintained sufficient supply voltage. However, since the buffer pointers are reset to their default values, the data is effectively lost unless the host processor has kept track of the starting address and length of each packet in the buffer. The CP2200/1 has five reset sources that place the device in the reset state. The method of entry to the reset state determines the amount of time spent in reset and the behavior of the /RST pin. Each of the following reset sources is described in the following sections: „ Power-On „ Power-Fail „ Oscillator-Fail „ External /RST Pin „ Software Command Upon exit from the reset state, the device automatically starts the external oscillator and waits fo r it to settle (this step is skipped on software reset). Once the crystal oscillator settles, the Oscillator Initialization Complete interrupt occurs (interrupt pin asserted), and the host processor may now access the internal registers to poll for the Self Initialization Complete Interrupt. If the host does not have acce ss to the interrupt signal, it should wait approximately 1 ms after the risi ng edge of reset pin prior to polling the internal register s. Note that the reset pin could remain low up to 100 ms depending on the power supply ramp time. The device is fully functional after the Self Initialization has completed. See “6.2. Reset Initialization” on page 18 for the recommended initialization procedure following a device reset.

Figure 14. Reset Timing

Rev. 1.0 39 9.2. Power-fail When a power-down transition or power irregularity causes V DD to drop below VRST, the power supply monitor will drive the /RST pin low and return the CP2200/1 to the reset state. When V DD returns to a level above V RST, the CP2200/1 will be released from the reset state as shown in Figure 14. The power supply monitor circuit (V DD Monitor) is enabled and selected as a reset source by hardware following every power-on reset. To prevent the device from being held in reset when VDD drops below VRST, the VDD Monitor may be deselected as a reset source (see RSTEN on page 42) and disabled (see VDMCN on page 39). It is recommended to leave the V DD Monitor enabled and selected as a reset source at all times. Register 11. VDMCN: VDD Monitor Control Register 9.3. Oscillator-Fail Reset If the system clock derived from the oscillator fails for any reason after oscillator initialization is complete, the reset circuitry will drive the /RST pin low an d return the CP2200/1 to the reset state. The CP 2200/1 will remain in the reset state for approximately 1 ms then exit the reset state in the same manner as that for the power-on reset. 9.4. External Pin Reset The external /RST pin provides a means for external circuitry to force the CP2200/1 into a reset state. Asserting the /RST pin low will cause the CP2200/1 to enter the reset state. It is recomme nded to provide an external pull-up and/or decoupling capacitor of the /RST pin to avoid er roneous noise-induced resets . The CP2200/1 will exit the reset state approximately 4 µs after a logic high is detected on /RST. Bit 7: VDMEN: V DD Monitor Enable This bit can be used to disable or enable the VDD Monitor Circuit. Note: The VDD Monitor circuit is enabled and selected as a reset source following every power-on reset. If the VDD Monitor is disabled and then reenabled during device operation, it must be allowed to stabilize before it is selected as a reset source. Selecting the VDD Monitor as a reset source before it has stabilized will generate a system reset. See Table 13 on page 42 for the minimum VDD Monitor turn-on time. 0: VDD Monitor Disabled. 1: VDD Monitor Enabled. Bit6: VDDSTAT: V DD Status This bit indicates the current power supply status (VDD Monitor output). 0: VDD voltage is at or below the VDD Monitor threshold. 1: VDD voltage is above the VDD Monitor threshold. Bits 5–0: RESERVED. Read = varies; Write = don’t care. R / W R / W RRRRRR R e s e t V a l u e VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x13

40 Rev. 1.0 9.5. Software Reset The software reset provides the host CPU the ability to reset the CP2200/1 through the parallel host interface. Writing a ‘1’ to RESET (SWRST.2) will force the device to enter the reset state with the exception that the external oscillator will not be stopped. As soon as the device enters the reset stat e, it will immediately exit the reset state and start device calibration; the Osc illator Initialization Comp lete interrupt is not be generated. After Self Initialization is complete, the device is fully functional. Note: The software reset is enabled after every reset; however, it may be de-selected as a rese t source (see the register description for RSTEN on page 42). Register 12. SWRST: Software Reset Register Bits 7–3: UNUSED. Read = 00000b, Write = don’t care. Bit 2: RESET: Software Reset Initiate Writing a ‘1’ to this bit will generate a software reset. Bits 1–0: UNUSED. Read = 00b, Write = don’t care. R\\W R\\W R/W R/W R/W W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x75

Rev. 1.0 41 9.6. Determining the Source of the Last Reset The RSTSTA register can be used to determine the cause of the last reset. Note: If the PORSI bit is set to logic 1, all other bits in RSTSTA are undefin ed. It is impossible to differentiate between a power-on, power-fail, and oscillator-fail reset by reading the RSTSTA register. Register 13. RSTSTA: Reset Source Status Register Bits 7–3: UNUSED. Read = 00000b, Write = don’t care. Bit 2: SWRSI: Software Reset Indicator 0: Source of last reset was not a write to RESET (SWRESET.2). 1: Source of last reset was a write to RESET (SWRESET.2). Bit 1: PORSI: Power-On / Power-Fail / Oscillator-Fail Reset Indicator 0: Source of last reset was not a power-on, power-fail, or oscillator-fail event. 1: Source of last reset was a power-on, power-fail, or oscillator-fail event. Bit 0: PINRSI: External Pin Reset Indicator 0: Source of last reset was not the /RST pin. 1: Source of last reset was the /RST pin. R/W R/W R/W R/W R/W R R R Reset Value — — — — — SWRSI PORSI PINRSI 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x73

of these two reset sources from generating a device reset. Table 13. Reset Electrical Characteristics VDD = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified. Bits 7–3: UNUSED. Read = 00000b, Write = don’t care. 0: Software reset is not selected as a reset source. 1: Software reset is selected as a reset source. DD Monitor) is not selected as a reset source. 1: The power fail detection circuitry (VDD Monitor) is selected as a reset source. Bit 0: UNUSED. Read = 0b, Write = don’t care.

Figure 15. Power and Clock Distribution Control

44 Rev. 1.0 10.1. Normal Mode Normal Mode should is used whenever the host is sending or receiving pa ckets. In this mode, the CP2200/01 is fully functional. Typical Normal Mode power consumption is listed in Table 2 on page 9. Note: When in normal mode, the transmitter has a power saving mode which is enabled on reset. This power saving mode dis- ables the transmitter's output driver an d placed the TX+/- pins in high impedance when the CP220x is not transmitting link pulses or data. To meet the minimum transmitter loss requirements in IEEE 802.3, this power saving mode should be disabled. See Register 17, “TXPWR: Transmitter Power Register,” on page 46 for details. 10.2. Link Detection Mode In Link Detection Mode, the transmitter and link pulse generation logic is disabled. The CP2200/1 will appear to be “offline” because link pulses will not be generated. The most common way to use Link Detection Mode is enabling the Wake-on-LAN interrupt, placing the CP2200/01 into Link Detection Mode, then placing the MCU in a low power mode until the system is plugged into a network. Note: When using link detection mode, the user should ensure that the link partner is always transmitting link pulses. An exam- ple of this type of device would be a hub or a switch. Some notebook PCs implement a power saving feature in which they stop transmitting link pulses if a valid link is not detected. This would create a situation where both link partners are waiting for each other to start transmitting link pulses. Note: A minimum transmitter return lo ss is specified in IEEE 802.3. If the transmitter is disabled, the TX± pins are placed in high impedance mode and do not create the minimum return loss. The transmitter should not be disabled if the device is considered "on a network" and valid link pulses are being received. From Normal Mode, the device can be placed in Link Detection Mode by clearing TXEN (PHYCN.6) to “0”. To return the device to Normal Mode, di sable the physical layer by clearin g PHYCN to 0x00, then re-enable the physical layer using the startup procedure in Section 15.7 on page 90. 10.3. Memory Mode In Memory Mode, the physical layer (receiver and transmi tter) is placed in a low-power state, and the CP2200/1 can neither send nor receive packets. The only primary functions of the device that remain functional are the Flash memory and RAM buffers. The RAM buffers are only accessible using the Random Access method described in Section 7.1 on page 23. The device can be placed in Memory Mode by clearing the three most significant bits of the PHYCN register to ‘000’. The device can be returned to normal mode by setting the three most significant bits of the PHYCN register to ‘111’ and waiting the appropriate physical layer turn-on times for both the transmitter and the receiver. The physical layer electrical characterist ics including turn-on time are specified in Table 22 on page 93. To return the device to Normal Mode, disable the physical layer by clearing PHYCN to 0x00, then re-enable the physical layer using the startup procedure in Section 15.7 on page 90. 10.4. Shutdown Mode Shutdown Mode is the lowest power mode for the CP2200/ 1. All primary and secondary functions are disabled, and the system clock is disconnected from the oscillato r. The device can recover from Shutdown Mode only through a power-on or pin reset. The device can be placed in Shutdown Mode using the following procedure: Step 1: Disable the PHY by clearing the three most significant bits of PHYCN to ‘000’. Step 2: Disable the LED drivers by clearing bits 2 and 3 of IOPWR to ‘00’. Step 3: Disable the VDD Monitor (optional) by clearing VDMEN (VDMCN.7) to ‘0’. Step 4: Disconnect the oscillator output from the rest of the device by clearing OSCOE (OSCPWR.0) to ‘0’. This step should be performed last because the device will no longer respond until the next pin or power-on reset.

Rev. 1.0 45 10.5. Disabling Secondary Device Functions The LED Drivers, weak pull-ups, and V DD Monitor can be disabled to minimi ze power consumption. The typical supply current for the VDD Monitor is specified in Table 13 on page 42. Disabling weak pull-ups will save current if the MOTEN and MUXEN pins are tied to ground, but w ill cause the address and data pins to float (causing undefined device behavior and increased power consumption) if they are not externally driven or pulled to a defined logic level using pull-up or pull-down resistors. The internal weak pull-ups should not be disabled unless all digital pins are externally driven to a logic high or logic low state. Register 15. IOPWR: Port Input/Output Power Register Bits 7–4: UNUSED. Read = 0000b, Write = don’t care. Bit 3 ACTEN: Activity LED Enable 0: Activity LED disabled. 1: Activity LED enabled. Bit 2 LINKEN: Link LED Enable (Link/Activity LED on CP2201) 0: Link (Link/Activity) LED disabled. 1: Link (Link/Activity) LED enabled. Bit 1: WEAKD: Weak Pull-up Disable 0: Weak pull-ups are enabled. 1: Weak pull-ups are disabled. Bit 0: Reserved. Read = 0b; Must write 0b. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value — — — — ACTEN LINKEN WEAKD Reserved 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x70

46 Rev. 1.0 Register 16. OSCPWR: Oscillator Power Register Register 17. TXPWR: Transmitter Power Register Bits 7–5: UNUSED. Read = 0000b, Write = don’t care. Bit 4–2: RESERVED. Read = 1 00b; Must write x00b. Bit 1: UNUSED. Read = 1b; Write = don’t care. Bit 0: OSCOE: Oscilla tor Output Enable This bit controls the output of the external oscillator. It does not affect the external crystal driver. 0: Oscillator output disabled. The device will no longer respond until the next reset. 1: Oscillator output enabled. R/W R/W R/W R/W R/W R/W R R/W Reset Value — — — Reserved Reserved Reserved Reserved OSCOE 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x7C Bit 7: PSAVED. Transmitter Powe r Save Mode Disable Bit 0: Enable transmitter power saving mode. 1: Disable transmitter power saving mode. Bits 6–0: Reserved. Read = varies; Must write 0000000b. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PSAVED Reserved Reserved Reserved Reserved Reserved Reserved Reserved 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x7A

generated. Figure 16 shows a typical Ethernet packet. Figure 16. Typical Ethernet Packet

48 Rev. 1.0 11.2. Transmitting a Packet Once reset initialization is complete (See ), the CP2200/1 is ready to transmit Ethernet packets. The following procedure can be used to transmit a packet: Step 1: Wait for the previous packet to complete (TXBUSY == 0x00). The worst case time to transmit a packet is 500 ms in half-duplex mode with exponential backoff. Step 2: Set the TXSTARTH:TXSTARTL transmit buffer pointer to 0x0000. Step 3: If the last packet was aborted ((TXSTA3 & 0xF8) != 0x00), then this packet must be loaded into the transmit buffer using the Random Memory Access Method: a. Set RAMADDRH:RAMADDRL to 0x0000. b. Write the first data byte to RAMTXDATA. c. Increment RAMADDRH:RAMADDRL. d. Write another data byte to RAMTXDATA. e. Repeat steps c and d until the entire packet is loaded. f. Pad small packets to at least 64 bytes. g. Set TXENDH:TXENDL to the address of the last byte added. This value must be greater than or equal to 0x0040. Step 4: If the last packet was successfully transmitted ((TXSTA2 & 0x80) == 0x80), then this packet may be loaded into the transmit buffer using the AutoWrite Interface: a. Write all data bytes to the TXAUTOWR register, one byte at time. b. If the MAC is in half-duplex mode, pad small packets to at least 64 bytes. Step 5: Set the TXSTARTH:TXSTARTL transmit buffer pointer back to 0x0000. Step 6: Write a ‘1’ to the TXGO bit (TXCN.0) to begin transmission. Note: Step 4 may be skipped if Step 3 is always performed. 11.3. Overriding Transmit Configuration Options The global transmit configuration options are set in the MAC registers. The transmit interface allows the host processor to customize packet transmission on a per-packe t basis by overriding the global MAC settings. The following options can be overridden by the transmit interface: „ Short Frame Padding—When enabled, ensures that no fram e smaller than 64 bytes is transmitted. The frame size does not include the 8 byte preamble; however, the 4-byte CRC field is included. „ CRC Generation—When en abled, a 32-bit CRC will be calculated and appended to the Ethernet frame. „ Pause packet transmission (Full Duplex Mode)—When en abled, an Ethernet PAUSE packet with a pause value of TXPAUSEH:TXPAUSEL is transmitted. The pause value is in units of 512 bit times (51.2 µs). „ Application of Back Pressure (Half Duplex Mode). „ Switching between Half/Full Duplex Modes. Note: This setting does not affect the physical layer. 11.4. Transmit Buffer and AutoWrite Interface The transmit buffer provides the AutoWrite interface to efficiently load the buffer with an entire packet. The interface consists of three registers: TXSTART, TXEND, and T XAUTOWR. The TXSTART register points to the address of the next available byte and can be rese t to the first byte of the buffer. TXEND points to the last byte added to the buffer. TXAUTOWR is the data register. Each write to TXAUTOWR sets TXEND to the address of the byte written and increments TXSTART. After the packet is loaded into the buffer, TXSTART is reset to 0x0000 to mark the starting point of the packet. TXEND will continue to point to the last byte in the packet. Note: The AutoWrite Interface cannot be used following an aborte d packet. This only applies if the device is in half-duplex mode.

accessible through the TXSTA0 — TXSTA6 registers. The transmit status vector is described in Table 15. Table 14. Transmit Status and Control Register Summary 0x00 when transmit interface is not transmitting. buffer. This register is managed by hardware. byte, and increment TXSTART.

Table 15. Transmit Status Vector Description

51 Transmitted VLAN Frame Last frame transmit ted had length/type field of 0x8100 (VLAN

50 Back Pressure Applied Back pressure was applied during transmission. 49 Transmitted PAUSE Frame Last frame transmitted was a valid PAUSE control frame. 48 Transmitted Control Frame Last frame transmitted was a control frame. 31 Transmit Under-Run Last packet was aborted due to a data under-run condition.

30 Jumbo Packet Detected Last packet was aborted due to the detection of a Jumbo

packet (oversized frame). Jumbo packets are not supported.

29 Late Collision Detected Last packet was abor ted due to a collision occurring after the

28 Excessive Collisions Detected Last packet was a borted due to detection of 16 or more colli-

27 Excessive Delay Detected Aborted due to a delay longer than 2.42ms. 25 Transmitted Broadcast Packet Last packet tran smitted had a broadcast destination address. 24 Transmitted Multicast Packet Last packet tran smitted had a multicast destination address. 23 Transmit Successful Last packe t was successfully transmitted. 22 Type Field Detected Last packet’s length/t ype field had a value greater than 1500.

21 Length Check Error Last packet’s length/type field had a value less than or equal

to 1500 which did not match the actual frame length.

20 CRC Error Last packet’s CRC field did not match the internally generated

15-0 Transmit Byte Count Numbe r of bytes in last frame not counting collided bytes.

Rev. 1.0 51 Register 18. TXCN: Transmit Control Register Register 19. TXBUSY: Transmit Busy Indicator Bit 7: OVRRIDE: Default Override 0: Settings for bits 5, 4, 3, 2, and 1 in TXCN will be ignored. MAC settings will take effect. 1: Settings for bits 5, 4, 3, 2, and 1 in TXCN will be applied. MAC settings will be overridden. Bit 6: UNUSED. Read = 0b, Write = don’t care. Bit 5: CRCENOV: CRC Enable 0: Disable CRC append on transmission. 1: Enable CRC append on transmission. Bit 4: PADENOV: Pad Enable 0: Disable padding of short frames. 1: Enable padding of short frames. Bit 3: TXPPKT: Transmit a PAUSE control packet 0: Normal packet transmission. Packet data will be obtained from the transmit buffer. 1: A PAUSE control packet with the value of TXPAUSEH:TXPAUSEL will be transmitted. Data in the transmit buffer will not be accessed. PAUSE control packets are only valid in full-duplex mode. Bit 2: BCKPRES: Apply Back Pressure 0: Normal packet transmission. Back pressure will not be applied. 1: Back pressure will be applied on transmission (only valid in half duplex mode). Bit 1: FDPLXOV: Full Duplex Operation Note: The transmit interface, MAC, and physical layer must be configured to the same duplex mode. 0: Transmit interface operates in half duplex mode. 1: Transmit interface operates in full duplex mode. Bit 0: TXGO: Transmit Packet Set this bit to ‘1’ to begin transmission of a packet. Note: TXGO should not be set to one if both TXSTART and TXEND are zero (i.e., no data has been added to the buffer). R/W R/W R/W R/W R/W R/W R/W W Reset Value OVRRIDE — CRCENOV PADENOV TXPPKT BCKPRES FDPLXOV TXGO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x53 Bits 7–1: UNUSED. Read = 0000000b, Write = don’t care. Bit 0: TXBUSY: Packet Transmit Status 0: Packet Transmit is not in progress. 1: Packet Transmit is in progress. RRRRRRRR R e s e t V a l u e Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x54

52 Rev. 1.0 Register 20. TXPAUSEH: Transmit Pause High Byte Register 21. TXPAUSEL: Transmit Pause Low Byte Register 22. TXSTARTH: Transmit Data Starting Address High Byte Register 23. TXSTARTL: Transmit Data Starting Address Low Byte Bits 7–0: TXPAUSEH: Transmit Pause High Byte High byte of the 16-bit pause value sent in a PAUSE control packet. The pause value is in units of 512 bit times (512 bit times = 51.2 µs). R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x55 Bits 7–0: TXPAUSEL: Transmit Pause Low Byte Low byte of the 16-bit pause value sent in a PAUSE control packet. The pause value is in units of 512 bit times (512 bit times = 51.2 µs). R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x56 Bits 7–0: TXSTARTH: Transmit Data Starting Address High Byte High byte of the starting address of outgoing packet in the transmit buffer. Note: Outgoing packets must start at 0x0000. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x59 Bits 7–0: TXSTARTL: Transmit Da ta Starting Address Low Byte Low byte of the starting address of outgoing packet in the transmit buffer. Note: Outgoing packets must start at 0x0000. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x5A

Rev. 1.0 53 Register 24. TXENDH: Transmit Data Ending Address High Byte Register 25. TXENDL: Transmit Data Ending Address Low Byte Register 26. TXAUTOWR: Transmit Data AutoWrite Bits 7–0: TXENDH: Transmit Data Ending Address High Byte High byte of the address of the last byte added to the transmit buffer. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x57 Bits 7–0: TXENDL: Transmit Data Ending Address Low Byte Low byte of the address of the last byte added to the transmit buffer. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x58 Bits 7–0: TXSTARTL: Transmit Da ta Starting Address Low Byte Writes to this register add a single byte to the transmit buffer and set the TXEND pointer to the address of the byte currently being written. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x03

54 Rev. 1.0 Register 27. TXSTA6: Transmit Status Vector 6 Register 28. TXSTA5: Transmit Status Vector 5 Note: This register contains bits 51–48 of the Transmit Status Vector. Bits 7–4: UNUSED. Read = 0000b, Write = don’t care. Bit 3. TXVLAN: Transmitted VLAN Frame 0: Transmitted frame had length/type field of 0x8100. 1: Transmitted frame did not have a length/type field of 0x8100. Bit 2: BCKPRES: Back Pressure Applied 0: Back pressure was not applied during transmission. 1: Back pressure was applied during transmission. Bit 1: TXPF: Transmitted PAUSE Frame 0: Transmitted frame was not a PAUSE control frame. 1: Transmitted frame was a valid PAUSE control frame. Bit 0: TXCF: Transmitted Control Frame 0: Transmitted frame was not a control frame. 1: Transmitted frame was a control frame. R/W R/W R/W R/W R R R R Reset Value — — — — TXVLAN BCKPRES TXPF TXCF 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x5C Note: This register contains bits 47–40 of the Transmit Status Vector. Bits 7–0: TXSTA5: Total Bytes Transmitted High Byte The most significant 8-bits of the total number of bytes transmitted on the wire, including all bytes from collided attempts. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x5D

Rev. 1.0 55 Register 29. TXSTA4: Transmit Status Vector 4 Register 30. TXSTA3: Transmit Status Vector 3 Note: This register contains bits 40-32 of the Transmit Status Vector. Bits 7-0: TXSTA4: Total Bytes Transmitted Low Byte The least significant 8-bits of the total number of bytes transmitted on the wire, including all bytes from collided attempts. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x5E Note: This register contains bits 31–24 of the Transmit Status Vector. Bit 7: TXURUN: Transmit Under-Run 0: Transmit under-run did not occur. 1: Packet aborted due to data under-run condition. Bit 6: TXJUMBO: Jumbo Packet Detected 0: Transmitted packet was not oversized. 1: Packet aborted due to its excessive size. Bit 5: TXLTCL: Late Collision Detected 0: Late collision was not detected. 1: Packet aborted due to the detection of a collision after the 51.2 us collision window. Bit 4: TXEXCL: Excessive Collisions Detected 0: Number of collisions on transmission was less than 16. 1: Packet aborted due to detection of 16 or more collisions. Bit 3: TXEXDE: Excessive Delay Detected 0: Packet was transmitted without an excessive delay (greater than 2.42 ms). Please check other flags for information. 1: Packet was aborted due to an excessive delay (greater than 2.42 ms). Bit 2: TXDE: Delay Detected 0: Packet was transmitted with no delay or was aborted. Please check other flags for information. 1: Packet was transmitted, but had some delay (less than 2.4 ms). Bit 1: TXBCAST: Transmitted Broadcast Packet 0: Transmitted packet did not have a broadcast destination address. 1: Transmitted packet had a broadcast destination address. Bit 0: TXMCAST: Transmitted Multicast Packet 0: Transmitted packet did not have a multicast destination address. 1: Transmit packet had a multicast destination address. RRRRRRRR R e s e t V a l u e TXURUN TXJUMBO TXLTCL TXEXCL TXEXDE TXDE TXBCAST TXMCAST 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x5F

56 Rev. 1.0 Register 31. TXSTA2: Transmit Status Vector 2 Register 32. TXSTA1: Transmit Status Vector 1 Note: This register contains bits 23–16 of the Transmit Status Vector. Bit 7: TXOK: Transmit Successful 0: Transmission was aborted. 1: Transmission was successful. Bit 6: TXLOOR: Type Field Detected 0: Last packet’s type/length field was used as a length. 1: Last packet’s type/length field was used as a type. Bit 5: TXLCERR: Length Check Error 0: Last packet’s length field matched the actual frame length. 1: Last packet’s length field did not match the actual frame length. Bit 4: TXCRCER: CRC Error 0: Last packet’s CRC matched the internally generated CRC. 1: Last packet’s CRC did not match the internally generated CRC. Bits 3–0: TXCOL3-0: Tr ansmit Collision Count Number of collisions encountered during transmission of the last packet. Note: This bit field does not overflow and will remain at 1111b (15 collisions) if 15 or more collisions are encountered. RRRRRRRR R e s e t V a l u e TXOK TXTYPE TXLCERR TXCRCER TXCOL3 TXCOL2 TXCOL1 TXCOL0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x60 Note: This register contains bits 15–8 of the Transmit Status Vector. Bits 7–0: TXSTA1: Transmit Byte Count High Byte The most significant 8-bits of the number of bytes in the last transmitted frame. Does not include bytes transmitted due to collided attempts. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x61

Rev. 1.0 57 Register 33. TXSTA0: Transmit Status Vector 0 Note: This register contains bits 15–8 of the Transmit Status Vector. Bits 7–0: TXSTA0: Transmit Byte Count Low Byte The least significant 8-bits of the number of bytes in the last transmitted frame. Does not include bytes transmitted due to collided attempts. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x62

overwritten as new packets arrive. determine whether or not to copy the packet. Figure 17. Receive Interface Block Diagram access method described in Section 7.1 on page 23 can be used to access the buffer. Step 2: If RXVALID or RXOK is 0, or to skip the packet, write a ‘1’ to RXSKIP (RXCN.1). If RXVALID and RXOK are 1, read the length of the current packet from CPLENH:CPLENL. Step 3: Read the entire packet, one byte at a time, by reading RXAUTORD. Step 4: If the entire packet was read, write a ‘1’ to RXCLRV (RXCN.2). If there are any unread bytes remaining in the current buffer, write a ‘1’ to RXSKIP (RXCN.1). to retrieve data from the receive buffer. The random access method described in Section 7.1 on page 23.

Rev. 1.0 59 Note: The value of CPADDRH:CPADDRL may be invalid if an overflow event occurs. After an overflow, the FIFOHEADH:FIFO- HEADL pointer should be used to determine the starting address of the current packet. CPLEN will always remain valid even after an overflow event. Note: If the Receive FIFO Full Interr upt is triggered, the interrupt flag must be cleared to re-enable packet reception. The Receive FIFO Full Interrupt is triggered based on the size of packets or on the number of packets. If triggered based on the number of packets, then pointer corruption has occurred. 12.4. Initializing the Receive Buffer, Filter and Hash Table After a device reset, the receive buffer is empty and the filter is configured to accept broadcast packets and multicast packets matching a hash value of 0x0400. Th is hash value allows PAUSE control packets to pass through the receive filter. The receive buffer does not require any additional initializat ion. The receive filter can be configured to accept or ignore broadcast packets, multicast packets, runt pack ets (Ethernet Frame smaller than 64 bytes), and packets with a CRC error. The receive filter is configured using the RXFILT register. The device can be configured to accept broadcast packets and packets addressed to the controller’s MAC address without using the hash table. If multicast packets need to be accepted, then the hash table can be programmed to accept packets addressed to specific address ranges. The CP2200/1 implements a 16-bit hash table to represent all possible addresses in the 64-bit address space. Each of the possible 65536 possible values for the hash table represent a range of MAC addresses. If all 16 bits are set to ‘1’, all multicast addresses will be accepted. If all 16-bits are set to ‘0’, then all multicast addresses will be rejected.The following procedure can be used to determine which bits to set for a specific address: Step 1: Perform a 32-bit CRC on the 6-bytes of the address using 0xC704DD7B as the polynomial. Step 2: Record the least significant 4 bits of the CRC result (Hash Index). Step 3: The Hash Index determines the bit that should be set in the hash table that will allow the address to be received. For example, if the least significant 4-bits of the CRC result are 101b (5d), then setting bit 5 of the 16-bit hash table will allow all MAC addresses whose CRC result is 5d to be accepted.

Table 16. Receive Status and Control Register Summary sequentially from the receive buffer. 16-bit Hash Table used to filter multicast packets. broadcast/multicast, CRC errors, etc.

Rev. 1.0 61 Register 34. RXCN: Receive Interface Control Register 35. RXSTA: Receive Interface Status Bits 7–4: UNUSED. Read = 0000b, Write = don’t care. Bit 3: RXINH: Receive Inhibit Setting this bit to ‘1’ temporarily inhibits new packet reception. If a packet is currently being received, reception will continue until the packet is received. Once set, this bit must be cleared to ‘0’ by software to resume packet reception. Bit 2: RXCLRV: Valid Bit Clear Writing a ‘1’ to this bit clears the valid bit of the current packet, freeing up the buffer for new packets. This action should only be started after all bytes of the current packet have been read (CPEND = 1). If the packet is not completely read, RXSKIP should be used to discard the remaining bytes. Bit 1: RXSKIP: Skip Current Packet Writing a ‘1’ to this bit updates discards the current packet by clearing its valid bit and advances the AutoRead buffer pointer to the beginning of the next packet. Bit 0: RXCLEAR: Receive Buffer Clear Writing a ‘1’ to this bit discards all packets in the receive buffer and resets all buffer pointers and valid bits to zero. Note: Any packets currently in the buffer will remain in memory, however, all infor- mation such as the starting address and length of each packet will be lost. Any new packets that arrive will overwrite the existing data. R/W R/W R/W R/W R/W W W W Reset Value — — — — RXINH RXCLRV RXSKIP RXCLEAR 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x11 Bits 7–2: UNUSED. Read = 000000b, Write = don’t care. Bit 1: CPEND: Current Packet End Reached This bit is automatically cleared by hardware when the valid bit for the current packet is cleared (see RXCLRV description) or the current packet is discarded (see RXSKIP description). 0: The last byte of the current packet has not been read using the AutoRead interface. 1: The last byte of the current packet has been read using the AutoRead interface. Bit 0: RXBUSY: Receiving Packet 0: Receive interface is idle. 1: Receive interface is currently receiving a packet. R / WR / WR / WR / WR / WR / W R R R e s e t V a l u e — — — — — — CPEND RXBUSY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x12

62 Rev. 1.0 Register 36. RXAUTORD: Receive AutoRead Data Register Register 37. RXFILT: Receive Filter Configuration Register 38. RXHASHH: Multicast Hash Table High Byte Bits 7–0: RXAUTORD: Receive AutoRead Data Register Reads from this register read a single byte from the receive buffer and adjust the receive buffer pointer RXFIFOHEAD accordingly. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x01 Bits 7–4: UNUSED. Read = 0000b, Write = don’t care. Bit 3: IGNRUNT: Ignore Runt Packets 0: Runt packets are not ignored. 1: Runt packets are ignored. Bit 2: IGNERR: Ignore FCS Error Packets 0: Packets with FCS error are not ignored. 1: Packets with FCS error are ignored. Bit 1: IGNBCST: Ignore Broadcast Packets 0: Broadcast packets are not ignored. 1: Broadcast packets are ignored. Bit 0: IGNMCST: Ignore Multicast Packets 0: Multicast packets are not ignored. 1: Multicast packets are ignored. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value — — — — IGNRUNT IGNERR IGNBCST IGNMCST 00001100 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x10 Bits 7–0: RXHASHH: Multicast Hash Table High Byte High Byte of 16-bit multicast hash table. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000100 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x0E

Rev. 1.0 63 Register 39. RXHASHL: Multicast Hash Table Low Byte Register 40. CPINFOH: Current Packet Information High Byte Bits 7–0: RXHASHL: Multicast Hash Table Low Byte Low Byte of 16-bit multicast hash table. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x0F Bit 7: RXVALID: Current packet valid 0: The current packet TLB slot is empty. 1: There is a packet in the current packet TLB slot. Bit 6: RXVLAN: VLAN Type Detected 0: VLAN tagged frame not detected. 1: VLAN tagged frame detected. Bit 5: RXUNSUP: Unsupp orted Control Frame 0: Unsupported control frame not detected. 1: Unsupported control frame detected. Bit 4: RXPCF: Pause Control Frame 0: Pause control frame not detected. 1: Pause control frame detected. Bit 3: RXCF: Control Frame 0: Control frame not detected. 1: Control frame detected. Bit 2: RXADATA: Additional Data Received 0: Normal Operation. 1: 1 to 7 additional bits of data received following receipt of the packet. Bit 1: BCAST: Broadcast Packet 0: Current packet is not a broadcast packet. 1: Current packet is a broadcast packet. Bit 0: MCAST: Multicast Packet 0: Current packet is not a multicast packet. 1: Current packet is a multicast packet. RRRRRRRR R e s e t V a l u e RXVALID RXVLAN RXUCF RXPCF RXCF RXADATA BCAST MCAST 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x1D

64 Rev. 1.0 Register 41. CPINFOL: Current Packet Information Low Byte Register 42. CPLENH: Current Packet Length High Byte Register 43. CPLENL: Current Packet Length Low Byte Bit 7: RXOK: Receive OK 0: Receive not OK. 1: Receive OK. Bit 6: LENGTH: Length/Type Field Detection 0: The length/type field of the current packet contains the packet length. 1: The length/type field of the current packet contains the packet type. Bit 5: LENERR: Length Check Error 0: No errors detected in length field. 1: The length field does not match actual packet length. Bit 4: CRCERR: CRC Error 0: CRC check passed. 1: CRC check failed. Bits 3–2: Reserved: Read = varies. Bit 1: RXLEN: Receive Length 0: Normal Operation. 1: The data received is not long enough to form a valid packet. Bit 0: RXDROP: Packet Dropped 0: Normal operation. 1: A packet has been dropped. RRRRRRRR R e s e t V a l u e RXOK LENGTH LENERR CRCERR Reserved Reserved RXLEN RXDROP 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x1E Bits 7–0: CPLENH: Current Packet Length High Byte High byte of the current packet length. RRRRRRRR R e s e t V a l u e Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x1F Bits 7–0: CPLENL: Current Packet Length Low Byte Low byte of the current packet length. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x20

Rev. 1.0 65 Register 44. CPADDRH: Current Packet Address High Byte Register 45. CPADDRL: Current Packet Address Low Byte Note: The contents of this register are invalid following a buffer overflow event. Bits 7–0: CPADDRH: Current Packet Address High Byte High byte of the current packet starting address in the receive FIFO buffer. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x21 Note: The contents of this register are invalid following a buffer overflow event. Bits 7–0: CPADDRL: Current Packet Address Low Byte Low byte of the current packet starting address in the receive FIFO buffer. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x22

The Receive FIFO Full interrupt will be generated once all free space in the buffer is used or all TLB slots are filled. discarding them. Packets can be discarded one at a time or all at once by writing ‘1’ to RXCLEAR (RXCN.0). accessed by the host processor except for debug purposes. Table 17. Receive Status and Control Register Summary associated with TLBn (n = 0–7). Points to the byte following the last valid byte. This is where new packets are added. and is incremented with each Auto Read. Bits 7–3: UNUSED. Read = 00000b; Write = don’t care. The TLB Number (0–7) of the TLB slot associated with the current packet.

68 Rev. 1.0 Register 47. TLBVALID: TLB Valid Indicator Register 48. TLBnINFOH: TLBn Information High Byte Bits 7–0: TLBVALID: TLB Valid Indicator Displays the valid bits for the eight TLB slots in a single byte. Note: This register may be used to clear multiple valid bits simultaneously. For all writes, bits with a value of ‘0’ will cause the associated valid bit to be cleared, and bits with a value of ‘1’ will be ignored. For example, writing 0xFE to this register will clear the valid bit for TLB0. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value VAL7 VAL6 VAL5 VAL4 VAL3 VAL2 VAL1 VAL0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x1C Address: TLB0INFOH: 0x23; TLB1INFOH: 0x 29; TLB2INFOH: 0x2F; TLB3INFOH: 0x35; TLB4INFOH: 0x3B; TLB5INFOH: 0x41; TLB6INFOH: 0x47; TLB7INFOH: 0x4D Bit 7: Reserved. Read = varies; Bit 6: RXVLAN: VLAN Type Detected 0: VLAN tagged frame not detected. 1: VLAN tagged frame detected. Bit 5: RXUNSUP: Unsupp orted Control Frame 0: Unsupported control frame not detected. 1: Unsupported control frame detected. Bit 4: RXPCF: Pause Control Frame 0: Pause control frame not detected. 1: Pause control frame detected. Bit 3: RXCF: Control Frame 0: Control frame not detected. 1: Control frame detected. Bit 2: RXADATA: Additional Data Received 0: Normal Operation. 1: 1 to 7 additional bits of data received following receipt of the packet. Bit 1: BCAST: Broadcast Packet 0: Packet is not a broadcast packet. 1: Packet is a broadcast packet. Bit 0: MCAST: Multicast Packet 0: Packet is not a multicast packet. 1: Packet is a multicast packet. RRRRRRRR R e s e t V a l u e Reserved RXVLAN RXUCF RXPCF RXC F RXADATA BCAST MCAST 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Rev. 1.0 69 Register 49. TLBnINFOL: TLBn Information Low Byte Register 50. TLBnLENH: TLBn Packet Length High Byte Address: TLB0INFOH: 0x24; TLB1INFOH: 0x2A; TLB2INFOH: 0x30; TLB3INFOH: 0x36; TLB4INFOH: 0x3C; TLB5INFOH: 0x42; TLB6INFOH: 0x48; TLB7INFOH: 0x4E Bit 7: RXOK: Receive OK 0: Receive not OK. 1: Receive OK. Bit 6: LENGTH: Length/Type Field Detection 0: The length/type field of the current packet contains the packet length. 1: The length/type field of the current packet contains the packet type. Bit 5: LENERR: Length Check Error 0: No errors detected in length field. 1: The length field does not match actual packet length. Bit 4: CRCERR: CRC Error 0: CRC check passed. 1: CRC check failed. Bits 3–2: Reserved: Read = varies. Bit 1: RXLEN: Receive Length 0: Normal Operation. 1: The data received is not long enough to form a valid packet. Bit 0: RXDROP: Packet Dropped 0: Normal operation. 1: A packet has been dropped. RRRRRRRR R e s e t V a l u e RXOK LENGTH LENERR CRCERR Reserved Reserved RXLEN RXDROP 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: TLB0LENH: 0x25; TLB1LENH: 0x2B; TLB2LENH: 0x31; TLB3LENH: 0x37; TLB4LENH: 0x3D; TLB5LENH: 0x43; TLB6LENH: 0x49; TLB7LENH: 0x4F Bits 7–0: TLBnLENH: TLBn Packet Length High Byte High byte of the packet length for the packet associated with TLBn. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

70 Rev. 1.0 Register 51. TLBnLENL: TLBn Packet Length Low Byte Register 52. TLBnADDRH: TLBn Packet Address High Byte Register 53. TLBnADDRL: TLBn Packet Address Low Byte Address: TLB0LENH: 0x26; TLB1LENH: 0x2C; TLB2LENH: 0x32; TLB3LENH: 0x38; TLB4LENH: 0x3E; TLB5LENH: 0x44; TLB6LENH: 0x4A; TLB7LENH: 0x50 Bits 7–0: TLBnLENL: TLBn Packet Length Low Byte Low byte of the packet length for the packet associated with TLBn. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Note: The contents of this register are invalid following a buffer overflow event. Address: TLB0ADDRH: 0x27; TLB1ADDRH: 0x2D; TLB2ADDRH: 0x33; TLB3ADDRH: 0x39; TLB4ADDRH: 0x3F; TLB5ADDRH: 0x45; TLB6ADDRH: 0x4B; TLB7ADDRH: 0x51 Bits 7–0: TLBnADDRH: TLBn Packet Address High Byte High byte of the packet starting address for the packet associated with TLBn. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Note: The contents of this register are invalid following a buffer overflow event. Address: TLB0ADDRH: 0x28; TLB1ADDRH: 0x2E; TLB2ADDRH: 0x34; TLB3ADDRH: 0x3A; TLB4ADDRH: 0x40; TLB5ADDRH: 0x46; TLB6ADDRH: 0x4C; TLB7ADDRH: 0x52 Bits 7–0: TLBnADDRL: TLBn Packet Address Low Byte Low byte of the packet starting address for the packet associated with TLBn. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Rev. 1.0 71 Register 54. RXFIFOHEADH: Receive FIFO Head Pointer High Byte Register 55. RXFIFOHEADL: Receive FIFO Head Pointer Low Byte Register 56. RXFIFOTAILH: Receive FIFO Tail Pointer High Byte Register 57. RXFIFOTAILL: Receive FIFO Tail Pointer Low Byte Bits 7–0: RXFIFOHEADH: Receive FIFO Head Pointer High Byte High byte of the receive FIFO buffer head pointer. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x17 Bits 7–0: RXFIFOHEADL: Receiv e FIFO Head Pointer Low Byte Low byte of the receive FIFO buffer head pointer. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x18 Bits 7–0: RXFIFOTAILH: Receiv e FIFO Tail Pointer High Byte High byte of the receive FIFO buffer tail pointer. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x15 Bits 7–0: RXFIFOTAILL: Receive FIFO Tail Pointer Low Byte Low byte of the receive FIFO buffer tail pointer. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x16

72 Rev. 1.0 Register 58. RXFIFOSTA: Receive FIFO Status Register This register is set by hardware and is valid after an RX FIFO Full Interrupt is generated or if TLBVALID equals 0xFF. Bits 7–2: UNUSED. Read = 000000b, Write = don’t care. Bits 1–0: FIFOSTA[1:0]: Receive FIFO Status 00: Initial Value— No information. 01: The last packet successfully received used all available free space in the buffer. 10: The last packet successfully received was the 8th packet in the receive buffer. There is free space remaining in the receive buffer; however, the maximum number of packets in the buffer has been reached. Any future packets received will cause overflow. Note: Receiving an unsuccessful 9th packet will cause overflow. 11: The last packet successfully received was the eighth packet in the receive buffer and used all available free space in the buffer. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value — — — — — — FIFOSTA1 FIFOSTA0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x5B

Rev. 1.0 73 13. Flash Memory The CP2200/1 has 8 kB of on-chip non-volatile Flash memory fully accessible by the host processor. The last six bytes of this memory space (addresses 0x1FFA to 0x 1FFF) are factory preprogrammed and contain a unique 48- bit MAC Address (Individual Address) registered with the IEEE Registration Authority. The most significant byte of the MAC address is at 0x1FFA, and the least significant byte is at 0x1FFF. The last page of Flash containing the MAC address is erasable, and the user should exercise caution to prevent erasing the MAC Address. 13.1. Programming the Flash Memory The Flash memory can be programmed one byte at a time th rough the parallel host interface. Once cleared to a logic 0, a Flash bit must be erased to set it back to logic 1. A Flash bit may always be changed from logic 1 to logic 0, as long as Flash bytes are only written once between erase cycles. Flash erase operations erase an entire 512 byte sector at a time. Fl ash write and erase operations are automati cally timed by hardware and do not affect the parallel host interface. After initiating a Flash write or erase operation, the host CPU can continue to access the CP2200/1 through the parallel host interface while the Flash operation is taking place. The host is notified with an interrupt request when the Flash write or erase operation is complete. Refer to Table 18 for complete Flash memory electrical characteristics including typical write and erase cycle times. The Flash memory can be writ ten and erased using the FLASH ADDRH:FLASHADDRL, FLASHDATA, and FLASHERASE registers. Once a Flash o peration is initiated, the status can be moni tored using the FLASHSTA register, or the host can wait for notification by the interrupt signal. 13.1.1. Flash Lock and Key Protection The Flash memory is protected from errant write and eras e operations by a lock and key function. Flash reads are unrestricted. The Flash Lo ck and Key Register (FL ASHKEY) must be written wit h the correct key codes, in sequence, before each Flash write or er ase operation. If a Flash write or erase operation is attempted without first writing the correc t key codes to the FLASHKEY regist er, Flash cannot be written or erased until the next reset. After programming Flash, the CP2200/1 should be reset in order to protect the device from errant Flash operations. The key codes for unlocking the CP2200/1 are 0xA5 and 0x F1. These codes must be written in sequence to the FLASHKEY register prior to each Flash write or erase operation. Note: To ensure the integrity of Flash contents, the on-chip V DD Monitor should not be disabled while the Flash memory is unlocked. 13.1.2. Flash Erase Procedure Step 1: Write 0xA5 followed by 0xF1 to FLASHKEY. Step 2: Set FLASHADDRH:FLASHADDRL to any address within the 512-byte page to be erased. Step 3: Write the value 0x01 to FLASHERASE. Step 4: Check FLASHSTA to determine when the Flash operation is complete. The Flash Write/Erase Completed interrupt can also be use to determine when the operation completes. 13.1.3. Flash Write Procedure Step 1: Write 0xA5 followed by 0xF1 to FLASHKEY. Step 2: If the byte to be written is not 0xFF, then erase the page containing the byte. Step 3: Set FLASHADDRH:FLASHADDRL to the address of the byte to be written. Step 4: Write the value to be written to the FLASHDATA register. Step 5: Check FLASHSTA to determine when the Flash operation is complete. The Flash Write/Erase Completed interrupt can also be used to determine when the operation is complete.

accessing sequential data in Flash by automatically incrementing the Flash address pointer after each read. Step 1: Set FLASHADDRH:FLASHADDRL to the address of the byte to be read. Step 2: Read the value of the byte from FLASHDATA. Step 1: Set FLASHADDRH:FLASHADDRL to the address of the first byte to be read. Step 2: For each byte, read the value from FLASHAUTORD. Table 18. Flash Electrical Characteristics VDD = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified.

Table 19. Flash Access Register Summary unlock the Flash for writing or erasing. 16-bit Address used for Flash operations. FLASHERASE Flash Erase 0x6A Initia tes a Flash erase operation. wait for the Flash Write/Erase Operation Complete Interrupt to occur. Bits 7–4: UNUSED. Read = 0000b, Write = don’t care. This bit indicates when a FLASH write or erase operation is in progress. 1: FLASH write/erase operation is currently in progress. 0: The last Flash operation completed was not a Flash write. 1: The last Flash operation completed was a Flash write. 0: The last Flash operation completed was not a Flash erase. 1: The last Flash operation completed was a Flash erase.

76 Rev. 1.0 Register 60. FLASHKEY: FLASH Lock and Key Register Register 61. FLASHADDRH: FLASH Address Register High Byte Register 62. FLASHADDRL: FLASH Address Register Low Byte Bits 7-0: FLKEY: Flash Lock and Key Register This register must be written to unlock the Flash for writing or erasing. To unlock the Flash, first write 0xA5 and then 0xF1 to this register. The VDD Monitor should not be disabled while the Flash is unlocked. The device must be unlocked prior to each Flash write/erase operation. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x67 Bits7–0: FLASHADDRH: Flash Address Register High Byte Holds the most significant eight bits of the target FLASH address. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x69 Bits7–0: FLASHADDRL: Flash Address Register Low Byte Holds the least significant eight bits of the target FLASH address. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x68

Rev. 1.0 77 Register 63. FLASHDATA: FLASH Read/Write Data Register Register 64. FLASHAUTORD: FLASH AutoRead Data Register Register 65. FLASHERASE: FLASH Erase Register Bits7–0: FLASHDATA: Flash Read/Write Data Register Read: Value of the Flash byte at the location specified by FLASHADDRH:FLASHADDRL. Write: Initiates a Flash write operation to the Flash byte at the address in FLASHADDRH:FLASHADDRL. The Flash memory must be unlocked, and the target Flash byte should have a value of 0xFF (value of erased Flash). R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x06 Bits7–0: FLASHAUTORD: Flash AutoRead Data Register Reads from this register return the value of the Flash byte at the location specified by the Flash Address Register. The Flash Address Register is automatically incremented by 1 after the read. RRRRRRRR R e s e t V a l u e 00000000 Bit7 Bit6 Bit5 Bit4 B Bit2 Bit1 Bit0 Address: 0x05 Bits 7–2: UNUSED. Read = 000000b, Write = don’t care. Bit 1: Reserved. Must write 0b. Bit 0: FLEGO: Flash Erase Start. Writing a ‘1’ to this bit initiates a Flash erase operation on the 512-byte page of Flash containing the Flash byte at the location specified in the Flash Address Register. The Flash memory must be unlocked prior to starting a Flash erase operation. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value —————— R e s e r v e d F L E G O 0 0 0 0 0 0 0 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x6A

78 Rev. 1.0 14. Media Access Controller (MAC) The CP2200/1 has an IEEE 802.3 complia nt Ethernet Media Access Cont roller (MAC). The MAC can be configured to automatically pad short frames (full du plex mode only), append CRC, and perform frame length checking. A loopback mode separate from PHY loopbac k is also provided for system debugging. The MAC is configured through nine indirect 16-bit registers summarized in Table 20. 14.1. Initializing the MAC MAC initialization occurs afte r the physical layer initializat ion and typically occurs once after each reset or Auto- Negotiation Complete interrup t. Most MAC indirect registers can be left at their reset values. See “6.2. Reset Initialization” on page 18 for the comp lete reset initialization procedure. The following are the steps required to initialize the MAC: Step 1: Determine if the physical layer is set to full-duplex or half-duplex. The MAC must be set to the same duplex mode as the physical layer before sending or receiving any packets. Step 2: Write 0x40B3 (full-duplex) or 0x4012 (half-duplex) to MACCF. The appropriate bits in this register may also be set or cleared to change padding options or MAC behavior. Step 3: Write 0x0015 (full-duplex) or 0x0012 (half-duplex) to IPGT. Step 4: Write 0x0C12 to IPGR. Step 5: Write 0x05EE to MAXLEN. Step 6: Program the 48-bit Ethernet MAC Address by writing to MACAD0:MACAD1:MACAD2. Step 7: Write 0x0001 to MACCN to enable reception. If loopback mode or flow control is desired, set the appropriate bits to enable these functions. 14.2. Accessing the Indirect MAC Registers The indirect MAC registers are accessed through fo ur direct mapped registers: MACADDR, MACDATAH, MACDATAL, and MACRW. The MAC registers can be accessed using the following procedure: Step 1: Write the address of the indirect register to MACADDR. Step 2: If writing a value to the indirect register, write a 16-bit value to MACDATAH:MACDATAL. Step 3: Write any value to MACRW to transfer the contents of MACDATAH:MACDATAL to the indirect register. Step 4: Perform a read on MACRW to transfer the contents of the indirect register to MACDATAH:MACDATAL. The MACDATAH and MACDATAL registers may now be directly read to determine the contents of the indirect register.

Rev. 1.0 79 Register 66. MACADDR: MAC Indirect Address Register 67. MACDATAH: MAC Data High Byte Register 68. MACDATAL: MAC Data Low Byte Register 69. MACRW: MAC Read/Write Initiate Bits 7–0: MACADDR: MAC Indirect Address Indirect MAC register address targeted by reads/writes to MACRW. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x0A Bits 7–0: MAC Data High Byte Holds the most significant 8-bits of data read or written to an indirect MAC register. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x0B Bits 7–0: MAC Data Low Byte Holds the least significant 8-bits of data read or written to an indirect MAC register. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x0C Bits 7–0: MAC Read/Write Initiate Initiates a read or write to the indirect MAC register at the address stored in MACADDR. Write: The contents of MACDATAH:MACDATAL are transferred to the target MAC register. Read: The contents of the target MAC register are transferred to MACDATAH:MACDATAL. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x0D

for detailed register descriptions. Table 20. Indirect MAC Register Summary MACCN MAC Control 0x00 Used to enable reception and other options. IPGT Back-to-Back Interpacket Delay 0x02 Set s the Back-to-Back Interpacket Delay. mum number of retransmits allowed. MAXLEN Maximum Frame Length 0x05 Sets the maximum receive frame length. Sets the MAC address of the local device.

Rev. 1.0 81 Indirect Register 1. MACCN: MAC Control Register Bit 15: Reserved. Read = varies; Must write 0b. Bit 14: RANDRST: Random Number Generator Reset Writing a ‘1’ to this bit resets the random number generator within the transmit function. Bits 13–5:Reserved. Read = varies; Must write 000000000b. Bit 4: LOOPBCK: Loopback Mode Enable Bit Note: MAC Loopback Mode is independent of the physical layer loopback mode. 0: Normal operation. 1: MAC transmit data is internally looped back as MAC receive data. Bit 3: TXPAUSE: TX Flow Control Enable Bit (Full-Duplex Only) 0: PAUSE control frames are blocked. 1: PAUSE control frames are allowed to pass through the MAC. Bit 2: RXPAUSE: RX Flow Control Enable Bit (Full-Duplex Only) 0: PAUSE control frames received from the physical layer are ignored. 1: PAUSE control frames received from the physical layer are acted upon. Bit 1: Reserved. Read = 0; Must write 0b. Bit 0: RCVEN: Receive Enable 0: The MAC blocks control frames from reaching the receive interface. The MAC blocks all received packets from the receive interface. 1: The MAC allows received packets to reach the receive interface. R/W R/W R/W R/W R/W R/W R/W R/W Reserved RANDRST Reserved Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 R/W R/W R/W R/W R/W R/W R/W R/W Default Value Reserved LOOPBCK TXPAUSE RX PAUSE Reserved RCVEN 0x8000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MACADDR: 0x00

82 Rev. 1.0 Indirect Register 2. MACCF: MAC Configuration Register Bit 15: Reserved. Read = 0b; Must write 0b. Bit 14: ABORTD: Abort Disable Bit 0: MAC will abort when excessive delay is detected and update the transmit status vector. 1: MAC will attempt to transmit indefinitely as specified in IEEE 802.3. Bit 13: EBBPD: Exponential Backoff after Back Pr essure Disable Bit (Half-Duplex Only) 0: After incidentally causing a collision during back pressure, the MAC will use the exponential backoff algorithm as specified in IEEE 802.3. 1: After incidentally causing a collision during back pressure, the MAC will immediately transmit without using the exponential backoff algorithm. Bit 12: EBD: Exponential Backoff Disable (Half-Duplex Only) 0: MAC will use the exponential backoff algorithm as specified in IEEE 802.3. 1: MAC will immediately retransmit following a collision. Bits 11–10:Reserved. Read = 00b; Write = don’t care. Bit 9: RLPRE: Reject Long Preamble 0: MAC allows any length preamble as specified in IEEE 802.3. 1: MAC rejects packets with a preamble greater than 12 bytes in length. Bit 8: PUREPRE: Pure Preamble Enforcement 0: No preamble checking is performed. 1: MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. Packets with an invalid preamble will be rejected. Bit 7–6: PADMD[1:0]: Pad Mode Note: This bit field is ignored if PADEN is cleared to ‘0’. See Table 21 for a complete description. Bit 5: PADEN: Pad Enable Bit (must be set to 0 in half-duplex operation) Note: See Table 21 for a complete description. Bit 4: CRCEN: CRC Enable Bit Note: This bit must be set to ‘1’ if padding is enabled. 0: CRC will not be appended. Frames presented to the MAC must contain CRC. 1: CRC will be appended. R/W R/W R/W R/W R/W R/W R/W R/W Reserved ABORTD EBBPD EBD Reserved RLPRE PUREPRE Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 R/W R/W R/W R/W R/W R/W R/W R/W Default Value PADMD1 PADMD0 PADEN CRCEN PHEADER Reserved LENCHK FLLDPLX 0x0000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MACADDR: 0x01

0: No proprietary header exists on the front of IEEE 802.3 frames. will be ignored by the CRC function. Bit 2: Reserved. Read = 0b; Must write 0b. 0: Frame length checking is disabled. 0: MAC operates in half-duplex mode. 1: MAC operates in full-duplex mode. Table 21. Pad Operation

84 Rev. 1.0 Indirect Register 3. IPGT: Back-to-Back Inter-Packet Gap Register Indirect Register 4. IPGR: Non-Back-to-Back Inter-Packet Gap Register Bits 15–7:Reserved. Read = 000000000b; Must write 000000000b. Bits 6–0: IPGT: Back-to-Back Inter-Packet Gap Register Sets the minimum delay between the end of any transmitted packet and the start of a new packet. In Full-Duplex mode, the register value should be set to the desired number of time units (each time unit is 0.46 µs) minus 3. The recommended setting is 0x15 (21d), which yields 9.6 µs. In Half-Duplex mode, the register value should be set to the desired number of time units (each time unit is 0.46 µs) minus 6. The recommended setting is 0x12 (18d), which yields 9.6 µs. R / WR / WR / WR / WR / WR / WR / WR / W Reserved Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 R/W R/W R/W R/W R/W R/W R/W R/W Default Value Reserved IPGT 0x0000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MACADDR: 0x02 Bit 15: Reserved. Read = 0b; Must write 0b. Bits 14–8:IPGR1: Non-Back-to-Back Inter-Packet Gap Part 1 values for this bit field are 0x00 to IPGR2. The recommended value is 0x0C. Bit 7: Reserved. Read = 0b; Must write 0b. Bits 6–0: IPGR2: Non-Back-to-Ba ck Inter-Packet Gap Part 2 Sets the Non-Back-to-Back Inter-Packet Gap. The recommended value is 0x12, which represents a minimum inter-packet gap of 9.6 µs. R / WR / WR / WR / WR / WR / WR / WR / W Reserved IPGR1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 R/W R/W R/W R/W R/W R/W R/W R/W Default Value Reserved IPGR2 0x0000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MACADDR: 0x03

Rev. 1.0 85 Indirect Register 5. CWMAXR: Collision Window and Maximum Retransmit Register Indirect Register 6. MAXLEN: Maximum Frame Length Register Note: This register does not require initialization and will be left at its reset value by most systems. Bits 15–14:Reserved. Read = 00b; Must write 00b. Bits 13–8:CW: Collision Window Sets the collision window in which collisions occur in a properly configured network. The collision window is specified in the number of bytes from the start of transmission. The pream- ble and frame delimiter are included in the byte count. Its default of 0x37 corresponds to the count of frame bytes at the end of the window. Bits 7–4: Reserved. Read = 0 000b; Must write 0000b. Bits 3–0: MAXR: Maximum Retransmit Attempts Sets the maximum number of retransmit attempts following a collision before aborting the packet due to excessive collisions. IEEE 802.3 specifies a maximum value of 0x0F (15d). R / WR / WR / WR / WR / WR / WR / WR / W Reserved CW Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 R/W R/W R/W R/W R/W R/W R/W R/W Default Value Reserved MAXR 0x370F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MACADDR: 0x04 Note: This register does not require initialization and will be left at its reset value will be set to 1518 (0x05EE) by most systems. Bits 15–0:MAXF: Maximum Frame Length Specifies the maximum length of a receive frame. The default value is 0x600 (1536 octets). This register should be programmed if a shorter maximum length restriction is desired. Examples of shorter frame lengths are untagged (1518 octets) and tagged (1522 octets). If a proprietary header is allowed, this field should be adjusted accordingly. R / WR / WR / WR / WR / WR / WR / WR / W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 R/W R/W R/W R/W R/W R/W R/W R/W Default Value 0x0600 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MACADDR: 0x05

86 Rev. 1.0 Indirect Register 7. MACAD0: MAC Address 0 Indirect Register 8. MACAD1: MAC Address 1 Bits 15–8:OCTET6: MAC Address, 6th Octet This field holds the sixth (least significant) octet of the MAC address. Bits 7–0: OCTET5: MAC Address, 5th Octet This field holds the fifth octet of the MAC address. R / WR / WR / WR / WR / WR / WR / WR / W OCTET6 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 R/W R/W R/W R/W R/W R/W R/W R/W Default Value OCTET5 0x0000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MACADDR: 0x10 Bits 15–8:OCTET4: MAC Address, 4th Octet This field holds the fourth octet of the MAC address. Bits 7–0: OCTET3: MAC Address, 3rd Octet This field holds the third octet of the MAC address. R / WR / WR / WR / WR / WR / WR / WR / W OCTET4 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 R/W R/W R/W R/W R/W R/W R/W R/W Default Value OCTET3 0x0000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MACADDR: 0x11

Rev. 1.0 87 Indirect Register 9. MACAD2: MAC Address 2 Bits 15–8:OCTET2: MAC Address, 2nd Octet This field holds the second octet of the MAC address. Bits 7–0: OCTET1: MAC Address, first Octet This field holds the first (most significant) octet of the MAC address. R/W R/W R/W R/W R/W R/W R/W R/W OCTET2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 R/W R/W R/W R/W R/W R/W R/W R/W Default Value OCTET1 0x0000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MACADDR: 0x12

88 Rev. 1.0 15. Physical Layer (PHY) The CP2200/1 has an IEEE 80 2.3 compliant 10 BASE-T Ethe rnet physical la yer transceiver that includes a receiver, transmitter, auto-negotiation, loopback, jabber, smart squelch, polarity co rrection, and link integrity functions. If enabled, the auto-negotiation function aut omatically negotiates the sp eed of the data link and the duplex mode. Both half-duplex and full-duplex modes are supported. The physical layer is controlled and monitored through three registers: PHYCN, PHYCF, and PHYSTA. The various functions and test modes that can be enabled and monitored through these registers are explained in the following sections. 15.1. Auto-Negotiation and Duplex Mode Auto-negotiation allows the CP220 0/1 to be connected to any 10/10 0/1000 BASE-T Ethern et network and advertise its capabilities. Auto-negotiation uses a series of fast lin k pulses to send 16-bit link code words. Many conditions (e.g., failure to detect fast link pulses) can cause auto-negotiation to fail. On failure, the Auto-Negotiation Failed interrupt will be generat ed, and/or the Auto-Negoti ation Complete Interrupt will not be ge nerated. The PHYSTA status register will indicate the cause of failure, and the physical layer will default to half-duplex mode. On success, the Auto-Negotiation Complete interrupt will be generated, and the Auto-Negotiation Failed interrupt will not be generated. Both interrupts must be checked to ensure that Auto-Negotiation has succeeded. The advertised link speed will always be 10BASE-T. The duplex mode (half or full) will be ne gotiated, and full duplex will be selected if supported by the network. Full duplex mode allows the physical layer to send and receive data at the same time. In half duplex mode, data can only be transmitted or received at any given time. Full duplex mode provides overall higher performance and reduces collisions. Software may also choose to advertise its ability to send and receive PAUSE control packets by setting ADPAUSE (PHYCF.2) to ‘1’. Important Note: When using auto-negotiation, the au to-negotiation enable bit AUTONEG (PHYCF.4) must be set to ‘1’ prior to enabling the physical layer. To restart auto-negotiation, the physical layer (transmitter, receiver, or both) must be disabled and reenabled. Important Note: The CP220x supports legacy link partners that ca nnot auto-negotiate. If the link partner cannot autonegotiate, then the physical layer will default to half-duplex mode. 15.2. Auto-Negotiation Synchronization The CP220x implements an autonegotiation scheme where autonegotiation is attempted for 250 ms, then a break- link delay of 1.5 seconds is inserted between auto-negot iation attempts. When the break-link delay is active, the CP220x does not listen for incoming auto-negotiation requests and does not attempt to auto-negotiate. If one device starts autonegotiation while the other device is in its “break-link period”, the autonegotiation attempt will fail. If the devices are unsyncronized, this can lead to a situation where each device attempts to autonegotiate in the other device’s “break-link period”. This can be solved by synchronizing one or both devices using the following procedure: Step 1: Disable the physical layer by writing 0x00 to the PHYCN register. Step 2: Enable the physical layer with link integrity test and auto-negotiation turned off. 1.Disable the transmitter power save mode (TXPWR = 0x80) and set physical layer options (PHYCF = SMSQ | JABBER | ADPAUSE | AUTOPOL). 2.Enable the physical layer (PHYEN = 1). 3.Wait for the physical layer to power up. See Physical Layer Startup Time in Table 22 on page 93. 4.Enable the transmitter and receiver (TXEN = 1 and RXEN = 1). Step 3: Poll the Wake-on-LAN interrupt flag (WAKEINT) to detect if a link partner is present. 1.If there is a signal, wait 250 ms then begin autonegotiation. 2.If there is no signal, wait 1.5 seconds then begin autonegotiation.

Rev. 1.0 89 15.3. Loopback Mode Loopback Mode provides th e ability to transfer data from the physical layer’s output directly to it’s input to aid in system debugging. When PHYCN.3 is set to ‘1’, transmit data is looped back to the receiver via an internal analog path. The transmit drivers and receive input circuitry ar e bypassed, isolating the device from the network. This prevents network traffic from affect ing the result of any system self-t ests and guarantees a collision-free environment. 15.4. Link Integrity Function The Link Integrity fu nction provides the ability to detect and respond to a 10 BASE-T link failure. When such a failure is detected, the transmitter and receiver are automa tically disabled, and the state of the link is reported in LINKSTA (PHYCN.0). The host can disable the link integrity function by clearing LINKINT (PHYCF.6) to ‘0’. When the link integrity function is disabled, the physical layer will operate regardless of the presence of link pulses. 15.5. Receiver Smart Squelch and Automatic Polarity Correction The physical layer receiver can detect and correct for noise or incorrect polarity of the received signal. If the receiver Smart Squelch feature is enab led by setting SMSQ (PHYCF.7) to ‘1’, the receiver circuitry performs a combination of amp litude and timing measurements (in accordance with IEEE 802.3) to determine the validity of received data. This prevents noise from falsely triggering the receiver in the absence of valid data. Automatic polarity correction can automat ically detect and correct the polarity of the received data to compensate for a wiring error at either end of the 10 BASE-T cable. Wh en automatic polarity correcti on is enabled by setting AUTOPOL (PHYCF.1) to ‘1’, the polarity of the receive data is indicated in POLREV (PHYCN.1). When automatic polarity detection is disabled, the polarity of the receive data can be manually reversed by setting REVPOL (PHYCF.0) to ‘1’. 15.6. Transmitter Jabber Function Provides the ability to automatically disable the transmitter if software attempts to transmit a packet longer than the maximum allowed packet length (per IEEE 802.3). The host processor will be notified via the Jabber Detected Interrupt if a jabber condition is automatically han dled by the hardware. En abling the jabber function is recommended to ensure that the embedded system using the CP2200/1 for Ethernet communication does not generate a jabber condition on the wire.

90 Rev. 1.0 15.7. Initializing the Physical Layer The physical layer should be configured to the desired mode prior to setting the enable bit PHYEN (PHYCN.7). The following procedure should be used to initialize the physical layer: Step 1: If auto-negotiation is used, implement the synchronization procedure in Section 15.2 on page 88. Step 2: Disable the physical layer by writing 0x00 to the PHYCN register. Step 3: Configure Desired Options using the PHYCN and PHYCF registers: 1.Specify the Duplex Mode or enable Auto-Negotiation. 2.Enable or Disable Loopback Mode. 3.Disable the transmitter power save mode (TXPWR = 0x80). 4.Enable the desired functions such as Receiver Smart Squelch, Automatic Polarity Correction, Link Integrity, Jabber Protection, and PAUSE packet capability advertisement. 5.If Automatic Polarity Correction is disabled, manually set the desired polarity. Step 4: Enable the physical layer: 1.Enable the physical layer (PHYEN = 1). 2.Wait for the physical layer to power up. See Physical Layer Startup Time in Table 22 on page 93. 3.Enable the transmitter and receiver (TXEN = 1 and RXEN = 1). Step 5: Wait for auto-negotiation to complete. If auto-negotiation is not enabled, software may wait for a valid link or go directly to MAC Initialization. Step 6: Enable the desired Activity, Link, or Activity/Link LEDs using the Register 15, “IOPWR: Port Input/ Output Power Register,” on page 45. Step 7: Initialize the MAC to the same duplex mode reported by the physical layer in the PHYCN register. Note: Step 6 and Step 7 are repeated in the reset initialization procedure. Software only needs to perform these steps once.

Rev. 1.0 91 Register 70. PHYCN: Physical Layer Control Register Important Note: When using auto-negotiation, the auto-negotiation enable bit, AUTONEG (PHYCF.4), must be set to “1” prior to setting PHYEN, TXEN, and RXEN to 1. To restart auto-negotiation, clear one of the three enable bits (PHYEN, TXEN, and RXEN) to “0” then set it back to “1”. Bit 7: PHYEN: Physical Layer Enable 0: The physical layer is placed in a low-power state with limited functionality. 1: The physical layer is placed in a normal power state and is fully functional. Bit 6: TXEN: Transmitter Enable 0: Physical Layer’s transmitter is placed in a low-power state. Packet transmission and Link Pulse Generation Functions are disabled. 1. Physical layer’s transmitter is enabled. Bit 5: RXEN: Receiver Enable 0: Physical layer’s receiver is placed in a low-power state. Packet reception is disabled. 1: Physical layer’s receiver is enabled. Bit 4: DPLXMD: Full-duplex Mode Enable Bit Note: This bit is read-only when Auto-Negotiation is enabled. 0: Half-duplex mode is selected. 1: Full-duplex mode is selected. Bit 3: LBMD: Loopback Mode Enable Bit Note: Loopback mode is automatically disabled if a jabber condition is detected. 0: Loopback mode is disabled. 1: Loopback mode is enabled. Bit 2: LPRFAULT: Link Partner Remote Fault (Local Fault) Indicator 0: Normal operation. 1: The link partner has detected a link fault and has sent notification during auto-negotiation. This condition can occur if the local transmitter is disabled and link pulses are no longer generated. Bit 1: POLREV: Polarity Reversed Indicator 0: Incorrect link polarity has not been detected. 1: Incorrect link polarity detected. Link polarity has been automatically reversed. Bit 0: LINKSTA: Link Status Indicator 0: Link is bad. 1: Link is good. R/W R/W R/W R/W or RO R/W R R R Reset Value PHYEN TXEN RXEN DPLXMD LBMD LPRFAULT POLREV LINKSTA 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x78

92 Rev. 1.0 Register 71. PHYCF: Physical Layer Configuration Register Bit 7: SMSQ: Receiver Smart Squelch Enable Bit 0: Receiver Smart Squelch is disabled. 1: Receiver Smart Squelch is enabled. Bit 6: LINKINT: Link Integrity Function Enable Bit Note: When enabled, the link integrity function will automatically disable the transmitter and receiver and update LINKSTA (PHYCN.0) if a link failure is detected. 0: Link integrity function is disabled. 1. Link integrity function is enabled. Bit 5: JABBER: Jabber Protecti on Function Enable Bit Note: When enabled, the jabber protection function will automatically disable loopback mode if a jabber condition is detected. 0: Jabber protection function is disabled. 1: Jabber protection function is enabled. Bit 4: AUTONEG: Auto-Neg otiation Enable Bit 0: Auto-Negotiation function is disabled. 1: Auto-Negotiation function is enabled. Bit 3: Reserved. Read = 0b; Must write 0b. Bit 2: ADPAUSE: Advertise Pause Packet Capability 0: Indicates (during auto-negotiation) that the CP2200/01 does not have pause packet capability. 1: Indicates (during auto-negotiation) that the CP2200/01 does have pause packet capability. Bit 1: AUTOPOL: Automatic Pola rity Correction Enable Bit 0: Automatic receiver polarity correction is disabled. 1: Automatic receiver polarity correction is enabled. Bit 0: REVPOL: Polarity Reversal Bit Note: This bit is ignored if Automatic Polarity Correction is enabled. 0: The receiver polarity is normal. 1: The receiver polarity is reversed. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SMSQ LINKINTG JABBER AUTONEG Reserve d ADPAUSE AUTOPOL REVPOL 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x79

Table 22. 10BASE-T Interface DC Electrical Characteristics VDD = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified. Note: The Auto-Negotiation states and error types are described in Clause 28 of IEEE 802.3. 1: Auto-negotiation failed due to an incompatible link.

1. Auto-negotiation failed due to a link fault.

1: Auto-negotiation failed due to lack of reception of fast link pulses. 1: Auto-negotiation failed due to reception of a link code word with the ACK bit cleared. 1: Auto-negotiation failed due to reception of inconsistent link code words. 1: Auto-negotiation failed due to lack of reception of fast link pulses. 1: Auto-negotiation failed due to the reception of link code word(s) with the ACK bit set. 1: Auto-negotiation failed due to the lack of reception of three consecutive link code words.

Figure 21. 10BASE-T Link Integrity Table 25. 10BASE-T Link Integrity Switching Characteristics VDD = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified.

1. The CP2201 (28-pin package) can only be used in multiplexed mode.
2. The PCB traces connecting RD, WR, CS, ALE, and all address and data lines should be matched such that the

propagation delay does not vary by more than 5n s between any two signals. 30 Mbps can be achieved. Tables 26 through 29 provide detailed information about bus timing in each mode. Figure 22. Nonmuxed Intel READ

1. CS must be asserted with or before RD.
2. WR must remain de-asserted during a READ.
3. CS must be asserted with or before WR.
4. RD must remain de-asserted during a WRITE.

Figure 23. Nonmuxed Intel WRITE Table 26. Non-Multiplexed Intel Mode AC Parameters

Table 27. Multiplexed Intel Mode AC Parameters

Table 28. Non-Multiplexed Motorola Mode AC Parameters

Table 29. Multiplexed Motorola Mode AC Parameters

Rev. 1.0 105 17.2. MAC Address Filtering Problem For unicast packets received over the Ethernet wire, the rece ive filter only validates the first 5 bytes of the 6-byte Ethernet MAC Address. Any packet addressed to a device whose MAC address only differs in the 6th byte will be allowed to pass through the receive filter. Workaround The Ethernet driver on the host controlle r should verify that the 6th byte of ea ch packet (i.e., the final byte of the MAC address) matches its assigned MAC address. If it detects a mismatch, the packet should be discarded by writing 1 to the RXSKIP bit. Implications on Throughput This behavior does not slow down the rate which the embedded system can send or receive packets, since the CP220x must receive and filter all packets on the network. However, it can interrupt the host controller for received packets addressed to another device with a similar MAC address (where the only difference is in the 6th byte) on the same subnet. On a managed switch network, present on most corporate LANs, the effect of this behavior is minimal due to the fact that the managed switch filters out unicast packets not addressed to the receiving Ethernet device.

106 Rev. 1.0 DOCUMENT CHANGE LIST Revision 0.4 to Revision 0.41 „ Modified Figure 2, “Typical Connection Diagram (Non-Multiplexed),” on page 6 and Figure 3, “Typical Connection Diagram (Multiplexed),” on page 7 for improved EMI emmissions and common mode stability. Revision 0.41 to Revision 1.0 „ Added Maximum Supply Current specification in Table 2 on page 9. „ Updated the maximum XTAL1 Input Low Voltage specification from 0.8 to 0.7 V (see Table 8 on page 20). „ Updated the maximum RST Input Pullup Current specification from 40 to 50 µA (see Table 13 on page 42). „ Updated the Non-Multiplexed EMIF address hold time from 20 to 30 ns and the Tvd2 specification from 40 to 60 ns. Note that the Thold specification is unchanged from its value of 60 ns; therefore, changes to host timing will not be required in most applications. See Section 16 on page 96. „ Added a Revision-Specific Behavior chapter. See Section 17 on page 104. „ Removed text indicating that all packets on the wire can be received and buffered by the CP220x.

Rev. 1.0 107 NOTES:

108 Rev. 1.0 CONTACT INFORMATION Silicon Laboratories Inc.

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