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Rev. 0.2 10/13 Copyright © 2013 by Silicon Laboratories CP2130-EK CP2130-EK CP2130 E VALUATION K IT U SER ’S G UIDE 1. Introduction The CP2130 Evaluation Kit consists of a CP2130 Evaluati on Board and software package to demonstrate the use of the CP2130 USB-to-SPI bridge to communicate with several SPI slave devices, including an on-board SPI ADC and SPI EEPROM. Several PC applications are included to demo nstrate the CP2130 feat ures and evaluate SPI performance. 2. Kit Contents The CP2130 Evaluation Kit contains the following items: CP2130 Evaluation Board Mini-USB Cable CP21xx Installation DVD Quick Start Guide 3. Relevant Documentation Application notes can be found on the Interface Application Notes pa ge for all fixed-function devices: www.silabs.com/interface-appnotes. AN721: CP21xx Device Customization Guide—Customize the VID, PID, serial number, and other parameters stored in the CP2130 one-time programmable ROM. AN792: CP2130 Interface Specification—Describes the USB control and bulk transfers for CP2130 devices as well as GPIO configuration. 4. Software Setup The Software Development Kit (SDK) for the CP2130 Evaluation Kit is incl uded on the kit DVD. The latest version of this installer can also be downloaded from the www.silabs.com/cp2130ek web site. This package includes: Documentation—data sheet, application notes, user’s gu ide, quick start guide, and SLAB_USB_SPI interface library API documentation. CP2130 Demo—Example software utilizing th e SLAB_USB_SPI interface library API to demonstrate the CP2130 Evaluation Board features. CP2130 Evaluation Tool—Advanced evaluation software used to execute low-level SPI transfers, control GPIO outputs, and retrieve device information. AN721 Device Customization Utility—Customization software used to program the one-time programmable ROM. Library—SLAB_USB_SPI interface library and header files used to interface between a user application and USB driver such as Microsoft’s WinUSB driver. The Windows installer should launch automatically after inserting the DVD. Follow the instructions to install the SDK to the system.

  1. CP2130 Hardware Interface
  2. Connect the CP2130 Evaluation Boar d to a PC as shown in Figure 1.
  3. Connect one end of the mini-USB cable to a USB Port on the PC.
  4. Connect the other end of the mini-USB cable to the mini-USB connector on the CP2130 Evaluation Board.

Figure 1. Hardware Setup

  1. CP2130 WinUSB Driver Installation

automatically install the driver on Windows machines. The CP2130 appears as a “Silicon Labs CP2130 USB to SPI Bridge” in Device Manager as shown in Figure 2. Figure 2. CP2130 in Device Manager

  1. CP2130 Software Interface

Evaluation Tool is an advanced tool used to execute low-level SPI transfers.

  1. CP2130 Demo Windows Application

following steps describe how to start the application and demonstrate some of its features.

  1. Make sure that the hardware is connected to a Window s PC as shown in Figure 1. If the device is properly
  2. Launch the CP2130 Demo application, which is found by clicking

StartAll ProgramsSilicon LaboratoriesCP2130 Evaluation KitCP2130 Demo.

  1. This application demonstrates the features of t he CP2130 Evaluation Board and requires the default

Config button to launch the help window.

  1. The Jumper Config window display the factory default jumper configuration. Install shorting blocks to

match the jumper locations outlined in red. Figure 3. Configuring the CP2130 Evaluation Board Shorting Blocks

  1. Connect to the CP2130 USB-to-SPI bridge by selecting the device in the Device Selection combo box

and clicking the Connect button. Figure 4. Connecting to a CP2130 Evaluation Board

  1. Observe the potentiometer voltage displayed in the Potentiometer Voltage gauge. Rotate the

potentiometer and watch the voltage change.

  1. Observe the temperature sensor value displayed in the Temperature Sensor gauge.

Figure 5. Reading the Potentiometer and Temperature Sensor ADC Channel Inputs

  1. Run SPI throughput tests using CS1 :

Read, Write/Read (simultaneous write and read). click the Continuous checkbox and then click Run Speed Test to run a continuous throughput test. Click Stop Speed Test to cancel a continuous throughput test. c. Observe the throughput measurement in the SPI Throughput gauge. Figure 6. Running SPI Throughput Tests

  1. Configure the general purpose input/output (GPIO) pins and read and write the pin latch values:

b. Read the current state of the GPIO pin latch from the Logic Level text field. latch value of ‘0’ will turn the LED on. Driving a latch value of ‘1’ will turn the LED off. Figure 7. Controlling GPIO Pins

  1. Write and read back a string to the external SPI EEPROM:

a. Enter a string into the Write text box. Click the Write button to write the string to the external EEPROM. Figure 8. Reading and Writing the SPI EEPROM

  1. Use the CP2130 event counter feature to monitor push-button presses on the EVENT button which is

field updates to reflect the total number of button presses. b. Click the Reset button in the application to clear the event count back to zero. Figure 9. Monitoring Push-Button Presses Using the Event Counter

  1. Plot the ADC analog input sample values:

a. Click the Plot ADC button to open the plot window. c. View the graph of the selected ADC input channel. Figure 10. Plotting ADC Sample Values

  1. CP2130 Evaluation Tool Windows Application

and demonstrate some of its features.

  1. Make sure that the hardware is connected to a Window s PC as shown in Figure 1. If the device is properly
  2. Launch the CP2130 Evaluation Tool application, which is found by clicking

StartAll ProgramsSilicon LaboratoriesCP2130 Evaluation KitCP2130 Evaluation Tool.

  1. Select the CP2130 device path in the Choose device combo box.
  2. Click the Connect button to connect to the device.

Figure 11. Connecting to a CP2130 Device Using the Evaluation Tool

  1. Once connected to a device, the application disp lays non-configurable and one-time configurable device

divider reset value is stored in the one-time programmable ROM but may be changed at runtime. divided by the CLKOUT divider. Figure 12. Connected Device Information

14 Rev. 0.2 6. To configure an SPI data transfer: a. Select one of the following transfer types from the SPI Transfer Type radio buttons: i. Write—Execute a synchronous SPI write. Write the data as specified in the Transmit Data section. ii. WriteRead—Execute a synchronous, simultaneous SPI write and read. Write the data as specified in the Transmit Data section and return the read data in the Receive Data section. iii. Read (Synchronous)—Execute a synchronous SPI read. The read data is returned in the Receive Data section. iv. Read (Asynchronous)—Execute an asynchronous SPI read. The read data is returned in the Receive Data section. An asynchronous read can be aborted before the specified timeout has elapsed and before the specified number of bytes are read by clicking on the Abort Read Operation button. v. Read with RTR—Execute an asynchronous SPI read with RTR. The CP2130 will read bytes only when the GPIO.3 / CS3 / RTR signal is asserted. The read data is returned in the Receive Data section. An asynchronous read with RTR can be aborted before the specified number of bytes are read by clicking on the Abort Read Operation button. b. Enter values in the Test Configuration text fields: i. Total Bytes (<1M)—Specifies the total number of bytes to read or write. For a WriteRead operation, this field specifies the number of bytes that will be read and the number of bytes that will be written. ii. Timeout (ms)—Specifies the timeout for SPI transfer operations in milliseconds. If the specified total number of bytes isn’t read or written in the time specified, the operation will timeout and abort. iii. Poll/RTR Block Size—For an asynchronous read and a read with RTR, the poll/RTR block size specifies the number of bytes to read from the library buffer during each poll interval period. iv. Poll Interval (ms)—For asynchronous read and read with RTR, the poll interval specifies how frequently to check for SPI read data in milliseconds. c. Configure the SPI parameters: i. Phase (CPHA)—Specifies the SPI clock phase: Leading Edge, Trailing Edge ii. Polarity (CPOL)—Specifies the SPI clock polarity: Active High, Active Low iii. Chip Select Mode—Specifies the output mode for th e specified chip select pin: Open Drain, Push-Pull iv. Clock Frequency—Specifies the SPI clock frequency: 12 MHz, 6M H z, 3M H z, 1.5 MHz, 750 kHz, 375 kHz, 187.5 kHz, 93.75 kHz v. Chip Select (0–10)—Specifies which chip-select pin is asserted during SPI transfers: CS0 – CS10 vi. Toggle CS—Specifies that the chip-select pin will be toggled after each SPI byte transferred. vii. Post-Assert Delay—Specifies the amo unt of time that the CP2130 will delay after the last SPI byte has been transferred before deasserting the chip-select pin. The delay is in units of 10 µs. viii. Inter-Byte Delay—Specifies the amount of time that the CP2130 will delay between SPI byte transfers. The delay is in units of 10 µs. ix. Pre-Deassert Delay—Specifies the amount of time that the CP2130 will delay after asserting the chip-select pin before the first SPI byte is transferred. The delay is in units of 10 µs.

Figure 13. Configuring an SPI Transfer

  1. To execute a WriteRead SPI transfer:

a. Select the WriteRead radio button from the SPI Transfer Type group box. read/write in the Total Bytes (<1M) text field. and send the data in the write transfer. number of bytes are written. iii. Random—Write random data until the sp ecified number of bytes are written. d. Click the Execute SPI Transfer button to start the WriteRead SPI transfer. f. The SPI transfer status and statistics will be displayed in the output text box at the bottom of the dialog. Figure 14. Executing a WriteRead SPI Transfer

  1. To execute an asynchronous Read SPI transfer:

a. Select the Read (Asynchronous) radio button from the SPI Transfer Type group box. the poll block size in bytes and poll interval in milliseconds. current read before the timeout elapses or the total number of bytes is read. block size every poll interval. poll interval will be logged. Figure 15. Executing an Asynchronous Read SPI Transfer

  1. Click the Reset button to send the Reset command to the CP2130. After the device receives this

command, it will perform a reset and re-enumerate on the bus.

  1. GPIO pins configured as GPIO outputs can controlled using the GPIO Toggle buttons. Click the GPIO pin

0–10 button to toggle the output latch value. GPIO pins not configured as GPIO outputs are grayed out. Figure 16. Resetting the Device and Toggling GPIO Pins

  1. CP2130 Evaluation Board Overview

Figure 17. CP2130 Evaluation Board Features (Front)

Figure 18. CP2130 Evaluation Board Features (Back)

This header can be used to connect the CP2130 to a CP2400 AB LCD expansion board. ribbon cable interface. See Table 1 for the SPI monitor pin definitions. CP2130. See Table 2 for the USB pin definitions. Table 1. SPI Monitor Pin Definitions

1 No Connect

3 No Connect

4 No Connect

6 No Connect

10 GND

Table 2. Mini-USB Connector Pin Definitions

1 VBUS

4 ID (No Connect)

5 GND (Ground)

voltage regulator is enabled. The board VDD is powered by the CP2130 internal voltage regulator output. See Table 4 for the VREGIN input header pin definitions. Table 3. Power and SPI Pin Definitions

4 VDDSW (Switched Supply)

6 VBUS

Table 4. VREGIN Input Header Pin Definitions

1 VDD (Self-Powered)

3 VBUS (Bus-Powered)

during normal SPI operation. See Table 6 for the SPI loopback header pin definitions. VIO. See Table 7 for the ADC VDD header pin definitions. Table 5. JP3, JP4, and JP5 LED Header Locations Table 6. SPI Loopback Header Pin Definitions Table 7. ADC VDD Header Pin Definitions

corresponding to each header position. CP2130 CS0 pin. See Table 9 for the ADC chip-select header pin definitions. EEPROM from VIO. See Table 10 for the EEPROM VDD header pin definitions. CP2130 CS2 pin to the EEPROM chip-select pin. See Table 11 for the EEPROM chip select header pin definitions. Table 8. ADC Channel Input Header Locations Table 9. ADC Chip-Select Header Pin Definitions

1 ADC Enable

Table 10. EEPROM VDD Header Pin Definitions

2 EEPROM VDD

Table 11. EEPROM Chip-Select Header Pin Definitions

the ADC reset pin via GPIO.7. See Table 12 for the ADC reset header pin definitions. Event Button (Short Pins 1–2 on JP17)— Count events from the event button. See Table 13 for the event counter input header pin definitions. to the CP2130 GPIO.3 / CS3 / RTR pin. See Table 14 for the RTR button header pin definitions. Table 12. ADC Reset Header Pin Definitions

2 ADC RST

Table 13. Event Counter Input Header Pin Definitions

1 EVENT Button

Table 14. RTR Header Pin Definitions

1 RTR Button

See Table 15 for the SPI monitor chip-select input header pin definitions. Table 17 for the VIO header pin definitions. Table 15. SPI Monitor Chip-Select Input Header Pin Definitions Table 16. ADC SPI Header Locations Table 17. VIO Header Pin Definitions

Figure 20. CP2130 Evaluation Board Schematic (1 of 2)

Figure 21. CP2130 Evaluation Board Schematic (2 of 2)

Table 18. CP2130 Evaluation Board Bill of Materials

Table 18. CP2130 Evaluation Board Bill of Materials (Continued)

32 Rev. 0.2 CONTACT INFORMATION Silicon Laboratories Inc.

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