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12 Configurable GPIO Pins with Alternate Functions

Figure 1. Example System Diagram

256 B RX

256 B TX

12 Mbps

352 Byte PROM

2 Rev. 1.1

Rev. 1.1 3 TABLE OF C ONTENTS Section Page

4 Rev. 1.1 1. System Overview All major commercial operating systems (Windows, Linux , Mac, iOS) support the standard USB Audio Device class. Codecs and DACs typically have only an I 2S (Inter-IC Sound) digital interface, and thus cannot connect directly to a host system. In addition, when a DAC is powered on, it typically needs to be configured by the host via an I 2C (inter-integrated-circuit) digital interface, with a non-standard protoc ol. Finally, in order to support push button volume and mute synchronization with the host system, the target USB device must support the standard USB-HID Consumer Control interface. Thus, adding USB di gital audio to an embedded system or as dongle or appliance typically involves complex US B protocol programming as well as I 2S and I 2C programming capability, prototyping, integration and testing. The CP2114 USB Audi o Bridge is specifically de signed to overcome all these issues and commoditize USB Audio and DAC configuration for turn-key product development. Note: Use with an iPad requires a camera kit connector to get USB from the Apple 30-pin connector. USB Audio is not sup- ported on the iPhone. The CP2114 includes a USB 2.0 full-speed function controller, USB transceiver, oscillator, one-time programmable read-only memory (ROM), I2S (audio) interface, I2C (control) interface, and UART interface in a compact 5 x 5 mm QFN-32 package (sometimes called “MLF” or “MLP”). The one-time programmable ROM on the device may be used to customize both product informat ion (including USB fields such as Ve ndor ID, Product ID, Strings, etc...) and external DAC configuration strings. By default, the CP2114 provides the following features Enumerates to the host as a Standard USB Audio Device and HID Consumer Control supporting: USB Digital Audio Out (Audio Playback Device) USB Digital Audio In (Microphone/Recording Device) HID Consumer Control handling standard volume and mute functionality Pre-configured support for 3 commercial DACs Handles all I2C configuration of the DAC automatically at boot Handles all volume and mute traffic converting from USB to I2C messages to the DAC Tested for USB plug & play and audio quality on all major operating systems UART interface using standard USB HID device class which is natively supported by most operating systems No custom driver installation needed Windows and MAC DLLs provided and interface specification is available for development on any operating system Implements transmit (TX), receive (RX), hardware flow control (CTS, RTS) Baud rate support from 300 to 1 Mbps, support for 5-8 data bits, 5 parity options, 3 types of stop bits Note: The CP2114 devices will not enumerate as a standard HID mouse or keyboard. 12 GPIO signals which support alternate functions Volume control, UART transmit and receive, UART hardware flow control, UART transmit/receive toggle, configurable clock output, and DAC selection Support for I/O interface voltages down to 1.8 V is provided via a VIO pin. An evaluation kit for the CP2114 (Part Number: CP2114EK) is available. It includes a CP2114-based USB-to-Audio motherboard, a USB cable, and full documentation. Additional kits with daughtercards are available as well: CP2114-CS42L55 evaluation kit (Part Number: CP2114-CS42L55EK) includes: CP2114 USB-to-I2S Digital Audio motherboard Cirrus Logic CS42L55 Codec daughtercard (includes a 3.5mm male-to-male audio cable) CP2114-WM8523 evaluation kit (Part Number: CP2114-WM8523EK) CP2114 USB-to-I2S Digital Audio motherboard Wolfson Microelectronics WM8523 DAC daughtercard CP2114-PCM1774 evaluation kit (Part Number: CP2114-PCM1774EK) CP2114 USB-to-I2S Digital Audio motherboard Texas Instruments PCM1774 DAC daughtercard All kits with daughtercards include a USB cable, ear bud headphones, and full documentation. Contact a Silicon Labs sales representatives or go to www.silabs.com to order a CP2114 Evaluation Kit.

  1. Electrical Characteristics

Table 1. Global DC Electrical Characteristics VDD = 3.0 to 3.6 V, –40 to +85 °C unless otherwise specified.

  1. If the device is connected to the USB bus, the USB Pull-up Current should be added to the supply current for total
  2. The USB Pull-up supply current values are calculated values based on USB specifications.

Table 2. I2S, I2C, UART and Suspend I/O DC Electrical Characteristics VDD = 3.0 to 3.6 V, VIO = 1.8 V to VDD, –40 to +85 °C unless otherwise specified. Table 3. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Table 4. Voltage Regulator Electrical Specifications –40 to +85 °C unless otherwise specified. *Note: The maximum regulator supply current is 100 mA. This includes the supply current of the CP2114.

Table 5. GPIO Output Specifications –40 to +85 °C unless otherwise specified. Table 6. One Time Programming Specifications VDD = 3.3 to 3.6 V, –40 to +85 °C unless otherwise specified.

3.3 V DD V

Table 7. System Clock Specifications VDD = 3.3 to 3.6 V, –40 to +85 °C unless otherwise specified.

  1. Depending on the requirements of the external DAC, the system clock frequency will be either 48.0 or 49.152 MHz. See

Section 5.6 for more information.

  1. The USB specification requires a clock accuracy of ±0.25%.

Table 8. I2S Digital Audio Interface Specifications VDD = 3.3 to 3.6 V, –40 to +85 °C unless otherwise specified. *Note: Measurement bandwidth: 100 Hz –40 kHz. Table 9. I2C Specifications VDD = 3.3 to 3.6 V, –40 to +85 °C unless otherwise specified.

Table 10. Analog Output/Input Characteristics (CS42L55 daughtercard) *Note: When analog input is locally muted, the CP2114 transmits sample values of 0 to the host. Table 11. Analog Output Characteristics (WM8523 daughtercard)

Figure 4. WM8523 THD+N vs. Amplitude (997 Hz) Table 12. Analog Output/Input Characteristics (PCM1774 Daughtercard)  AOUT_L and AOUT_R outputs have 4.7  series resistors.

Table 13. Absolute Maximum Ratings operation of the devices at or exceeding the conditions in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

  1. Pinout and Package Definitions

Table 14. CP2114 Pin Definitions Voltage Regulator Output. See Section 10. VIO 6 Power In I/O Supply Voltage Input. GND 3 Ground. Must be tied to ground. REGIN 8 Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator. programming via the USB interface. SCK 2 D Out Serial clock output signal for the I 2S interface. SDIN 1 D In Serial data input signal for the I 2S interface. SDOUT 32 D Out Serial data output signal for the I 2S interface. MCLK 25 D Out Master clock output signal for the I 2S interface. LRCK 23 D Out Left-right clock output for the I 2S interface. codec/DAC does not support a 12.000 MHz master clock (MCLK). SDA 27 D I/O Serial data signal for the I 2C interface. SCL 26 D I/O Serial clock signal for the I 2C interface. User-configurable input or output. User-configurable input or output. *Note: Pins can be left unconnected when not used.

User-configurable input or output. Decreases volume each time this pin is driven low. User-configurable input or output. Increases volume each time this pin is driven low. User-configurable input or output. Record Mute LED: This pin is driven low while recording is muted. User-configurable input or output. the UART is not transmitting data. Selects one of the predefined DACs. See Section 8.2 for more information. User-configurable input or output. Selects one of the predefined DACs. See Section 8.2 for more information. User-configurable input or output. Ready to Send control output (active low) for the UART Interface. Selects one of the predefined DACs. See Section 8.2 for more information. User-configurable input or output. Clear To Send control input (active low) for the UART Interface. Selects one of the predefined DACs. See Section 8.2 for more information. User-configurable input or output. Outputs a configurable frequency clock signal. User-configurable input or output. Asynchronous data output (UART Transmit) for the UART Interface. User-configurable input or output. Asynchronous data input (UART Receive) for the UART Interface. NC 24* This pin should be left unconnected or tied to V IO. Table 14. CP2114 Pin Definitions (Continued) *Note: Pins can be left unconnected when not used.

Figure 5. QFN-32 Pinout Diagram (Top View)

25 MCLK16

  1. QFN-32 Package Specifications

Figure 6. QFN-32 Package Drawing Table 15. QFN-32 Package Dimensions

  1. All dimensions shown are in millimeters (mm) unless otherwise noted.
  2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
  3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for

custom features D2, E2, and L which are toleranced per supplier designation.

  1. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Figure 7. QFN-32 Recommended PCB Land Pattern Table 16. QFN-32 PCB Land Pattern Dimensions

  1. All dimensions shown are in millimeters (mm) unless otherwise noted.
  2. This Land Pattern Design is based on the IPC-7351 guidelines.
  3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder

mask and the metal pad is to be 60 m minimum, all the way around the pad.

  1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used

to assure good solder paste release.

  1. The stencil thickness should be 0.125 mm (5 mils).
  2. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
  3. A 3x3 array of 1.0 mm square openings on 1.2 mm pitch should be used for the center ground
  4. A No-Clean, Type-3 solder paste is recommended.
  5. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
  1. Audio (I2S and I2C) Interfaces

programmable ROM configuration and a real-time API. read to the CP2114 GPIO pins as desired. shows the signals in Left-Justified format. Figure 8. I2S Format

Figure 9. Left-Justified Format LRCK going to the connected audio device. Typically MCLK = 250*LRCK or MCLK=256*LRCK. device to latch the audio output data bits on SDOUT and assert the audio input data bits on SDIN. SDOUT: Audio-out data stream going to the connected audio device (e.g. CODEC). SDIN: Audio-in data stream coming from the connected audio device (e.g. CODEC). Note: MCLK, LRCK, SCK and SDOUT are driven by the CP2114. SDIN is driven by the connected audio device. a configuration option in the CP2114 one-time programmable ROM. sample rate of LRCK = 48 kHz, the resulting MCLK requirement is shown in Equation 1 or Equation 2.

configurations to address this issue and is covered in Section 5.6. Table 17. USB Audio Synchronization Modes

  1. Implicit feedforward means the recipient determines the next data input size according to the current input

size (i.e. if 48 samples were sent in the current frame then expect the same number in the next frame).

  1. Explicit feedback means the recipient of the feedback will receive an explicit request for the number of

samples to send in the next frame.

The CP2114 always reports its capabilities to the USB host at a sample rate of 48 kHz and sample size of 16 bits. For source audio files differ ing from this format the U SB host will automatically perfor m sample rate conversion. the host sample rate, or to periodically drop or repeat an audio sample if SYSCLK is driven by an External Clock. Table 18. Clock Configuration Options Table 19. Valid Clock Configuration Modes

  1. USB Function Controller and Transceiver

pin has the opposite logic value of the SUSPEND pin. to ensure SUSPEND remains low during reset. the PROM. See Section 9 for more information.

  1. Asynchronous Serial Data Bus (UART) Interfaces

rates. The data formats and baud rates available are listed in Table 20. will choose the closest possible option. The actual baud rate is dictated by Equation 3 and Equation 4. Table 20. Data Formats and Baud Rates

  1. 1.5 stop bits only available when using 5 data bits.
  2. Baud rates above 500,000 baud are not supported with 5 or 6
  3. Max of 500 kBaud with flow control, audio playback only
  4. Max of 230 kBaud with flow control, audio playback and listening
  5. With flow control, audio can support higher baud rates, but

throughput is greatly reduced.

rates, the total baud rate error can be found using Equation 5. 1 to 125 ms, or it can be set to transmit indefinitely until a stop command is sent from the application. information about programming the GPIO pin functionality. voltage through an external pull-up resistor. The maximum external pull-up voltage is 5 V. inputs or outputs are not recommended for real-time signaling. Table 21. GPIO Alternate Functions

(GPIO.0_RMUTE) and the playback mute (GPIO.1_PMUTE) buttons will toggle between mute and unmute states. 1110b (Index 14), or if any of the fo ur GPIO.5-8 pins have been configured to something other than DAC Select. selection pin mapping is shown in Table 22. Table 22. DAC Selection Pin Mapping

UART data transfer is in progress. Typically, these pins are connected to two LEDs to indicate data transfer. Figure 12. Transmit and Receive Toggle Typical Connection Diagram

high to indicate to the external UART device to stop sending data. bytes of data once CTS is pulled high. Figure 13. Hardware Flow Control Typical Connection Diagram

  1. One-Time Programmable ROM
  2. Global configuration area. This area stores the USB string descriptors and GPIO pin configuration. The
  3. Audio specific configuration area. This area stores up to 32 different audio configurations. The

configurations set behavior of the CP2114 audio functions as well as configuration data for DACs. programmed, the device uses the default configuration data shown in Table 26 and Table 27. 3.3 V or higher to successfully write to the configuration ROM. Figure 14. One-Time Programmable ROM Configuration Block Diagram

sections describe the audio interface in more detail. can be set by a one-time programmable ROM boot index or by reading the boot index from the DAC Select pins. can be programmed in-system or Silicon Labs can provide preprogrammed parts with a customer configuration. Figure 15. Boot Configuration Flowchart

  1. Programmability of the CP2114 itself.
  2. Programmability of the DAC.

configuration of the DAC. Table 23 shows the format of the configuration string for the CP2114 and attached DAC. are used to specify delays and are documented in the following sections. field before sending the request to the device. Table 23. Audio Configuration String

0 DAC_Version Identifies revision of DAC

1 User_Defined User can store any info desired here

2 I2C_Address Specify the DAC I

3 Audio_Props Controls audio properties

0: Asynchronous. Will send feedback to USB host. clock adjustment of sample insert/drop, depending on clock configuration. I2C_CK Maximum I 2C clock rate supported by the DAC. I2C_PR I 2C Protocol for read operations. LJMS I 2S Mode. Only applies if using Left Justified format. 0: 16bit Left Justified Mode.

7 System_Props System Properties

DMMF DAC Min/Max register Format. SVRP Secondary Volume Registers Polarity. 1: Secondary volume registers have opposite polarity as primary registers. the DAC, either can be designated as primary. CP2114 updates either or both registers when the host changes volume. Some DACs may require a separate bit as a “take into effect immediately” bit. 0: DAC has no volume update registers. 1: DAC has volume update registers. SCS System Clock Source. NOTE: Audio cl ocks will be driven from this source. ACR Audio Clock Ratio. This is the MCLK/LRCK ratio. 8 DPVCL DAC Primary Volume Control Left channel register address. 9 DPVCR DAC Primary Volume Control Right channel register address. 10 DSVCL DAC Secondary Volume Control Left channel register address. 11 DSVCR DAC Secondary Volume Control Right channel register address. 12 DPMBLC DAC Primary Mute Bit Left Chan nel register address. Ignored if MB=0. 13 DPMBRC DAC Primary Mute Bit Right Channel register address. Ignored if MB=0. 14 DSMBLC DAC Secondary Mute Bit Left Channel register address. Ignored if MB=0. 15 DSMBRC DAC Secondary Mute Bit Right Channel register address. Ignored if MB=0.

16 DVCB DAC Volume Control Bits start position and bits count. would set Volume_Bit_Count=7 and Volume_Bit_Start=0. VBS Volume Bits Start. Specifies the start position of the volume significant bits. 17 DMBP DAC Mute Bit Positions. DMBPL DAC Mute Bit Position Left channel. Ignored if MB=0. DMBPR DAC Mute Bit Position Right channel. Ignored if MB=0. 20 DVUBP DAC Volume Update Bit Position. Ignored VUR=0.

25 DMP1 DAC Mute Property 1

GPION GPIO Number (0..11) used for DAC mute. Ignored of MBG=0. SWM GPIO State When Muted. Ignored of MBG=0. 0: Do not use GPIO for mute.

26 DMP2 DAC Mute Property 2

1: Mute by sending 00’s to the DAC. This is useful for a DAC that does not support hardware mute or volume functions. Not supported when playback and record are both active. MBVR Mute By Volume Register. 0: Do not mute via the volume register. 1: Mute via the volume register. Some DACs mute by sending a specific value to the volume register. 27 DVMV DAC Volume Mute Value. Mute by sending this value to the volume registers.

28 Reserved Reserved

29 Reserved Reserved

Rev. 1.1 35 9.1.3. DAC Configuration String Starting at byte 30, a DAC configuration string is used to communicate with the DAC over the I 2C interface. If the DAC register size bit is 0 (indicating 8-bit mode), the DAC register/value pairs should be written in the format of: Byte[30] = <DAC_Register_Address> Byte[31] = <DAC_Register_Value> Byte[32] = <DAC_Register_Address> Byte[33] = <DAC_Register_Value> ... If the DAC register size bit is 1 (indicating 16-bit mode), the DAC register/value pairs should be written in the format of: Byte[30] = <DAC_Register_Address> Byte[31] = <DAC_Register_Value_MSB> Byte[32] = <DAC_Register_Value_LSB> Byte[33] = <DAC_Register_Address> Byte[34] = <DAC_Register_Value_MSB> Byte[35] = <DAC_Register_Value_LSB> ... 9.1.4. DAC Configuration In-Band Commands To support special functions such as GPIO outputs, arbitrary delay in between DAC register access, DAC power off sequence in suspend and power on sequence in active mode, the CP2114 supports special in-band commands starting from byte 30. These commands are identified by command codes 0xFA to 0xFF. When parsing DAC register/value pairs, if CP2114 firmware encounters 0xFA to 0xFF in the <DAC_Register_Address> field, the CP2114 performs the task associated with the command instead of sending it to the DAC. SUSPEND_SEQUENCE specifies a sequence of DAC register/value pairs/triplets to power down certain blocks on the DAC in suspend mode to minimize power consumption. ACTIVE_SEQUENCE specifies a sequence of DAC register/value pairs/triplets to power up certain blocks on the DAC in active mode. The DELAY_MICROSECONDS, SET_GPIO and DELAY_MILLISECONDS in-band commands can be embedded in SUSPEND_SEQUENCE and ACTIVE_SEQUENCE if needed. SET_GPIO sets a specified GPIO to high or low. DELAY_MICROSECONDS instructs the firmware to introduce a coarse delay of n microseconds as specified in the parameter list. Similarly, DELAY_MILLISECONDS instructs the firmware to introduce a course delay in milliseconds. The format of most In-band commands exce pt for SUSPEND_SEQUENCE and ACTIVE_SEQUENCE is analogous to DAC register/value pairs/triplets.

reset via a GPIO pin, this can be accomplished with in-band commands as well. should be set to minimum. This allows CP2114 to synchronize with the host at startup. Table 24. DAC Configuration In-Band Commands

programmable ROM as shipped for the CS42L55 codec. Table 25. CS42L55 Configuration String 3 A6 MB = 1 Mute is handled with this DAC. ST = 0. Use Asynchronous mode—provide feedback to the host. I2C_PR = 0. I2C uses stop bit. DRS = 0. DAC has 8-bit registers. LJMS = 1. 24bit Left Justified mode is used. AF = 0. Left Justified format is used. 4 C4 Minimum volume value for the DAC is 0xC4 = –60 dB. 6 01 Volume step per dB is 1. 7 E0 DMMF = 1. DAC min/max registers are signed. ARE = 1. Analog Record is enabled. SVRP = 1. Secondary volume registers have opposite polarity as primary registers. VUR = 0. DAC does not have volume update (take effect) registers. UCS = 0. USB clock uses internal oscillator. SCS = 0. System clock uses internal oscillator. SF = 0. System frequency is 48 MHz. ACR = 0. Audio Clock Ration (MCLK/LRCK) is 250. VBC = 7. Volume register has 7 significant bits. VBS = 0. Volume control starts at bit 0.

18 44 DVMV = 0x44. DAC value for minimum volume is 0x44. 19 0C DVXV = 0x0C. DAC value fo r maximum volume is 0x0C. 20 00 NA - No volume update register. 21 00 NA - No volume update register. 22 00 NA - No volume update register. 23 00 NA - No volume update register. 24 00 NA - No volume update register. 25 00 NA. MBG = 0. No Mute by GPIO. 26 00 MBZ = 0. Do not mute by sending 00’s. MBVR = 0. Do not mute but volume register. 27 00 DVMV = 0. Do not mute by sending value to register.

addition, each field in Table 26, Table 27, and Table 28 may only be customized once. Table 26. Default USB Configuration Data Table 27. Default GPIO Data Table 28. Default UART and Suspend Data

shown in Note 5 of Figure 17 is required to meet the absolute maximum voltage on VBUS specification in Table 13. Figure 16. Typical Bus-Powered Connection Diagram added at the connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent. Note 3 : An external pull-up is not required, but can be added for noise immunity. not be connected to other circuitry, and VIO must be at least 3.3 V.

3.45 V Power

the regulator bypassed is shown in Figure 17. Figure 17. Typical Self-Powered Connection Diagram (Regulator Bypass) added at the connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent. Note 3 : An external pull-up is not required, but can be added for noise immunity. not be connected to other circuitry, and VIO must be at least 3.3 V. absolute maximum voltage on VBUS specification in the Electrical Characteristics section.

42 Rev. 1.1 11. CP2114 Interface Specification and Windows Interface DLL The CP2114 is a USB Human Interface Device (HID), an d as most operating systems include native HID drivers, custom drivers do not need to be installed. The CP2114 does not fit one of the standard HID device types, such as a keyboard or mouse, and any CP2114 PC application needs to use the CP2114’s HID specification to communicate with the device. The low-level HID specif ication for the CP2114 is provided in “AN433: CP2110/ CP2114 HID Interface Specification.” This document describes all of the basic functions for opening, reading from, writing to, and closing the device, as well as the ROM programming functions. A Windows DLL that encapsulates the CP2114 HID interfac e and also adds higher level features such as read/ write time-outs is provided by Silicon Labs. This DLL is the recommended interface for the CP2114. The Windows DLL is documented in CP2114 Windows DLL Specification. Both of these documents and the DLL are available online at http://www.silabs.com/. 12. Relevant Application Notes The following Application Notes are applicable to the CP 2114. The latest versions of these application notes and their accompanying software are available at http://www.silabs.com/appnotes. AN721: CP210x/CP21xx Device Customization Guide. This application note describes how to use the AN721 software CP21xxSetIDs to configure the USB parameters on the CP21xx devices. AN433: CP2110/CP2114 HID to UART API Specification. This application note describes how to interface to the CP2114 using the Windows Interface DLL and the Max OS-X dylib.

Rev. 1.1 43 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1  Updated text describing MCLK as an input. MCLK is an output from the CP2114.  Referenced the SDIN signal to a generic audio device, rather than a DAC, since a DAC would not have an input signal.  Added a row for VBUS in Table 13, “Absolute Maximum Ratings,” on page 12.  Added VDD Ramp Time for Power On specification to Table 3, “Reset Electrical Characteristics,” on page 6.  Added VPP Voltage specification to Table 6, “One Time Programming Specifications,” on page 7.  Updated "10. Voltage Regulator" on page 40 to add absolute maximum voltage on VBUS requirements in self- powered systems.

44 Rev. 1.1 CONTACT INFORMATION Silicon Laboratories Inc.

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