CD4001

CD4001 SYC | Alldatasheet

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• PDF pages: 8

Technical content

Features

■ Low power TTL: Fan out of 2 driving 74L compatibility: or 1 driving 74LS ■ 5V–10V–15V parametric ratings ■ Symmetrical output characteristics ■ Maximum input leakage 1 µA at 15V over full temperature range Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC and SOP CD4001BC Top View Pin Assignments for DIP and SOIC CD4011BC Top View Order Number Package Number Package Description CD4001BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4001BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4001BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4011BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4011BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide www.sycelectronica.com.ar

J = A + B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. CD4011BC 1/4 of device shown J = A • B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. www.sycelectronica.com.ar

Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The Electrical Characteristics tables provide conditions for actual device operation. Note 2: All voltages measured with respect to V SS unless otherwise speci- fied. Note 3: IOL and IOH are tested one output at a time. CD4001BC: TA = 25°C, Input tr; tf = 20 ns. CL = 50 pF , RL = 200k. Typical temperature coefficient is 0.3%/°C. Note 4: AC Parameters are guaranteed by DC correlated testing. Voltage at any Pin −0.5V to VDD +0.5V Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW V DD Range −0.5 VDC to +18 VDC Storage Temperature (TS) −65°C to +150°C Lead Temperature (TL) (Soldering, 10 seconds) 260 °C Operating Range (VDD )3 V DC to 15 VDC Operating Temperature Range CD4001BC, CD4011BC −40°C to +85°C Symbol Parameter Conditions −40°C +25°C +85°C Units Min Max Min Typ Max Min Max IDD Quiescent Device V DD = 5V, VIN = VDD or VSS 1 0.004 1 7.5 µA Current V DD = 10V, VIN = VDD or VSS 20 . 0 0 5 2 1 5 µA VDD = 15V, VIN = VDD or VSS 40 . 0 0 6 4 3 0 µA VOL LOW Level V DD = 5V 0.05 0 0.05 0.05 V Output Voltage V DD = 10V |I O | < 1 µA 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V VOH HIGH Level V DD = 5V 4.95 4.95 5 4.95 V Output Voltage V DD = 10V |I O | < 1 µA 9.95 9.95 10 9.95 V VDD = 15V 14.95 14.95 15 14.95 V VIL LOW Level V DD = 5V, VO = 4.5V 1.5 2 1.5 1.5 V Input Voltage V DD = 10V, VO = 9.0V 3.0 4 3.0 3.0 V VDD = 15V, VO = 13.5V 4.0 6 4.0 4.0 V VIH HIGH Level V DD = 5V, VO = 0.5V 3.5 3.5 3 3.5 V Input Voltage V DD = 10V, VO = 1.0V 7.0 7.0 6 7.0 V VDD = 15V, VO = 1.5V 11.0 11.0 9 11.0 V IIN Input Current V DD = 15V, VIN = 0V −0.30 −10−5 −0.30 −1.0 µA VDD = 15V, VIN = 15V 0.30 10 −5 0.30 1.0 µA Symbol Parameter Conditions Typ Max Units tPHL Propagation Delay Time, V DD = 5V 120 250 ns HIGH-to-LOW Level V DD = 10V 50 100 ns VDD = 15V 35 70 ns tPLH Propagation Delay Time, V DD = 5V 110 250 ns LOW-to-HIGH Level V DD = 10V 50 100 ns VDD = 15V 35 70 ns tTHL , tTLH Transition Time V DD = 5V 90 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns C IN Average Input Capacitance Any Input 5 7.5 pF C PD Power Dissipation Capacity Any Gate 14 pF www.sycelectronica.com.ar

CD4011BC: TA= 25°C, Input tr; tf = 20 ns. CL = 50 pF , RL = 200k. Typical T emperature Coefficient is 0.3%/°C. Note 5: AC Parameters are guaranteed by DC correlated testing. Typical Performance Characteristics Typical Transfer Characteristics Typical Transfer Characteristics Typical Transfer Characteristics Symbol Parameter Conditions Typ Max Units tPHL Propagation Delay, V DD = 5V 120 250 ns HIGH-to-LOW Level V DD = 10V 50 100 ns VDD = 15V 35 70 ns tPLH Propagation Delay, V DD = 5V 85 250 ns LOW-to-HIGH Level V DD = 10V 40 100 ns VDD = 15V 30 70 ns tTHL , tTLH T ransition Time V DD = 5V 90 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns C IN Average Input Capacitance Any Input 5 7.5 pF C PD Power Dissipation Capacity Any Gate 14 pF www.sycelectronica.com.ar

Typical Transfer Characteristics www.sycelectronica.com.ar

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Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.sycelectronica.com.ar

CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A www.sycelectronica.com.ar