C8051F063

C8051F060_07 SILABS | Alldatasheet

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Mixed Signal ISP Flash MCU Family Preliminary Rev. 1.2 7/04 Copyright © 2004 by Silicon Laboratories C8051F060/1/2/3/4/5/6/7 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Peripherals - Two 16-Bit SAR ADCs

• 16-bit resolution
• ±0.75 LSB INL, guaranteed no missing codes
• Programmable throughput up to 1 Msps
• Operate as two single-ended or one differential con- verter
• Direct memory access; data stored in RAM without software overhead
• Data-dependent windowed interrupt generator - 10-bit SAR ADC (C8051F060/1/2/3)
• Programmable throughput up to 200 ksps
• 8 external inputs, single-ended or differential
• Built-in temperature sensor - Two 12-bit DACs (C8051F060/1/2/3)
• Can synchronize outputs to timers for jitter-free wave- form generation - Three Analog Comparators
• Programmable hysteresis/response time - Voltage Reference - Precision VDD Monitor/Brown-Out Detector On-Chip JTAG Debug & Boundary Scan - On-chip debug circuitry facilitates full-speed, non- intrusive in-circuit/in-system debugging - Provides breakpoints, single-stepping, watchpoints, stack monitor; inspect/modify memory and registers - Superior performance to emulation systems using ICE-chips, target pods, and sockets - IEEE1149.1 compliant boundary scan - Complete development kit High Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instruction set in 1 or 2 system clocks - Up to 25 MIPS throughput with 25 MHz clock - Flexible Interrupt sources Memory - 4352 Bytes internal data RAM (4 k + 256) - 64 kB (C8051F060/1/2/3/4/5), 32 kB (C8051F066/7) Flash; In-system programmable in 512-byte sectors - External 64 kB data memory interface with multi- plexed and non-multiplexed modes (C8051F060/2/ 4/6) Digital Peripherals - 59 general purpose I/O pins (C8051F060/2/4/6) - 24 general purpose I/O pins (C8051F061/3/5/7) - Bosch Controller Area Network (CAN 2.0B - C8051F060/1/2/3) - Hardware SMBus™ (I2C™ Co mpatible), SPI™, and two UART serial ports available concurrently - Programmable 16-bit counter/timer array with 6 capture/compare modules - 5 general purpose 16-bit counter/timers - Dedicated watchdog timer; bi-directional reset pin Clock Sources - Internal calibrated precision oscillator: 24.5 MHz - External oscillator: Crystal, RC, C, or clock Multiple power saving sleep and shutdown modes 100-Pin and 64-Pin TQFP Packages Available Temperature Range: -40 to +85 °C JTAG64/32 kB ISP FLASH 4352 B SRAM SANITY CONTROL 16-bit

1 Msps

HIGH-SPEED CONTROLLER CORE DEBUG CIRCUITRY INTERRUPTS

8051 CPU

(25MIPS) 10-bit 200ksps ADC Port 4 Port 5 Port 6 Port 7 External Memory Interface 100 pin Only UART0 SMBus SPI Bus PCA Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 UART1 CAN 2.0B C8051F060/1/2/3 AMUX VREF DMA Interface 16-bit S 12-Bit DAC Port 3+ C8051F060/1/2/3 Only

2 Rev. 1.2

Rev. 1.2 3 Table of Contents

4 Rev. 1.2

Rev. 1.2 5

6 Rev. 1.2 19.2.5.Using CAN0ADR, CAN0DATH, and CANDATL To Access CAN Registers 229

Rev. 1.2 7

8 Rev. 1.2

16 Rev. 1.2

Rev. 1.2 17 List of Tables

18 Rev. 1.2 Table 23.1.Timer Settings for Standard Baud Rates Using the Internal Oscillator 284 Table 23.2.Timer Settings for Standard Baud Rates Using an External Oscillator 284 Table 23.3.Timer Settings for Standard Baud Rates Using an External Oscillator 285 Table 23.4.Timer Settings for Standard Baud Rates Using an External Oscillator 285 Table 23.5.Timer Settings for Standard Baud Rates Using an External Oscillator 286 Table 23.6.Timer Settings for Standard Baud Rates Using an External Oscillator 286

Rev. 1.2 19 1. System Overview The C8051F06x family of devices are fully integrated mixed-signal System-on-a-Chip MCUs with 59 digital I/O pins (C8051F060/2/4/6) or 24 digital I/O pins (C8051F061/3/5/7), and two integrated 16-bit 1 Msps ADCs. Highlighted features are listed below; refer to Table 1.1 for specific product feature selection.

• High-Speed pipelined 8051-compatible CIP-51 microcontroller core (up to 25 MIPS)
• Two 16-bit 1 Msps ADCs with a Direct Memory Access controller
• Controller Area Network (CAN 2.0B ) Controller with 32 message objects, each with its own indentifier mask (C8051F060/1/2/3)
• In-system, full-speed, non-intrusive debug interface on-chip
• 10-bit 200 ksps ADC with PGA and 8-channel analog multiplexer (C8051F060/1/2/3)
• Two 12-bit DACs with programmable update scheduling (C8051F060/1/2/3)
• 64 kB (C8051F060/1/2/3/4/5) or 32 kB (C8051 F066/7) of in-system programmable Flash memory
• 4352 (4096 + 256) bytes of on-chip RAM
• External Data Memory Interf ace with 64 kB direct address space (C8051F060/2/4/6)
• SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware
• Five general purpose 16-bit Timers
• Programmable Counter/Timer Array with six capture/compare modules
• On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor With on-chip VDD monitor, Watchdog Timer, and clock oscillator, the C8051F06x family of devices are truly stand-alone System-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and con- figured by user firmware. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resource s), full speed, in-circuit debugging using the production MCU installed in the final application. This debug system supports inspec- tion and modification of memory and registers, settin g breakpoints, watchpoints, single stepping, Run and Halt commands. All analog and digital peripherals are fully functional while debugging using JTAG. Each MCU is specified for 2.7 to 3.6 V operation over the industrial temperature range (-45 to +85 °C). The C8051F060/2/4/6 are available in a 100-pin TQFP pa ckage and the C8051F061/3/5/7 are available in a

20 Rev. 1.2 Table 1.1. Product Selection Guide MIPS (Peak) Flash Memory RAM External Memory Interface SMBus/I2C and SPI CAN UARTS Timers (16-bit) Programmable Counter Array Digital Port I/O’s 16-bit 1 Msps ADC Typical INL (LSBs) 10-bit 200 ksps ADC Inputs Voltage Reference Temperature Sensor DAC Resolution (bits) DAC Outputs Analog Comparators Package C8051F060 25 64 k 4352 333 25 3 59 ±0.75 8 33 12 2 3 100 TQFP C8051F061 25 64 k 4352 - 33 25 3 24 ±0.75 8 33 12 2 3 64 TQFP C8051F062 25 64 k 4352 333 25 3 59 ±1.5 8 33 12 2 3 100 TQFP C8051F063 25 64 k 4352 - 33 25 3 24 ±1.5 8 33 12 2 3 64 TQFP C8051F064 25 64 k 4352 33 -25 3 59 ±0.75 - 3 - - - 3 100 TQFP C8051F065 25 64 k 4352 - 3 -25 3 24 ±0.75 - 3 --- 3 6 4 T Q F P C8051F066 25 32 k 4352 33 -25 3 59 ±0.75 - 3 - - - 3 100 TQFP C8051F067 25 32 k 4352 - 3 -25 3 24 ±0.75 - 3 --- 3 6 4 T Q F P

Rev. 1.2 21 Figure 1.1. C8051F060 / C8051F062 Block Diagram P0, P1, P2, P3 Latches JTAG Logic TCK TMS TDI TDO UART1 SMBus SPI Bus PCA 64k byte FLASH 256 byte RAM VDD Monitor SFR Bus C o r e Timers 0, 1, 2,3,4 Drv C R O S S B A RReset/RST XTAL1 XTAL2 External Os cillator Circuit Sys tem Clock Trimmed Internal Os cillator Digital Power Analog Power Debug HW Boundary Scan 4k byte RAM P2.0 P2.7 P1.0/ AIN2.0 P1.7/ AIN2.7 P0.0 P0.7 Drv Drv Data Bus Addres s Bus Bus Control DAC0 DAC0 (12-Bit) VREFVREF UART0 P3.0 P3.7 Drv ADC2 2 0 0 ksp s (10-Bit) A M U X MONEN WDT VREF2 VREFD P4 Latch P7 Latch P5 Latch P6 Latch P7.0 P7.7 DRV P5.0 P5.7 DRV P6.0 P6.7 DRV DRV P4.5 P4.6 P4.7 External Data Memory Bus Addr[7:0] Addr[15:8] Ctrl Latch Data Latch CANTX CANRX CAN 2.0B ADC0 1Ms ps (16-Bit) VRGND0 A D C D A T A A D C D A T A Σ + D I F F DMA Interface DAC1 Temp Sens or EMIF Control VDD VDDVDD DGND DGND DGND AV+ AGND VREF0 AGND AV+ VRGND VREF1 AGND AVDD AIN0 AIN0G VBGAP 0CNVSTR ADC1 1Ms ps (16-Bit) AGND AV+ AIN1 AIN1G VBGAP 1CNVSTR 32X136 CANRAM P2.7 P2.6+-CP0 P2.3 P2.2+ -CP1 P2.5 P2.4+-CP2

22 Rev. 1.2 Figure 1.2. C8051F061 / C8051F063 Block Diagram Drv P0, P1, P2, P3 Latches JTAG Logic TCK TMS TDI TDO UART1 SMBus SPI Bus PCA 64k byte FLASH 256 byte RAM VDD Monitor SFR Bus C o r e Timers 0, 1, 2,3,4 Drv C R O S S B A R Reset/RST XTAL1 XTAL2 External Os cillator Circuit Sys tem Clock Trimmed Internal Os cillator Digital Power Analog Power Debug HW Boundary Scan 4k byte RAM P2.0 P2.7 P1.0/ AIN2.0 P1.7/ AIN2.7 P0.0 P0.7 Drv Drv DAC0 DAC0 (12-Bit) VREFVREF UART0 ADC2 2 0 0 ksp s (10-Bit) A M U X MONEN WDT VREF2 VREF2 External Data Memory Bus CANTX CANRX CAN 2.0B ADC0 1Ms ps (16-Bit) VRGND0 A D C D A T A A D C D A T A Σ + D I F F DMA Interface DAC1 Temp Sens or EMIF Control VDD VDDVDD DGND DGNDDGND AV+ AGND VREF0 AGNDAV+ VRGND VREF1 AGND AVDD AIN0 AIN0G VBGAP 0CNVSTR ADC1 1Ms ps (16-Bit) AGND AV+ AIN1 AIN1G VBGAP 1CNVSTR 32X136 CANRAM P2.7 P2.6+-CP0 P2.3 P2.2+-CP1 P2.5 P2.4+-CP2 P4 Latch P7 Latch P5 Latch P6 Latch DRV DRV DRV DRV Addr[7:0] Addr[15:8] Ctrl Latch Data Latch

Rev. 1.2 23 Figure 1.3. C8051F064 / C8051F066 Block Diagram P0, P1, P2, P3 Latches JTAG Logic TCK TMS TDI TDO UART1 SMBus SPI Bus PCA 256 byte RAM VDD Monitor SFR Bus C o r e Timers 0, 1, 2,3,4 Drv C R O S S B A R Reset/RST XTAL1 XTAL2 External Oscillator Circuit System Clock Trimmed Internal Oscillator Digital Power Analog Power Debug HW Boundary Scan 4kbyte RAM P2.0 P2.7 P1.0 P1.7 P0.0 P0.7 Drv Drv Data Bus Address Bus Bus Control VREFVREF UART0 P3.0 P3.7 Drv MONEN WDT P4 Latch P7 Latch P5 Latch P6 Latch P7.0 P7.7 DRV P5.0 P5.7 DRV P6.0 P6.7 DRV DRV P4.5 P4.6 P4.7 External Data Memory Bus Addr[7:0] Addr[15:8] Ctrl Latch Data Latch ADC0 1Msps (16-Bit) VRGND0 A D C D A T A A D C D A T A Σ + D I F F DMA Interface EMIF Control VDDVDDVDD DGNDDGNDDGND AV+ AGND VREF0 AGNDAV+ VRGND1VREF1 AGNDAVDD AIN0 AIN0G VBGAP0 CNVSTR0 ADC1 1Msps (16-Bit) AGNDAV+ AIN1 AIN1G VBGAP1 CNVSTR1 P2.3 P2.2+-CP1 P2.5 P2.4+-CP2 P2.7 P2.6+-CP0 FLASH Memory 64k byte (C8051F064) 32k byte (C8051F066)

24 Rev. 1.2 Figure 1.4. C8051F065 / C8051F067 Block Diagram Drv P0, P1, P2, P3 Latches JTAG Logic TCK TMS TDI TDO UART1 SMBus SPI Bus PCA FLASH Memory 64k byte (C8051F065) 32k byte (C8051F067) 256 byte RAM VDD Monitor SFR Bus C o r e Timers 0, 1, 2,3,4 Drv C R O S S B A R Reset/RST XTAL1 XTAL2 External Oscillator Circuit System Clock Trimmed Internal Oscillator Digital Power Analog Power Debug HW Boundary Scan 4kbyte RAM P2.0 P2.7 P1.0 P1.7 P0.0 P0.7 Drv Drv VREFVREF UART0 MONEN WDT External Data Memory BusADC0 1Msps (16-Bit) VRGND0 A D C D A T A A D C D A T A Σ + D I F F DMA Interface EMIF Control VDDVDDVDD DGNDDGNDDGND AV+ AGND VREF0 AGNDAV+ VRGND1VREF1 AGNDAVDD AIN0 AIN0G VBGAP0 CNVSTR0 ADC1 1Msps (16-Bit) AGNDAV+ AIN1 AIN1G VBGAP1 CNVSTR1 P4 Latch P7 Latch P5 Latch P6 Latch DRV DRV DRV DRV Addr[7:0] Addr[15:8] Ctrl Latch Data Latch P2.3 P2.2+-CP1 P2.5 P2.4+-CP2 P2.7 P2.6+-CP0

Rev. 1.2 25 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F06x family of devices ut ilizes Silicon Labs' proprietary CI P-51 microcontroller core. The CIP- 51 is fully compatible with the MC S-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The core has all the peripherals included with a standard 8052, including five 16-bit counter/timers, two fu ll-duplex UARTs, 256 bytes of intern al RAM, 128 byte Special Function Register (SFR) address space, and bit-addressable I/O Ports. 1.1.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture. In a standa rd 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core exe- cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5 shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks. Figure 1.5. Comparison of Peak MCU Execution Speeds Clocks to Execute 1 22 / 333 / 444 / 55 8 Number of Instructions 2 6 5 051 47 3 1 2 1 ADuC812 8051 (16 MHz clk) Philips 80C51 (33 MHz clk) Microchip PIC17C75x (33 MHz clk) Silicon Labs CIP-51 (25 MHz clk) MIPS

26 Rev. 1.2 1.1.3. Additional Features The C8051F06x MCU family includes several key enhancements to the CIP-51 core and peripherals to improve overall performance and ease of use in end applications. The extended interrupt handler provides 22 interrupt sources into the CIP-51, allowing the numerous ana- log and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. There are up to seven reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock detector, a voltage level detection from Compar ator0, a forced software reset, the CNVSTR2 input pin, and the /RST pin. The /RST pin is bi-directio nal, accommodating an external reset, or allowing the internally generated POR to be output on the /RST pin. Each reset source except for the VDD monitor and Reset Input pin may be disabled by the user in so ftware; the VDD monitor is enabled/disabled via the MONEN pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during MCU initialization. The MCU has an internal, stand alone clock generator which is used by default as the system clock after any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) exter- nal crystal source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed. Figure 1.6. On-Board Clock and Reset WDT XTAL1 XTAL2 OSC Internal Clock Generator System Clock CIP-51 Microcontroller Core Missing Clock Detector (one- shot) WDT Strobe Software Reset Extended Interrupt Handler Clock Select /RST+ VDD Supply Reset Timeout (wired-OR) System Reset Supply Monitor PRE Reset Funnel CP0+ Comparator0 CP0- (Port I/O) Crossbar CNVSTR2 (CNVSTR reset enable) (CP0 reset enable) EN WDT Enable ENMCD Enable (wired-OR) VDD Monitor reset enable

Rev. 1.2 27 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data addr ess configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The CIP-51 SFR address space contains up to 256 SFR Pages. In this way, the CIP-51 MCU can accommodate the many SFRs required to control and configure the various peripherals featured on the device. The lower 128 bytes of RAM are accessible via direct and indire ct addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. The CIP-51 in the C8051F060/1/2/3/ 4/5/6/7 MCUs additionally has an on-chip 4 kB RAM block. The on- chip 4 kB block can be addressed over the entire 64 k external data memory address range (overlapping 4 k boundaries). The C8051F060/2/4/6 also have an external memory interfac e (EMIF) for accessing off- chip data memory or memory-mapped peripherals. External data memory address space can be mapped to on-chip memory only, off-chip memory only, or a combination of the two (addresses up to 4 k directed to on-chip, above 4 k directed to EMIF). The EMIF is also configurable for multiplexed or non-multiplexed address/data lines. The MCU’s program memory consists of 64 k (C8051F060/1/2/3/4/5) or 32 k (C8051F066/7) of Flash. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip program- ming voltage. On the C8051F060/1/2/3/4/5, th e 1024 bytes from addresses 0xFC00 to 0xFFFF are reserved. There is also a single 128 byte Scratchpad Memory sector on all devices which may be used by firmware for non-volatile data storage. See Figure 1.7 for the MCU system memory map. Figure 1.7. On-Chip Memory Map PROGRAM/DATA MEMORY (FLASH) (Direct and Indirect Addressing) 0x00 0x7F Upper 128 RAM (Indirect Addressing Only) 0x80 0xFF Special Function Registers (Direct Addressing Only) DATA MEMORY (RAM) General Purpose Registers 0x1F 0x20 0x2F Bit Addressable Lower 128 RAM (Direct and Indirect Addressing) 0x30 INTERNAL DATA ADDRESS SPACE EXTERNAL DATA ADDRESS SPACE XRAM - 4096 Bytes (accessable using MOVX instruction)0x0000 0x0FFF Off-chip XRAM space (C8051F060/2/4/6 Only) 0x1000 0xFFFF FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 0xFFFF RESERVED0xFC00 0xFBFF Scrachpad Memory (data only) 0x1007F 0x10000 Up To

256 SFR Pages

(In-System Programmable in 512 Byte Sectors)0x0000 0xFFFF RESERVED 0x8000 0x7FFF Scrachpad Memory (data only) 0x1007F 0x10000 C8051F066/7

28 Rev. 1.2 1.3. JTAG Debug and Boundary Scan The C8051F06x family has on-chip JTAG bounda ry scan and debug circ uitry that provides non-intrusive, full speed, in-circuit debugging using the produc tion part installed in the end application , via the four-pin JTAG interface. The JTAG port is fully compliant to IEEE 1149.1, providing full boundary scan for test and manufacturing purposes. Silicon Laboratories' debugging system supports in spection and modification of memory and registers, breakpoints, watchpoints, a stack monitor, and single stepping. No additional target RAM, program mem- ory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADCs and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized with instruction execution. The C8051F060DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with t he C8051F06x MCUs. The kit includes a Windows (95 or later) development environment, a serial adapter for connecting to the JTAG port, and a target application board with a C8051F060 MCU installed. All of th e necessary communication cables and a wall-mount power supply are also supplied with the development kit. Silicon Labs’ debug environment is a vastly supe- rior configuration for developing and debugging embedded applications compared to standard MCU emu- lators, which use on-board "ICE Chips" and target cables and require the MCU in the application board to be socketed. Silicon Labs' debug environment both increases ease of use and preserves the performance of the precision, on-chip analog peripherals. Figure 1.8. Development/In-System Debug Diagram TARGET PCB Serial Adapter C8051 F060 JTAG (x4), VDD, GND WINDOWS 95 OR LATER Silicon Labs Integrated Development Environment

Rev. 1.2 29 1.4. Programmable Digital I/O and Crossbar Three standard 8051 Ports (0, 1, and 2) are availa ble on the MCUs. The C805 1F060/2/4/6 have 4 addi- tional 8-bit ports (3, 5, 6, and 7), and a 3-bit port (port 4) for a total of 59 general-purpose I/O Pins. The Ports behave like the standard 8051 with a few enhancements. Each port pin can be configured as either a push-pull or open-drain output. Also, the "weak pull-ups" which are normally fixed on an 8051 can be globally disabl ed, providing additional powe r saving capabilities for low-power applications. Perhaps the most unique enhancement is the Digital Crossbar. This is a large digital switching network that allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3. (See Figure 1.9) Unlike microcontrollers with standard mu ltiplexed digital I/O port s, all combinations of functions are supported with all package options offered. The on-chip counter/timers, serial buses, HW interrup ts, comparator outputs, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular application. Figure 1.9. Digital Crossbar Diagram External Pins Digital Crossba r Priority Decoder SMBus SPI 4 UART0 PCA T0, T1, T2, T2EX, T3, T3EX, T4,T4EX, /INT0, /INT1 P1.0 P1.7 P2.0 P2.7 P0.0 P0.7 Highest Priority Lowest Priority Comptr. Outputs (Internal Digital Signals) Highest Priority Lowest Priority UART1 P3.0 P3.7 P0MDOUT, P1MDOUT, P2MDOUT, P3MDOUT Registers XBR0, XBR1, XBR2, XBR3 P1MDIN, P2MDIN, P3MDIN Registers I/O Cells I/O Cells I/O Cells I/O Cells Port Latches (P2.0-P2.7) (P1.0-P1.7) (P0.0-P0.7) (P3.0-P3.7) To ADC2 Input (C8051F060/1/2/3) To Comparators /SYSCLK CNVSTR2 C8051F060/2/4/6 Only

30 Rev. 1.2 1.5. Programmable Counter Array The C8051F06x MCU family includes an on-board Pr ogrammable Counter/Timer Array (PCA) in addition to the five 16-bit general purpose counter/timers. Th e PCA consists of a dedica ted 16-bit counter/timer time base with 6 programmable capture/compare modul es. The timebase is clocked from one of six sources: the system clock divided by 12, the system clock divided by 4, Time r 0 overflow, an External Clock Input (ECI pin), the system clock, or the external oscillator source divided by 8. Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. The PCA Capture/Compare Module I/O and External Clock Input are routed to the MCU Port I/ O via the Digital Crossbar. Figure 1.10. PCA Block Diagram Capture/Compare Module 1 Capture/Compare Module 0 Capture/Compare Module 2 Capture/Compare Module 3 CEX1 ECI Crossbar CEX2 CEX3 CEX0 Port I/O 16-Bit Counter/TimerPCA CLOCK MUX SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 Capture/Compare Module 4 CEX4 Capture/Compare Module 5 CEX5

Rev. 1.2 31 1.6. Controller Area Network The C8051F060/1/2/3 devices feature a Controller Ar ea Network (CAN) controller that implements serial communication using the CAN protoc ol. The CAN controller facilitates communication on a CAN network in accordance with the Bosch specification 2.0A (basic CAN) and 2.0B (full CAN). The CAN controller con- sists of a CAN Core, Message RAM (separate from the C8051 RAM), a message handler state machine, and control registers. The CAN controller can operate at bit rates up to 1 Mbit/second. Silicon Labs CAN has 32 message objects each having its own identifier mask used for acceptance filtering of received messages. Incoming data, message objects and identifier masks are stored in the CAN message RAM. All protocol functions for transmission of data and acceptance filtering is performed by the CAN controller and not by the C8051 MCU. In this way, minimal CPU bandwidth is used for CAN communication. The C8051 configures the CAN controller, accesses received data, and passes data for transmission via Special Function Registers (SFR) in the C8051. Figure 1.11. CAN Controller Overview Message Handler REGISTERSMessage RAM (32 Message Objects) CAN Core TX RX CAN Controller C M C U Interrupt S F R CANTX CANRX C8051F060/1/2/3

32 Rev. 1.2 1.7. Serial Ports The C8051F06x MCU Family includes two Enhanced Full-Duplex UARTs, an enhanced SPI Bus, and SMBus/I2C. Each of the serial bu ses is fully implemented in hardwar e and makes extensive use of the CIP-51's interrupts, thus requiring very little intervention by the CPU. The serial buses do not "share" resources such as timers, interrupts, or Port I/O, so any or all of the serial buses may be used together with any other.

Rev. 1.2 33 1.8. 16-Bit Analog to Digital Converters The C8051F060/1/2/3/4/5/6/7 devices have two on- chip 16-bit SAR ADCs (ADC0 and ADC1), which can be used independently in single-ended mode, or to gether in differential mode. ADC0 and ADC1 can directly access on-chip or external RAM, using the DMA interface. With a maximum throughput of 1 Msps, the ADCs offer 16 bit performance with two availabl e linearity grades. ADC0 and ADC1 each have the capability to use dedicated, on-chip voltage reference circuitry or an external voltage reference source. The ADCs are under full control of the CIP-51 microc ontroller via the associated Special Function Regis- ters. The system controller can also put the ADCs into shutdown mode to save power. Conversions can be started in four ways; a software command, an overflow of Timer 2, an overflow of Timer 3, or an external signal input. This flexibility allows the start of conversion to be triggered by software events, external HW signals, or a periodic timer overflow signal. The two ADCs can operate independently, or be synchronized to perform conversions at the same time. Conversion completions are indicated by sta- tus bits, and can generate interrupts. The resulting 16-bit data words are latched into SFRs upon comple- tion of a conversion. A DMA interface is also provi ded, which can gather conversions from the ADCs, and directly store them to on-chip or external RAM. ADC0 also contains Window Compare registers, whic h can be configured to interrupt the controller when ADC0 data is within or outside of a specified range. ADC0 can monitor a key voltage continuously in back- ground mode, and not interrupt the controller unless the converted data is within the specified window. Figure 1.12. 16-Bit ADC Block Diagram AIN0G REF AIN0 Start Conversion Timer 3 Overflow Timer 2 Overflow Write to AD1BUSY CNVSTR1 16-Bit SAR ADC0 (DC, -0.2 to 0.6 V) AIN1G REF AIN1 Start Conversion 16-Bit SAR ADC1 (DC, -0.2 to 0.6 V) Write to AD0BUSY Timer 3 Overflow Timer 2 Overflow Write to AD0BUSY CNVSTR0 Configuration and Control Registers DMA Interface ADC0 Window Compare Logic ADC Data Registers

34 Rev. 1.2 1.9. 10-Bit Analog to Digital Converter The C8051F060/1/2/3 devices have an on-board 10-bit SAR ADC (ADC2) with a 9-channel input multi- plexer and programmable gain amplifier. This ADC features a 200 ksps maximum throughput and true 10- bit performance with an INL of ±1LSB. Eight input pi ns are available for measurement and can be pro- grammed as single-ended or differential inputs. Addi tionally, the on-chip temperature sensor can be used as an input to the ADC. The ADC is under full control of the CIP-51 microcontroller via the Special Function Registers. The ADC2 voltage reference is selected between the analog power supply (AV+) and the exter- nal VREF2 pin. User software may put ADC2 into shutdown mode to save power. A flexible conversion scheduling s ystem allows ADC2 conv ersions to be initiated by software commands, timer overflows, or an external input signal. Conver sion completions are indicated by a status bit and an interrupt (if enabled), and the resulting 10-bit data word is latched into two SFR locations upon completion. ADC2 also contains Window Compare registers, whic h can be configured to interrupt the controller when ADC2 data is within or outside of a specified range. ADC2 can monitor a key voltage continuously in back- ground mode, and not interrupt the controller unless the converted data is within the specified window. Figure 1.13. 10-Bit ADC Diagram 9-to-1 AMUX AIN2.0 AIN2.1 AIN2.2 AIN2.3 AIN2.4 AIN2.5 AIN2.6 AIN2.7 Configuration and Control Registers Analog Multiplexer 10-Bit SAR ADC Start Conversion Timer 3 Overflow Timer 2 Overflow Write to AD2BUSY CNVSTR2 Input ADC Data Registers Conversion Complete Interrupt VREF2 Pin AV+ VREF Single-ended or Differential Measurement TEMP SENSOR AGND ADC2 Window Compare Logic

Rev. 1.2 35 1.10. 12-bit Digital to Analog Converters The C8051F060/1/2/3 MCUs have two integrated 12-bit Digital to Analog Converters (DACs). The MCU data and control interface to each DAC is via the Special Function Registers. The MCU can place either or both of the DACs in a low power shutdown mode. The DACs are voltage output mode and include a flex ible output scheduling mechanism. This scheduling mechanism allows DAC output updates to be forced by a software write or scheduled on a Timer 2, 3, or 4 overflow. The DAC voltage reference is supplied from the dedicated VREFD input pin on C8051F060/2 devices or via the VREF2 pin on C8051F061/3 devi ces, which is shared with ADC2. The DACs are espe- cially useful as references for the comparators or offsets for the differential inputs of the ADCs. Figure 1.14. DAC System Block Diagram DAC0 DAC1 VREF VREF CIP-51 and Interrupt Handler DAC0 DAC1 SFR's (Data and Control)

36 Rev. 1.2 1.11. Analog Comparators The C8051F060/1/2/3/4/5/6/7 MCUs include three an alog comparators on-chip. The comparators have software programmable hysteresis and response time. Ea ch comparator can generate an interrupt on its rising edge, falling edge, or both. The interrupts are capable of waking up the MCU from sleep mode, and Comparator 0 can be used as a reset source. The outp ut state of the comparators can be polled in soft- ware or routed to Port I/O pins via the Crossbar. Outputs from the comparator can be routed through the crossbar. The comparators can be programmed to a low power shutdown mode when not in use. Figure 1.15. Comparator Block Diagram CPn+ CPn- CIP-51 and Interrupt Handler CPn CPn Output (Port I/O) SFR's (Data and Control) CROSSBAR

3 Comparators

Port 2.[7:2]

Rev. 1.2 37 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Parameter Conditions Min Typ Max Units Ambient temperature under bias -55 125 °C Storage Temperature -65 150 °C Voltage on any pin (except VDD, AV+, AVDD, and Port 0) with respect to DGND -0.3 VDD + 0.3 V Voltage on any Port 0 Pin with respect to DGND. -0.3 5.8 V Voltage on VDD, AV+, or AVDD with respect to DGND -0.3 4.2 V Maximum Total current through VDD, AV+, AVDD, DGND, and AGND 800 mA Maximum output current sunk by any Port pin 100 mA Maximum output current sunk by any other I/O pin 50 mA Maximum output current sourced by any Port pin 100 mA Maximum output current sourced by any other I/O pin 50 mA * Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

38 Rev. 1.2 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics -40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter Conditions Min Typ Max Units Analog Supply Voltage (AV+, AVDD) (Note 1) 2.7 3.0 3.6 V Digital Supply Voltage (VDD) 2.7 3.0 3.6 V Analog-to-Digital Supply Delta (|VDD - AV+| or |VDD - AVDD|) 0.5 V Supply Current from Analog Peripherals (active) Internal REF, ADC, DAC, Com- parators all enabled. (Note 2) 14 mA Supply Current from Analog Peripherals (inactive) Internal REF, ADC, DAC, Com- parators all disabled, oscillator disabled. 0.2 µA Supply Current from CPU and Digital Peripherals (CPU active) (Note 3) VDD=2.7 V, Clock=25 MHz VDD=2.7 V, Clock=1 MHz VDD=2.7 V, Clock=32 kHz VDD=3.0 V, Clock=25 MHz VDD=3.0 V, Clock=1 MHz VDD=3.0 V, Clock=32 kHz 0.7 1.0 mA mA µA mA mA µA Supply Current from CPU and Digital Peripherals (CPU inac- tive, not accessing Flash) (Note 3) VDD=2.7 V, Clock=25 MHz VDD=2.7 V, Clock=1 MHz VDD=2.7 V, Clock=32 kHz VDD=3.0 V, Clock=25 MHz VDD=3.0 V, Clock=1 MHz VDD=3.0 V, Clock=32 kHz 0.5 0.8 mA mA µA mA mA µA Supply Current with all systems shut down Oscillator not running 0.2 µA VDD Supply RAM Data Reten- tion Voltage 1.5 V SYSCLK (System Clock) (Note 4) 0 25 MHz Specified Operating Tempera- ture Range -40 +85 °C Note 1: Analog Supply AV+ must be greater than 1 V for VDD monitor to operate. Note 2: Internal Oscillator and VDD Monitor current not included. Individual supply current contributions for each peripheral are listed in the chapter. Note 3: Current increases linearly with supply Voltage. Note 4: SYSCLK must be at least 32 kHz to enable debugging.

Rev. 1.2 39 4. Pinout and Package Definitions Table 4.1. Pin Definitions Name Pin Numbers Type DescriptionF060 F061 F064 F065 F062 F063 F066 F067 VDD 37, 64, 26, 40, 37, 64, 26, 40, Digital Supply Voltage. Must be tied to +2.7 to +3.6 V. DGND 38, 63, 27, 39, 38, 63, 27, 39, Digital Ground. Must be tied to Ground. AV+ 11, 16, 7, 10, 11, 16, 7, 10, Analog Supply Voltage. Must be tied to +2.7 to +3.6 V. AVDD 13 23 13 23 Analog Supply Voltage. Must be tied to +2.7 to +3.6 V. AGND 10, 14, 17, 23 6, 11, 19, 22 10, 14, 17, 23 6, 11, 19, 22 Analog Ground. Must be tied to Ground. TMS 96 52 96 52 D In JTAG Test Mode Select with internal pull-up. TCK 97 53 97 53 D In JTAG Test Clock with internal pull-up. TDI 98 56 98 56 D In JTAG Test Data Input with internal pull-up. TDI is latched on the rising edge of TCK. TDO 99 57 99 57 D Out JTAG Test Data Outp ut with internal pull-up. Data is shifted out on TDO on the falling edge of TCK. TDO output is a tri-state driver. /RST 100 58 100 58 D I/O Device Reset. Open-drain output of internal VDD monitor. Is driven low when VDD is <2.7 V and MONEN is high. An external source can initiate a system reset by driving this pin low. XTAL1 26 20 26 20 A In Crystal Input. This pin is the return for the internal oscillator circuit for a crystal or ceramic resonator. For a precision internal clock, connect a crystal or ceramic resonator from XTAL1 to XTAL2. If over- driven by an external CMOS clock, this becomes the system clock. XTAL2 27 21 27 21 A Out Crystal Output. This pin is the excitation driver for a crystal or ceramic resonator. MONEN 28 63 28 63 D In VDD Monitor Enable. When tied high, this pin enables the internal VDD monitor, which forces a system reset when VDD is < 2.7 V. When tied low, the internal VDD monitor is disabled. Recom- mended configuration is to connect directly to VDD. VREF 4 61 4 61 A Out Bandgap Voltage Reference Output VREF0 21 15 21 15 A I/O Bandgap Voltage Reference Output for ADC0. ADC0 Voltage Reference Input.

40 Rev. 1.2 VRGND0 20 14 20 14 A In ADC0 Voltage Reference Ground. This pin should be grounded if using the ADC. VBGAP0 22 16 22 16 A Out ADC0 Bandgap Bypass Pin. VREF1 6 2 6 2 A I/O Bandgap Voltage Reference Output for ADC1. ADC1 Voltage Reference Input. VRGND1 7 3 7 3 A In ADC1 Voltage Refer ence Ground. This pin should be grounded if using the ADC. VBGAP1 5 1 5 1 A Out ADC1 Bandgap Bypass Pin. VREF2 2 A In ADC2 Voltage Reference Input. 62 A In ADC2, DAC0, and DAC1 Voltage Reference Input. VREFD 3 A In DAC0 and DAC1 Voltage Reference Input. AIN0 18 12 18 12 A In ADC0 Signal Input (See ADC0 Specification for complete description). AIN0G 19 13 19 13 A In ADC0 DC Bias In put (See ADC0 Specification for complete description). AIN1 9 5 9 5 A In ADC1 Signal Input (See ADC1 Specification for complete description). AIN1G 8 4 8 4 A In ADC1 DC Bias Input (See ADC1 Specification for complete description). CNVSTR0 15 9 15 9 D In External Conversion Start Source for ADC0 CNVSTR1 12 8 12 8 D In External Conversion Start Source for ADC1 CANTX 94 59 D Out Controller Area Network Transmit Output. CANRX 95 60 D In Controller Ar ea Network Receive Input. DAC0 25 17 A Out Digital to Analog Converter 0 Voltage Output. (See DAC Specification for complete description). DAC1 1 64 A Out Digital to Analog Converter 1 Voltage Output. (See DAC Specification for complete description). P0.0 62 51 62 51 D I/O Port 0.0. See Port Input/Output section for complete description. P0.1 61 50 61 50 D I/O Port 0.1. See Port Input/Output section for complete description. P0.2 60 49 60 49 D I/O Port 0.2. See Port Input/Output section for complete description. P0.3 59 48 59 48 D I/O Port 0.3. See Port Input/Output section for complete description. P0.4 58 47 58 47 D I/O Port 0.4. See Port Input/Output section for complete description. Table 4.1. Pin Definitions (Continued) Name Pin Numbers Type DescriptionF060 F061 F064 F065 F062 F063 F066 F067

Rev. 1.2 41 P0.5 57 46 57 46 D I/O Port 0.5. See Port Input/Output section for complete description. P0.6 56 45 56 45 D I/O Port 0.6. See Port Input/Output section for complete description. P0.7 55 44 55 44 D I/O Port 0.7. See Port Input/Output section for complete description. P1.0/AIN2.0 36 33 36 33 D I/O A In Port 1.0. See Port Input/Output section for complete description. ADC2 Input Channel 0 (C8051F060/1/2/3 Only). P1.1/AIN2.1 35 32 35 32 D I/O A In Port 1.1. See Port Input/Output section for complete description. ADC2 Input Channel 1 (C8051F060/1/2/3 Only). P1.2/AIN2.2 34 31 34 31 D I/O A In Port 1.2. See Port Input/Output section for complete description. ADC2 Input Channel 2 (C8051F060/1/2/3 Only). P1.3/AIN2.3 33 30 33 30 D I/O A In Port 1.3. See Port Input/Output section for complete description. ADC2 Input Channel 3 (C8051F060/1/2/3 Only). P1.4/AIN2.4 32 29 32 29 D I/O A In Port 1.4. See Port Input/Output section for complete description. ADC2 Input Channel 4 (C8051F060/1/2/3 Only). P1.5/AIN2.5 31 28 31 28 D I/O A In Port 1.5. See Port Input/Output section for complete description. ADC2 Input Channel 5 (C8051F060/1/2/3 Only). P1.6/AIN2.6 30 25 30 25 D I/O A In Port 1.6. See Port Input/Output section for complete description. ADC2 Input Channel 6 (C8051F060/1/2/3 Only). P1.7/AIN2.7 29 24 29 24 D I/O A In Port 1.7. See Port Input/Output section for complete description. ADC2 Input Channel 7 (C8051F060/1/2/3 Only). P2.0 46 43 46 43 D I/O Port 2.0. See Port Input/Output section for complete description. P2.1 45 42 45 42 D I/O Port 2.1. See Port Input/Output section for complete description. P2.2 44 41 44 41 D I/O Port 2.2. See Port Input/Output section for complete description. P2.3 43 38 43 38 D I/O Port 2.3. See Port Input/Output section for complete description. P2.4 42 37 42 37 D I/O Port 2.4. See Port Input/Output section for complete description. Table 4.1. Pin Definitions (Continued) Name Pin Numbers Type DescriptionF060 F061 F064 F065 F062 F063 F066 F067

42 Rev. 1.2 P2.5 41 36 41 36 D I/O Port 2.5. See Port Input/Output section for complete description. P2.6 40 35 40 35 D I/O Port 2.6. See Port Input/Output section for complete description. P2.7 39 34 39 34 D I/O Port 2.7. See Port Input/Output section for complete description. P3.0 54 54 D I/O Port 3.0. See Port I nput/Output section for complete description. P3.1 53 53 D I/O Port 3.1. See Port I nput/Output section for complete description. P3.2 52 52 D I/O Port 3.2. See Port I nput/Output section for complete description. P3.3 51 51 D I/O Port 3.3. See Port I nput/Output section for complete description. P3.4 50 50 D I/O Port 3.4. See Port I nput/Output section for complete description. P3.5 49 49 D I/O Port 3.5. See Port I nput/Output section for complete description. P3.6 48 48 D I/O Port 3.6. See Port I nput/Output section for complete description. P3.7 47 47 D I/O Port 3.7. See Port I nput/Output section for complete description. P4.5/ALE 93 93 D I/O Port 4.5. See Port Input/Output section for complete description. ALE Strobe for External Memory Address Bus (Mul- tiplexed mode). P4.6/RD 92 92 D I/O Port 4.6. See Port Inpu t/Output section for complete description. /RD Strobe for External Memory Address Bus. P4.7/WR 91 91 D I/O Port 4.7. See Port Inpu t/Output section for complete description. /WR Strobe for External Memory Address Bus. P5.0/A8 88 88 D I/O Port 5.0. See Port Input/Output section for complete description. Bit 8 External Memory Address Bus (Non-multi- plexed mode). P5.1/A9 87 87 D I/O Port 5.1. See Port Input/Output section for complete description. Table 4.1. Pin Definitions (Continued) Name Pin Numbers Type DescriptionF060 F061 F064 F065 F062 F063 F066 F067

Rev. 1.2 43 P5.2/A10 86 86 D I/O Port 5.2. See Port Input/Output section for complete description. P5.3/A11 85 85 D I/O Port 5.3. See Port Input/Output section for complete description. P5.4/A12 84 84 D I/O Port 5.4. See Port Input/Output section for complete description. P5.5/A13 83 83 D I/O Port 5.5. See Port Input/Output section for complete description. P5.6/A14 82 82 D I/O Port 5.6. See Port Input/Output section for complete description. P5.7/A15 81 81 D I/O Port 5.7. See Port Input/Output section for complete description. P6.0/A8m/ 80 80 D I/O Port 6.0. See Port Inpu t/Output section for complete description. Bit 8 External Memory Address Bus (Multiplexed mode). Bit 0 External Memory Address Bus (Non-multi- plexed mode). P6.1/A9m/ 79 79 D I/O Port 6.1. See Port Inpu t/Output section for complete description. P6.2/A10m/ 78 78 D I/O Port 6.2. See Port Inpu t/Output section for complete description. P6.3/A11m/ 77 77 D I/O Port 6.3. See Port Inpu t/Output section for complete description. P6.4/A12m/ 76 76 D I/O Port 6.4. See Port Inpu t/Output section for complete description. P6.5/A13m/ 75 75 D I/O Port 6.5. See Port Inpu t/Output section for complete description. P6.6/A14m/ 74 74 D I/O Port 6.6. See Port Inpu t/Output section for complete description. P6.7/A15m/ 73 73 D I/O Port 6.7. See Port Inpu t/Output section for complete description. P7.0/AD0m/ 72 72 D I/O Port 7.0. See Port Inpu t/Output section for complete description. Bit 0 External Memory Address/Data Bus (Multi- plexed mode). Bit 0 External Memory Data Bus (Non-multiplexed mode). P7.1/AD1m/ 71 71 D I/O Port 7.1. See Port Inpu t/Output section for complete description. Table 4.1. Pin Definitions (Continued) Name Pin Numbers Type DescriptionF060 F061 F064 F065 F062 F063 F066 F067

44 Rev. 1.2 P7.2/AD2m/ 70 70 D I/O Port 7.2. See Port Inpu t/Output section for complete description. P7.3/AD3m/ 69 69 D I/O Port 7.3. See Port Inpu t/Output section for complete description. P7.4/AD4m/ 68 68 D I/O Port 7.4. See Port Inpu t/Output section for complete description. P7.5/AD5m/ 67 67 D I/O Port 7.5. See Port Inpu t/Output section for complete description. P7.6/AD6m/ 66 66 D I/O Port 7.6. See Port Inpu t/Output section for complete description. P7.7/AD7m/ 65 65 D I/O Port 7.7. See Port Inpu t/Output section for complete description. NC 1, 2, 3, 25, 94, 17, 59, 60, 62, No Connection. Table 4.1. Pin Definitions (Continued) Name Pin Numbers Type DescriptionF060 F061 F064 F065 F062 F063 F066 F067

Rev. 1.2 45 Figure 4.1. C8051F060 / C8051F062 Pinout Diagram (TQFP-100) C8051F060/F062 100 P7.6/AD6m/D6 P7.7/AD7m/D7 VDD DGND P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P3.3 P6.5/A13m/A5 P6.6/A14m/A6 P6.7/A15m/A7 P7.0/AD0m/D0 P7.1/AD1m/D1 P7.2/AD2m/D2 P7.3/AD3m/D3 P7.4/AD4m/D4 P7.5/AD5m/D5 /RST TDO TDI TCK TMS CANRX CANTX P4.5/ALE P4.6/RD P4.7/WR VDD DGND P5.0/A8 P5.1/A9 P5.2/A10 P5.3/A11 P5.4/A12 P5.5/A13 P5.6/A14 P5.7/A15 P6.0/A8m/A0 P6.1/A9m/A1 P6.2/A10m/A2 P6.3/A11m/A3 P6.4/A12m/A4 AGND AV+ CNVSTR1 AVDD AGND CNVSTR0 AV+ AGND AIN0 AIN0G VRGND0 VREF0 VBGAP0 AGND AV+ DAC0 DAC1 VREF2 VREFD VREF VBGAP1 VREF1 VRGND1 AIN1G AIN1 XTAL1 XTAL2 MONEN P1.7/AIN2.7 P1.6/AIN2.6 P1.5/AIN2.5 P1.4/AIN2.4 VDD DGND P1.3/AIN2.3 P1.2/AIN2.2 P1.1/AIN2.1 P1.0/AIN2.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P3.7 P3.6 P3.5 P3.4 P3.2 P3.1 P3.0

46 Rev. 1.2 Figure 4.2. C8051F064 / C8051F066 Pinout Diagram (TQFP-100) C8051F064/F066 100 P7.6/AD6m/D6 P7.7/AD7m/D7 VDD DGND P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P3.3 P6.5/A13m/A5 P6.6/A14m/A6 P6.7/A15m/A7 P7.0/AD0m/D0 P7.1/AD1m/D1 P7.2/AD2m/D2 P7.3/AD3m/D3 P7.4/AD4m/D4 P7.5/AD5m/D5 /RST TDO TDI TCK TMS NC NC P4.5/ALE P4.6/RD P4.7/WR VDD DGND P5.0/A8 P5.1/A9 P5.2/A10 P5.3/A11 P5.4/A12 P5.5/A13 P5.6/A14 P5.7/A15 P6.0/A8m/A0 P6.1/A9m/A1 P6.2/A10m/A2 P6.3/A11m/A3 P6.4/A12m/A4 AGND AV+ CNVSTR1 AVDD AGND CNVSTR0 AV+ AGND AIN0 AIN0G VRGND0 VREF0 VBGAP0 AGND AV+ NC NC NC NC VREF VBGAP1 VREF1 VRGND1 AIN1G AIN1 XTAL1 XTAL2 MONEN P1.7 P1.6 P1.5 P1.4 VDD DGND P1.3 P1.2 P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P3.7 P3.6 P3.5 P3.4 P3.2 P3.1 P3.0

Rev. 1.2 47 Figure 4.3. TQFP-100 Package Drawing A b D e E L 0.05 0.95 0.17 0.45 1.00 0.22 16.00 14.00 0.50 16.00 14.00 0.60 1.20 0.15 1.05 0.27 0.75 MIN (mm) NOM (mm) MAX (mm) 100 e A1b A PIN 1 DESIGNATOR E1 E D L

48 Rev. 1.2 Figure 4.4. C8051F061 / C8051F063 Pinout Diagram (TQFP-64) C8051F061/063 DAC1 MONEN VREF2 VREF CANRX CANTX /RST TDO TDI VDD DGND TCK TMS P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 VDD DGND P2.3 P2.4 P2.5 P2.6 P2.7 P1.0/AIN2.0 VBGAP1 VREF1 VRGND1 AIN1G AIN1 AGND AV+ CNVSTR1 CNVSTR0 AV+ AGND AIN0 AIN0G VRGND0 VREF0 VBGAP0 DAC0 AV+ AGND XTAL1 XTAL2 AGND AVDD P1.7/AIN2.7 P1.6/AIN2.6 VDD DGND P1.5/AIN2.5 P1.4/AIN2.4 P1.3/AIN2.3 P1.2/AIN2.2 P1.1/AIN2.1

Rev. 1.2 49 Figure 4.5. C8051F065 / C8051F067 Pinout Diagram (TQFP-64) C8051F065/067 NC MONEN NC VREF NC NC /RST TDO TDI VDD DGND TCK TMS P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 VDD DGND P2.3 P2.4 P2.5 P2.6 P2.7 P1.0 VBGAP1 VREF1 VRGND1 AIN1G AIN1 AGND AV+ CNVSTR1 CNVSTR0 AV+ AGND AIN0 AIN0G VRGND0 VREF0 VBGAP0 NC AV+ AGND XTAL1 XTAL2 AGND AVDD P1.7 P1.6 VDD DGND P1.5 P1.4 P1.3 P1.2 P1.1

50 Rev. 1.2 Figure 4.6. TQFP-64 Package Drawing A b D e E L 0.05 0.95 0.17 0.45 0.22 12.00 10.00 0.50 12.00 10.00 0.60 1.20 0.15 1.05 0.27 0.75 MIN (mm) NOM (mm) MAX (mm) E e A1b D PIN 1 DESIGNATOR A L

Rev. 1.2 51 5. 16-Bit ADCs (ADC0 and ADC1) The ADC subsystem for the C8051F060 /1/2/3/4/5/6/7 consists of two 1 Msps, 16-bit successive-approxi- mation-register ADCs with integrated track-and-hold, a Programmable Window Detector, and a DMA inter- face (see block diagrams in Figure 5.1 and Figure 5.2). The ADCs can be configured as two separate, single-ended ADCs, or as a differential pair. T he Data Conversion Modes, Window Detector, and DMA interface are all configurable under software control via the Special Function Registers shown in Figure 5.1 and Figure 5.2. The voltage references used by ADC0 and ADC1 are selected as described in Section 5.2. The ADCs and their respective track-and-hold circuitr y can be independently enabled or disabled with the Special Function Registers. Either ADC can be enabled by setting the ADnEN bit in the ADC’s Control reg- ister (ADCnCN) to logic 1. The ADCs are in low power shutdown when these bits are logic 0. Figure 5.1. 16-Bit ADC0 and ADC1 Control Path Diagram AIN0G REF AV+ AD0EN SYSCLK AIN0 Start Conversion Timer 3 Overflow Timer 2 Overflow AD0BUSY (W) CNVSTR0 16-Bit SAR ADC0 ADC0CF AD0OCAL AD0LCAL AD0GCAL AD0SCAL AD0SC0 AD0SC1 AD0SC2 AD0SC3 ADC0CN AD0WINT AD0CM0 AD0CM1 AD0BUSY AD0INT AD0TM AD0EN REF AV+ AD1EN SYSCLK AIN1 Start Conversion Timer 3 Overflow Timer 2 Overflow AD1BUSY (W) CNVSTR1 16-Bit SAR ADC1 ADC1CF AD1OCAL AD1LCAL AD1GCAL AD1SCAL AD1SC0 AD1SC1 AD1SC2 AD1SC3 ADC1CN AD1CM0 AD1CM1 AD1CM2 AD1BUSY AD1INT AD1TM AD1EN AD0BUSY (W) 000 010 100 110 xx1 ADC0 Data Bus ADC1 Data Bus AIN1G (DC, -0.2 to 0.6 V) (DC, -0.2 to 0.6 V)

52 Rev. 1.2 Figure 5.2. 16-bit ADC0 and ADC1 Data Path Diagram 5.1. Single-Ended or Di fferential Operation ADC0 and ADC1 can be programmed to operate i ndependently as single-ended ADCs, or together to accept a differential input. In single-ended mode, the ADCs can be configured to sample simultaneously, or to use different conversion speeds. In differential mo de, ADC1 is a slave to ADC0, and its configuration is based on ADC0 settings, except during offset or ga in calibrations. The DIFFSEL bit in the Channel Select Register AMX0SL (Figure 5.6) selects between single-ended and differential mode. 5.1.1. Pseudo-Differential Inputs The inputs to the ADCs are pseudo-differential. The actual voltage measured by each ADC is equal to the voltage between the AINn pin and the AINnG pin. AINn G must be a DC signal between -0.2 and 0.6 V. In most systems, AINnG will be connected to AGND. If not tied to AGND, the AINnG signal can be used to negate a limited amount of fixed offset, but it is recommended that the internal offset calibration features of the device be used for this purpose. When operating in differential mode, AIN0G and AIN1G should be tied together. AINn must remain above AINnG in both modes for accurate conversion results. 16AIN0 16-Bit SAR ADC0 AMX0SLDIFFSEL 16AIN1 16-Bit SAR ADC1 ADC0H ADC0LADC1H ADC1L Single-Ended Differential ADC0LTLADC0LTHADC0GTLADC0GTH AD0WINTWindow Compare DMA Interface Σ AIN0G AIN1G

Rev. 1.2 53 5.2. Voltage Reference The voltage reference circuitries for ADC0 and ADC1 allow for many different voltage reference configura- tions. Each ADC has the capability to use its own dedicated, on-chip voltage reference, or an off-chip refer- ence circuit. A block diagram of the reference circuitry for one ADC is shown in Figure 5.3. The internal voltage reference circuit for each ADC consists of an independent, temperature stable 1.2 V bandgap voltage reference generator, with an output buffer amplifier which multiplies the bandgap refer- ence by 2. The maximum load seen by the VREFn (V REF0 or VREF1) pin must be less than 100 µA to AGND. Bypass capacitors of 0.1 µF and 47 µF are recommended from the VREFn pin to VRGNDn. The voltage reference circuitry for each ADC is controlled in the Reference Cont rol Registers. REF0CN (defined in Figure 5.11) is the Reference Control Register for ADC0, and REF1CN (defined in Figure 5.12) is the Reference Control Register for ADC1. The REFnCN registers are used to enable/disable the internal reference and bias generator circuitry for each ADC independently. The BIASEn bits enable the on-board bias generators for each ADC, while the REFBEn bits enable the 2x buffer amplifiers which drive the VREFn pins. When disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA (typical) and the output of the buffer amplifier enters a high impedance state (approximately 25 k Ohms). If the internal voltage re ference for an ADC is used, the BI ASEn and REFBEn bits for that ADC must both be set to logic 1. If an external reference is used, the REFBEn bit should be set to logic 0. Note that the BIASEn bit for an ADC must be set to logic 1 to enable that ADC, regardless of the voltage refer- ence that is used. If an ADC is not being used, the BIASEn bit can be set to logic 0 to conserve power. The electrical specifications for the Voltage References are given in Table 5.3. Figure 5.3. Voltage Reference Block Diagram Recommended Bypass Capacitors ADCn Ref REFnCN REFBEn BIASEn 1.25V Band-Gap EN VBGAPn 0.1µF Bias VREFn 47µF0 . 1 µF VRGNDn External Voltage Reference

54 Rev. 1.2 5.3. ADC Modes of Operation ADC0 and ADC1 have a maximum conv ersion speed of 1 Msps. The conv ersion clocks for the ADCs are derived from the system clock. The ADCnSC bits in the ADCnCF register determine how many system clocks (from 1 to 16) are used for each conversion clock. 5.3.1. Starting a Conversion For ADC0, conversions can be initiated in one of fo ur ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM1, AD0CM0) in ADC0CN. For ADC0, conversions may be ini- tiated by: 1. Writing a ‘1’ to the AD0BUSY bit of ADC0CN; 2. A Timer 3 overflow (i.e. timed continuous conversions); 3. A rising edge detected on the external ADC convert start signal, CNVSTR0; 4. A Timer 2 overflow (i.e. timed continuous conversions). ADC1 conversions can be initiated in five different ways, according to the ADC1 Start of Conversion Mode bits (AD1CM2-AD1CM0) in ADC1CN. For ADC1, conversions may be initiated by: 1. Writing a ‘1’ to the AD1BUSY bit of ADC1CN; 2. A Timer 3 overflow (i.e. timed continuous conversions); 3. A rising edge detected on the external ADC convert start signal, CNVSTR1; 4. A Timer 2 overflow (i.e. timed continuous conversions); 5. Writing a ‘1’ to the AD0BUSY bit of ADC0CN. The ADnBUSY bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete. The falling edge of ADnBUSY triggers an interrupt (when en abled) and sets the AD nINT interrupt flag (ADCnCN.5). In single-ended mode, the converted data for ADCn is available in the ADCn data word MSB and LSB registers, ADCnH, ADCnL. In differential mode, the converted data (combined from ADC0 and ADC1) is available in the ADC0 data word MSB and LSB registers, ADC0H, ADC0L. When initiating conversions by wr iting a ‘1’ to ADnBUSY, the ADnINT bit should be polled to determine when a conversion has completed (ADCn interrupts may also be us ed). The recommended polling proce- dure is shown below. Step 1. Write a ‘0’ to ADnINT; Step 2. Write a ‘1’ to ADnBUSY; Step 3. Poll ADnINT for ‘1’; Step 4. Process ADCn data. When an external start-of-conversion source is required in differential mode the two pins (CNVSTR0 and CNVSTR1) should be tied together. 5.3.2. Tracking Modes The ADnTM bit in register ADCnCN controls the AD Cn track-and-hold mode. When the ADC is enabled, the ADC input is continuously tracked when a conversi on is not in progress. When the ADnTM bit is logic 1, each conversion is preceded by a tracking period (after the start-of-conversion signal). When the CNVSTRn signal is used to initiate conversions, t he ADC will track until a risi ng edge occurs on the CNVSTRn pin (see Figure 5.4 and Table 5.1 for conver sion timing parameters). Setting ADnTM to 1 can be useful to ensure that settling time requirements are met when an external multiplexer is used on the analog input (see Section “5.3.3. Settling Time Requirements” on page 56).

Rev. 1.2 55 Figure 5.4. ADC Track and Conversion Example Timing Table 5.1. Conversion Timing (tConv) ADnSC3-0 ADCnTM = 0 ADCnTM = 1 ADnSC3-0 ADCnTM = 0 ADCnTM = 1 0000 21*t SYSCLK 38*tSYSCLK 1000 171*t SYSCLK 315*tSYSCLK 0001 40*t SYSCLK 72*tSYSCLK 1001 189*t SYSCLK 349*tSYSCLK 0010 58*t SYSCLK 106*tSYSCLK 1010 208*t SYSCLK 384*tSYSCLK 0011 78*t SYSCLK 142*tSYSCLK 1011 226*t SYSCLK 418*tSYSCLK 0100 97*t SYSCLK 177*tSYSCLK 1100 245*t SYSCLK 453*tSYSCLK 0101 115*t SYSCLK 211*tSYSCLK 1101 263*t SYSCLK 487*tSYSCLK 0110 134*t SYSCLK 246*tSYSCLK 1110 282*t SYSCLK 522*tSYSCLK 0111 152*t SYSCLK 280*tSYSCLK 1111 300*t SYSCLK 556*tSYSCLK CNVSTRn Timer 2, Timer 3 Overflow; Write '1' to ADnBUSY ADCnTM=1 ADCnTM=0 A. ADC Timing for External Trigger Source B. ADC Timing for Internal Trigger Sources Track Convert Track Track Track Convert TrackTrack Convert Track tConv tConv tConv

56 Rev. 1.2 5.3.3. Settling Time Requirements The ADC requires a minimum tracking time before an accurate conversion can be performed. This tracking time is determined by the ADC input resistance, the ADC sampling capacitance, any external source resis- tance, and the accuracy required for the conversion. Figure 5.5 shows the equivalent ADC input circuits for both Differential and Single-ended modes. Notice that the equivalent time constant for both input circuits is the same. The required settling time for a given settling accuracy ( SA) may be approximated by Equation 5.1. An absolute minimum tracking time of 280 ns is required prior to the start of a conversion. Equation 5.1. ADC0 Settling Time Requirements Where: SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required settling time in seconds R TOTAL is the sum of the ADC input resistance and any external source resistance. n is the ADC resolution in bits (16). Figure 5.5. ADC0 and ADC1 Equivalent Input Circuits t 2n  RTOTAL CSAMPLE×ln= RAIN = 30 Ω RCInput= RAIN * CSAMPLE RAIN = 30 Ω CSAMPLE = 80pF CSAMPLE = 80pF Differential Mode AIN0 AIN1 RAIN = 30 Ω CSAMPLE = 80pF RCInput= RAIN * CSAMPLE Single-Ended Mode AIN0 or AIN1

Rev. 1.2 57 Figure 5.6. AMX0SL: AMUX Configuration Register Bit 7: RESERVED. Write to 0b. Bit 6: DIFFSEL: Fully Differential Conversion Mode Select Bit. 0: Operate In Single-Ended Mode. 1: Operate In Differential Mode. Bit 5-0: RESERVED. Write to 000000b. NOTE: For single-ended mode, the ADC0 Data Word is stored in ADC0H and ADC0L, while the ADC1 Data Word is stored in ADC1H and ADC1L. In differential mode, the combined ADC Data Word is stored in ADC0H and ADC0L, and is a 2’s complement number. ADC1’s Data Word (single-ended) is also stored in ADC1H and ADC1L. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - DIFFSEL - - - - - - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xBB

58 Rev. 1.2 Figure 5.7. ADC0CF: ADC0 Configuration Register Bits 7-4: AD0SC3-0: ADC0 SAR Co nversion Clock Period Bits. SAR Conversion clock is divided down from the system clock according to the AD0SC bits (AD0SC3-0). The number of system clocks used for each SAR conversion clock is equal to AD0SC + 1. (Note: the ADC0 SAR Conversion Clock should be less than or equal to 25 MHz). See Table 5.1 for conversion timing details. Bit 3: AD0SCAL: System Calibration Enable. 0: Internal ground and reference voltage are used during offset and gain calibration. 1: External voltages can be used during offset and gain calibration. Bit 2: AD0GCAL: Gain Calibration. Read: 0: Gain Calibration is completed or not yet started. 1: Gain Calibration is in progress. Write: 0: No Effect. 1: Initiates a gain calibration if ADC0 is idle. Bit 1: AD0LCAL: Linearity Calibration Read 0: Linearity Calibration is completed or not yet started 1: Linearity Calibration is in progress Write 0: No Effect 1: Initiates a linearity calibration if ADC0 is idle Bit 0: AD0OCAL: Offset Calibration. Read: 0: Offset Calibration is completed or not yet started. 1: Offset Calibration is in progress. Write: 0: No Effect. 1: Initiates an offset calibration if ADC0 is idle. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0SCAL AD0GCAL AD0LCAL AD0OCAL 11110000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xBC

Rev. 1.2 59 Figure 5.8. ADC1CF: ADC1 Configuration Register Bits 7-4: AD1SC3-0: ADC1 SAR Co nversion Clock Period Bits. SAR Conversion clock is divided down from the system clock according to the AD1SC bits (AD1SC3-0). The number of system clocks used for each SAR conversion clock is equal to AD1SC + 1. (Note: the ADC1 SAR Conversion Clock should be less than or equal to 25 MHz). See Table 5.1 for conversion timing details. Bit 3: AD1SCAL: System Calibration Enable. 0: Internal ground and reference voltage are used for offset and gain calibration. 1: External voltages can be used for offset and gain calibration. Bit 2: AD1GCAL: Gain Calibration. Read: 0: Gain Calibration is completed or not yet started. 1: Gain Calibration is in progress. Write: 0: No Effect. 1: Initiates a gain calibration if ADC1 is idle. Bit 1: AD1LCAL: Linearity Calibration Read 0: Linearity Calibration is completed or not yet started 1: Linearity Calibration is in progress Write 0: No Effect 1: Initiates a linearity calibration if ADC1 is idle Bit 0: AD1OCAL: Offset Calibration. Read: 0: Offset Calibration is completed or not yet started. 1: Offset Calibration is in progress. Write: 0: No Effect. 1: Initiates an offset calibration if ADC1 is idle. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value AD1SC3 AD1SC2 AD1SC1 AD1SC0 AD1SCAL AD1GCAL AD1LCAL AD1OCAL 11110000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xBC

60 Rev. 1.2 Figure 5.9. ADC0CN: ADC0 Control Register Bit 7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions or calibrations. Bit 6: AD0TM: ADC Track Mode Bit. 0: When the ADC is enabled, tracking is continuous unless a conversion is in process. 1: Tracking Defined by AD0CM1-0 bits. Bit 5: AD0INT: ADC0 Conversion Complete Interrupt Flag. This flag must be cleared by software. 0: ADC0 has not completed a data conversion since the last time this flag was cleared. 1: ADC0 has completed a data conversion. Bit 4: AD0BUSY: ADC0 Busy Bit. Read: 0: ADC0 Conversion is complete or a conversion is not currently in progress. AD0INT is set to logic 1 on the falling edge of AD0BUSY. 1: ADC0 Conversion is in progress. Write: 0: No Effect. 1: Initiates ADC0 Conversion if AD0CM1-0 = 00b. Bits 3-2: AD0CM1-0: ADC0 Start of Conversion Mode Select. If AD0TM = 0: 00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY. 01: ADC0 conversion initiated on overflow of Timer 3. 10: ADC0 conversion initiated on rising edge of external CNVSTR0. 11: ADC0 conversion initiated on overflow of Timer 2. If AD0TM = 1: 00: Tracking starts with the write of ‘1’ to AD0BUSY and is followed by the conversion. 01: Tracking started by the overflow of Timer 3 and is followed by the conversion. 10: ADC0 conversion starts on rising CNVSTR0 edge. 11: Tracking started by the overflow of Timer 2 and is followed by the conversion. See Figure 5.4 and Table 5.1 for conversion timing parameters. Bit 1: AD0WINT: ADC0 Windo w Compare Interrupt Flag. This bit must be cleared by software. 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. Bit 0: RESERVED: Write to 0b. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 AD0WINT - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: SFR Page: 0xE8

Rev. 1.2 61 Figure 5.10. ADC1CN: ADC1 Control Register Bit 7: AD1EN: ADC1 Enable Bit. 0: ADC1 Disabled. ADC1 is in low-power shutdown. 1: ADC1 Enabled. ADC1 is active and ready for data conversions or calibrations. Bit 6: AD1TM: ADC Track Mode Bit. 0: When the ADC is enabled, tracking is continuous unless a conversion is in process. 1: Tracking Defined by AD1CM2-0 bits. Bit 5: AD1INT: ADC1 Conversion Complete Interrupt Flag. This flag must be cleared by software. 0: ADC1 has not completed a data conversion since the last time this flag was cleared. 1: ADC1 has completed a data conversion. Bit 4: AD1BUSY: ADC1 Busy Bit. Read: 0: ADC1 Conversion is complete or a conversion is not currently in progress. AD1INT is set to logic 1 on the falling edge of AD1BUSY. 1: ADC1 Conversion is in progress. Write: 0: No Effect. 1: Initiates ADC1 Conversion if AD1CM2-0 = 000b. Bits 3-1: AD1CM2-0: ADC1 Start of Conversion Mode Select. If AD1TM = 0: 000: ADC1 conversion initiated on every write of ‘1’ to AD1BUSY. 010: ADC1 conversion initiated on overflow of Timer 3. 100: ADC1 conversion initiated on rising edge of external CNVSTR1. 110: ADC1 conversion initiated on overflow of Timer 2. xx1: ADC1 conversion initiated on every write of ‘1’ to AD0BUSY in ADC0CN If AD1TM = 1: 000: Tracking starts with the write of ‘1’ to AD1BUSY and is followed by the conversion. 010: Tracking started by the overflow of Timer 3 and is followed by the conversion. 100: ADC1 conversion starts on rising CNVSTR1 edge. 110: Tracking started by the overflow of Timer 2 and is followed by the conversion. xx1: Tracking starts with the write of ‘1’ to AD0BUSY and is followed by the conversion. See Figure 5.4 and Table 5.1 for conversion timing parameters. Bit 0: RESERVED: Write to 0b. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value AD1EN AD1TM AD1INT AD1BUSY AD1CM2 AD1CM1 AD1CM0 - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: SFR Page: 0xE8

64 Rev. 1.2 16-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows: Example: ADC0 Data Word Conversion Map, AIN0 Input in Single-Ended Mode (AMX0SL = 0x00) Example: ADC0 Data Word Conversion Map, AIN0-AIN1 Differential Input Pair (AMX0SL = 0x40) ; ‘n’ = 16 for Single-Ended; ‘n’=15 for Differential. AIN0-AIN0G (Volts) ADC0H:ADC0L VREF * (65535/65536) 0xFFFF VREF / 2 0x8000 VREF * (32767/65536) 0x7FFF 0 0x0000 AIN0-AIN1 (Volts) ADC0H:ADC0L VREF * (32767/32768) 0x7FFF VREF / 2 0x4000 VREF * (1/32768) 0x0001 0 0x0000 -VREF * (1/32768) 0xFFFF -VREF / 2 0xC000 -VREF 0x8000 Code Vin Gain Figure 5.15. ADC0 Data Word Example

Rev. 1.2 71 Figure 5.28. 16-Bit ADC0 Window Interrupt Example: Single-Ended Data Given: AMX0SL = 0x00, ADC0LTH:ADC0LTL = 0x2000, ADC0GTH:ADC0GTL = 0x1000. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x2000 and > 0x1000. Given: AMX0SL = 0x00, ADC0LTH:ADC0LTL = 0x1000, ADC0GTH:ADC0GTL = 0x2000. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is > 0x2000 or < 0x1000. 0xFFFF 0x2001 0x2000 0x1FFF 0x1001 0x1000 0x0FFF 0x0000 AD0WINT=1 AD0WINT not affected AD0WINT not affected ADC0 Data Word 0xFFFF 0x2001 0x2000 0x1FFF 0x1001 0x1000 0x0FFF 0x0000 AD0WINT=1 AD0WINT not affected AD0WINT=1 ADC0LTH:ADC0LTL ADC0GTH:ADC0GTL ADC0 Data Word ADC0GTH:ADC0GTL ADC0LTH:ADC0LTL Input Voltage (AIN0 - AIN0G) REF x (65535/65536) REF x (4096/65536) REF x (8192/65536) Input Voltage (AIN0 - AIN0G) REF x (65535/65536) REF x (4096/65536) REF x (8192/65536)

72 Rev. 1.2 0x7FFF 0x1001 0x1000 0x0FFF 0x0000 0xFFFF 0xFFFE 0x8000 AD0WINT=1 AD0WINT not affected AD0WINT not affected 0x7FFF 0x1001 0x1000 0x0FFF 0x0000 0xFFFF 0xFFFE 0x8000 AD0WINT=1 AD0WINT not affected Input Voltage (AIN0 - AIN1) AD0WINT=1 ADC0LTH:ADC0LTL ADC0GTH:ADC0GTL ADC0 Data Word ADC0 Data Word ADC0LTH:ADC0LTL ADC0GTH:ADC0GTL -REF Input Voltage (AIN0 - AIN1) REF x (32767/32768) REF x (4096/32768) REF x (-1/32768) -REF REF x (32767/32768) REF x (4096/32768) REF x (-1/32768) Figure 5.29. 16-Bit ADC0 Window Interrupt Example: Differential Data Given: AMX0SL = 0x40, ADC0LTH:ADC0LTL = 0x1000, ADC0GTH:ADC0GTL = 0xFFFF. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x1000 and > 0xFFFF. (In two’s-complement math, 0xFFFF = -1.) Given: AMX0SL = 0x40, ADC0LTH:ADC0LTL = 0xFFFF, ADC0GTH:ADC0GTL = 0x1000. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0xFFFF or > 0x1000. (In two’s-complement math, 0xFFFF = -1.)

Rev. 1.2 73 Table 5.2. 16-Bit ADC0 and ADC1 Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, AVDD = 3.0 V, VREF = 2.50 V (REFBE=0), -40 to +85 °C unless otherwise specified Parameter Conditions Min Typ Max Units DC Accuracy Resolution 16 bits Integral Nonlinearity Single-Ended Differential ±0.75 ±0.5 LSB Integral Nonlinearity (C8051F062/3) Single-Ended Differential ±1.5 LSB Differential Nonlinearity Gu aranteed Monotonic ±0.5 LSB Offset Error 0.1 mV Full Scale Error 0.008 %F.S. Gain Temperature Coefficient 0.5 ppm/°C Dynamic Performance (Sampling Rate = 1 Msps, AVDD, AV+ = 3.3V) Signal-to-Noise Plus Distortion Fin = 10 kHz, Single-Ended Fin = 100 kHz, Single-Ended Fin = 10 kHz, Differential Fin = 100 kHz, Differential dB dB dB dB Total Harmonic Distortion Fin = 10 kHz, Single-Ended Fin = 100 kHz, Single-Ended Fin = 10 kHz, Differential Fin = 100 kHz, Differential 103 dB dB dB dB Spurious-Free Dynamic Range Fin = 10 kHz, Single-Ended Fin = 100 kHz, Single-Ended Fin = 10 kHz, Differential Fin = 100 kHz, Differential 104 dB dB dB dB CMRR Fin = 10 kHz 86 dB Channel Isolation 100 dB Timing SAR Clock Frequency 25 MHz Conversion Time in SAR Clocks 18 clocks Track/Hold Acquisition Time 280 ns Throughput Rate 1 Msps Aperture Delay External CNVST Signal 1.5 ns RMS Aperture Jitter External CNVST Signal 5 ps Analog Inputs Input Voltage Range Single-Ended (AINn - AINnG) Differential (AIN0 - AIN1) -VREF VREF VREF V V Input Capacitance 80 pF

74 Rev. 1.2 Operating Input Range AIN0 or AIN1 AIN0G or AIN1G (DC Only) -0.2 -0.2 AV+ 0.6 V V Power Specifications Power Supply Current (each ADC) Operating Mode, 1 Msps AV+ AVDD Shutdown Mode 4.0 2.0 mA mA µA Power Supply Rejection VDD ± 5% ±0.5 LSB Table 5.3. Voltage Reference 0 and 1 Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, AVDD = 3.0 V, -40 to +85 °C unless otherwise specified Parameter Conditions Min Typ Max Units Internal Reference Output Voltage 25 °C ambient 2.36 2.43 2.48 V VREF Temperature Coefficient 15 ppm/°C Power Supply Current (each Voltage Reference) AV+ 1.5 mA External Reference Input Voltage Range 2.0 AV+ V Input Current ADC throughput = 1 Msps 450 µA Table 5.2. 16-Bit ADC0 and ADC1 Electrical Characteristics (Continued) VDD = 3.0 V, AV+ = 3.0 V, AVDD = 3.0 V, VREF = 2.50 V (REFBE=0), -40 to +85 °C unless otherwise specified Parameter Conditions Min Typ Max Units

Rev. 1.2 75 6. Direct Memory Access Interface (DMA0) The DMA interface works in conjunction with ADC0 and ADC1 to write AD C outputs directly to a specified region of XRAM. The DMA interface is configured by software using the Special Function Registers shown in Figure 6.1. Up to 64 instructions can be programmed into the Instruction Buffer to designate a sequence of DMA operations. The Instruction Buffer is accessed by the DMA Control Logic, which gathers the appro- priate data from the ADCs and controls writes to XRAM. The DMA instructions tell the DMA Control Logic which ADC(s) to expect results from, bu t do not initiate the actual conversions. It is important to configure the ADCs for the desired start-of-conversion source, voltage reference, and SAR clock frequency prior to starting the DMA interface. For information on setting up the ADCs, refer to Section “5. 16-Bit ADCs (ADC0 and ADC1)” on page 51. 6.1. Writing to the Instruction Buffer The Instruction Buffer has 64 8-bit locations that can be programmed with a sequence of DMA instructions. Filling the Instruction Buffer is done with the Sp ecial Function Registers DMA0 IPT (DMA Instruction Write Address Register, Figure 6.6) and DMA0IDT (DMA Inst ruction Write Data Register, Figure 6.7). Instruc- tions are written to the Instruction Buffer at address DMA0IPT when the instruction word is written to DMA0IDT. Reading the register DMA0IDT will return the instruction word at location DMA0IPT. After a write or read operation on DMA0IDT, the DMA0IPT register is automatically incremented to the next Instruction Buffer location. AIN0 ADC0 AIN1 ADC1 DMA Control Logic DMA0IDT Instruction Data DMA0IPT Address Write Logic DMA0BND Start Address Instruction Buffer (64 Bytes) ADC0EN ADC1EN DIFFSEL CCNV DMA0ISW Current Address XRAM (on-chip or off-chip) DMA0DSH Current XRAM Address DMA0DSL DMA0DAH Beginning XRAM Address DMA0DAL DMA0CSH Current Repeat Counter Value DMA0CSLDMA0CTH Repeat Counter Limit DMA0CTL Address Bus Data Bus DMA0CF DMA0EO DMA0EOE DMA0CI DMA0CIE DMA0XBY DMA0HLT DMA0CN DMA0DO0 DMA0DO1 DMA0DOE DMA0DE0 DMA0DE1 DMA0MD DMA0INT DMA0EN AIN0G AIN1G Figure 6.1. DMA0 Block Diagram

76 Rev. 1.2 6.2. DMA0 Instruction Format DMA instructions can request single-ended data from both ADC0 and ADC1, as well as the differential combination of the two ADC inputs. The instruction fo rmat is identical to the DMA0IDT register, shown in Figure 6.7. Depending on which bits are set to ‘1’ in the instruction word, either 2 or 4 bytes of data will be written to XRAM for each DMA in struction cycle (excluding End-Of -Operation instructions). Table 6.1 details all of the valid DMA instruct ions. Instructions not listed in the table are not valid DMA instructions, and should not be used. Note that the ADCs can be independently controlled by the microcontroller when their outputs are not requested by the DMA. 6.3. XRAM Addressing and Setup The DMA Interface can be configured to access either on-chip or off-chip XRAM. Any writes to on-chip XRAM by the DMA Control Logic occur when the processor core is not accessing the on-chip XRAM. This ensures that the DMA will not interfere with processor instruction timing. Off-chip XRAM access (only available on the C8 051F060/2/4/6) is controlled by the DMA0HLT bit in DMA0CF (DMA Configuration Register, Figure 6.5). The DMA will have full access to off-chip XRAM when this bit is ‘0’, and the processor core will have full access to off-chip XRAM wh en this bit is ‘1’. The DMA0HLT bit should be controlled in software when both the processor core and the DMA Interface require access to off-chip XRAM data space. Before setting DMA0HLT to ‘1’, the software should check the DMA0XBY bit to ensure that the DMA is not currently accessing of f-chip XRAM. The processor core can- not access off-chip XRAM while DMA0HLT is ‘0’. The processor will continue as though it was able to per- form the desired memory access, but the data will not be written to or read from off-chip XRAM. When the processor core is finished acce ssing off-chip XRAM, DMA0HLT shoul d be set back to ‘0’in software to return control to the DMA Interfac e. The DMA Control Logic will wait un til DMA0HLT is ‘0’ before writing data to off-chip XRAM. If new data becomes available to the DMA Interface before the previous data has been written, an overflow condition will occur, and the new data word may be lost. The Data Address Pointer Registers (DMA0DSH and DMA0DSL) contain the 16-bit XRAM address loca- tion where the DMA interface will wr ite data. When the DMA is initially enabled, the DMA Data Address Table 6.1. DMA0 Instruction Set Instruction Word Description First Data Written to XRAM (2 bytes) Second Data Written to XRAM (2 bytes) 00000000b End-Of-Operation none none 10000000b End-Of-Operation with Continuous Conversion none none x0010000b Retrieve ADC0 Data ADC0H:ADC0L none x0100000b Retrieve ADC1 Data ADC1H:ADC1L none x0110000b Retrieve ADC0 and ADC1 Data ADC0H:ADC0L ADC1H:ADC1L x10x0000b Retrieve Differential Data ADC0H:ADC0L (differential result from both ADCs) none x11x0000b Retrieve Differential and ADC1 Data ADC0H:ADC0L (differential result from both ADCs) ADC1H:ADC1L

Rev. 1.2 79 6.6. Interrupt Sources The DMA contains multiple interrupt sources. Some of these can be individually enabled to generate inter- rupts as necessary. The DMA Control Register (DMA0CN, Figure 6.4) and DMA Configuration Register (DMA0CF, Figure 6.5) contain the enable bits and flags for the DMA interrupt sources. When an interrupt is enabled and the interrupt condition occurs, a DMA interrupt will be generated (EIE2.7 is set to ‘1’). The DMA flags that can generate a DMA0 interrupt are: 1. DMA Operations Complete (DMA0CN.6, DMA0INT) occurs when all DMA operations have been completed, and the DMA interface is idle. 2. ADC1 Data Overflow Error (DMA0CN.4, DMA0 DE1) occurs when the DMA interface cannot access XRAM for two conversion cycles of ADC1. This flag indicates that at least one conver- sion result from ADC1 has been discarded. 3. ADC0 Data Overflow Error (DMA0CN.3, DMA0 DE0) occurs when the DMA interface cannot access XRAM for two conversion cycles of ADC0. This flag indicates that at least one conver- sion result from ADC0 has been discarded. 4. ADC1 Data Overflow Warning (DMA0CN.1, DMA0DO1) occurs when data from ADC0 becomes available and the DMA has not yet written the previous results to XRAM. This inter- rupt source can be enabled and disabled wi th the Data Overflow Warning Enable bit (DMA0CN.2, DMA0DOE). 5. ADC0 Data Overflow Warning (DMA0CN.0, DMA0DO0) occurs when data from ADC1 becomes available and the DMA has not yet written the previous results to XRAM. This inter- rupt source can be enabled and disabled wi th the Data Overflow Warning Enable bit (DMA0CN.2, DMA0DOE). 6. Repeat Counter Overflow (DMA0CF.2, DMA0 CI) occurs when the Repeat Counter reaches the Repeat Counter Limit. This interrupt sour ce can be enabled and disabled with the Repeat Counter Overflow Interrupt Enable bit (DMA0CF.3, DMA0CIE). 7. End Of Operation (DMA0CF.0, DMA0EO) occurs when an End Of Operation instruction is reached in the Instruction Buffer. This interrupt source can be enabled and disabled with the End Of Operation Interrupt Enable bit (DMA0CF.1, DMA0EOE). 6.7. Data Buffer Overflow Warnings and Errors The data paths from the ADCs to XRAM are double-bu ffered when using the DMA interface. When a con- version is completed by the ADC, it first enters the A DCs data register. If the DMA’s data buffer is empty, the conversion results will immediately be written into the DMA’s internal data buffer for that ADC. Data in the DMA’s internal data buffer is written to XRAM at the first available opportunity (see Section “6.3. XRAM Addressing and Setup” on page 76). Conversion results from the ADC’s data registers are not copied into the DMA’s data buffer until data in the buffer has been written to XRAM. When a conversion is completed and the DMA’s data buffer is not empty, an overflow warning flag is generated. If a second conversion data word becomes available before the DMA’s data buffer is written to XRAM, the data in the ADC’s data regis- ters is over-written with the new data word, and a data overflow error flag is generated.

80 Rev. 1.2 Figure 6.4. DMA0CN: DMA0 Control Register Bit 7: DMA0EN: DMA0 Enable. Write: 0: Stop DMA0 Operations. 1: Begin DMA0 Operations. Read: 0: DMA0 is Idle. 1: DMA0 Operation is in Progress. Bit 6: DMA0INT: DMA0 Operations Complete Flag. 0: DMA0 has not completed all operations. 1: DMA0 operations are complete. This bit must be cleared by software. Bit 5: DMA0MD: DMA0 Mode Select. 0: DMA0 will operate in Mode 0. 1: DMA0 will operate in Mode 1. Bit 4: DMA0DE1: ADC1 Data Overflow Error Flag. 0: ADC1 Data Overflow has not occured. 1: ADC1 Data Overflow has occured, and data from ADC1 has been lost. This bit must be cleared by software. Bit 3: DMA0DE0: ADC0 Data Overflow Error Flag. 0: ADC0 Data Overflow has not occured. 1: ADC0 Data Overflow has occured, and data from ADC0 has been lost. This bit must be cleared by software. Bit 2: DMA0DOE: Data Overflow Warning Interrupt Enable. 0: Disable Data Overflow Warning interrupts. 1: Enable Data Overflow Warning interrups. Bit 1: DMA0DO1: ADC1 Data Overflow Warning Flag. 0: No ADC1 Data Buffer Warnings have been issued. 1: ADC1 Data Buffer is full, and the DMA has not written previous data to XRAM. This bit must be cleared by software. Bit 0: DMA0DO0: ADC0 Data Overflow Warning Flag. 0: No ADC0 Data Buffer Warnings have been issued. 1: ADC0 Data Buffer is full, and the DMA has not written previous data to XRAM. This bit must be cleared by software. SFR Page: SFR Address: 0xD8 (bit addressable) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value DMA0EN DMA0INT DMA0MD DMA0DE1 DMA0DE0 DMA0DOE DMA0DO1 DMA0DO0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Rev. 1.2 81 Figure 6.5. DMA0CF: DMA0 Configuration Register Bit 7: DMA0HLT: Halt DMA0 Off-Chip XRAM Access (C8051F060/2/4/6 Only). 0: DMA0 has complete access to off-chip XRAM. 1: Processor core has complete access to off-chip XRAM. DMA0 will wait until this bit is ‘0’ before writing to off-chip XRAM locations. Bit 6: DMA0XBY: Off-chip XRAM Bu sy Flag (C8051F060/2/4/6 Only). 0: DMA0 is not accessing off-chip XRAM. 1: DMA0 is accessing off-chip XRAM. Bits 5-4: RESERVED. Write to 00b. Bit 3: DMA0CIE: Repeat Counter Overflow Interrupt Enable. 0: Disable Repeat Counter Overflow Interrupt. 1: Enable Repeat Counter Overflow Interrupt. Bit 2: DMA0CI: Repeat Counter Overflow Flag. 0: Repeat Counter Overflow has not occured. 1: Repeat Counter Overflow has occured. This bit must be cleared by software. Bit 1: DMA0EOE: End-Of-O peration Interrupt Enable. 0: Disable End-Of-Operation Interrupt. 1: Enable End-Of-Operation Interrupt. Bit 0: DMA0EO: End- Of-Operation Flag. 0: End-Of-Operation Instruction has not been received. 1: End-Of-Operation Instruction has been received. This bit must be cleared by software. SFR Page: SFR Address: 0xF8 (bit addressable) R/W R R/W R/W R/W R/W R/W R/W Reset Value DMA0HLT DMA0XBY - - DMA0CIE DMA0CI DMA0EOE DMA0EO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

86 Rev. 1.2

88 Rev. 1.2 7.1. Analog Multiplexer The analog multiplexer (AMUX2) selects the inputs to the ADC, allowing any of the pins on Port 1 to be measured in single-ended mode, or as a differential pair. Additionally, the on-chip temperature sensor may be selected as a single-ended input. The ADC2 input channels are configured and selected in the AMX2CF and AMX2SL registers as described in Figu re 7.5 and Figure 7.6, respectively. In Single-ended Mode, the selected pin is measured with respect to AGND. In Differential Mode, the selected differential pair is measured with respect to one another. The polarity of the differential measurement depends on the setting of the AMX2AD3-0 bits in the AMX2SL register. For example, if pins AIN2.0 and AIN2.1 are config- ured for differential measurement (AIN01IC = 1), and AMX2AD3-0 = 0000b, the ADC will measure the volt- age (AIN2.0 - AIN2.1). If AMX2AD3- 0 is changed to 0001b, the ADC will measure the same voltage, with opposite polarity (AIN2.1 - AIN2.0). The conversion code format differs between Single -ended and Differential modes. The registers ADC2H and ADC2L contain the high and low bytes of the outpu t conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD2LJST bit (ADC2CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers. Inputs are measured from ‘0’ to VREF * 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC2H and ADC2L registers are set to ‘0’. When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers. Inputs are measured from -VREF to VREF * 511/512. Example codes are shown below for both right-justi- fied and left-justified data. For right-justified data, the unused MSBs of ADC2H are a sign-extension of the data word. For left-justified data, the unused LSBs in the ADC2L register are set to ‘0’. Important Note About ADC2 Input Configuration: Port 1 pins selected as ADC2 inputs should be con- figured as analog inputs. To configure a Port 1 pin for analog input, set to ‘1’ the corresponding bit in regis- ter P1MDIN. Port 1 pins used as ADC2 inputs will be skipped by the crossbar for peripheral assignments. See Section “18. Port Input/Output” on page 203 for more Port I/O configuration details. The Temperature Sensor transfer function is shown in Figure 7.2 on Page 89. The output voltage (V TEMP) is a single-ended input to ADC2 when the Temperatur e Sensor is selected by bi ts AMX2AD3-0 in register AMX2SL. Typical values for the Slope and Offset parameters can be found in Table 7.1. Input Voltage Right-Justified ADC2H:ADC2L (AD2LJST = 0) Left-Justified ADC2H:ADC2L (AD2LJST = 1) VREF * 1023/1024 0x03FF 0xFFC0 VREF * 512/1024 0x0200 0x8000 VREF * 256/1024 0x0100 0x4000 0 0x0000 0x0000 Input Voltage Right-Jus tified ADC2H:ADC2L (AD2LJST = 0) Left-Justified ADC2H:ADC2L (AD2LJST = 1) VREF * 511/512 0x01FF 0x7FC0 VREF * 256/512 0x0100 0x4000 0 0x0000 0x0000 -VREF * 256/512 0xFF00 0xC000 - VREF 0xFE00 0x8000

Rev. 1.2 89 7.2. Modes of Operation ADC2 has a maximum conversion speed of 200 ksps. The ADC2 conversion clock is a divided version of the system clock, determined by the AD2SC bits in the ADC2CF register (system clock divided by (AD2SC + 1) for 0 ≤ AD2SC ≤ 31). The ADC2 conversion clock should be no more than 3 MHz. 7.2.1. Starting a Conversion A conversion can be initiated in one of four ways, depending on the programmed states of the ADC2 Start of Conversion Mode bits (AD2CM1-0) in register ADC2CN. Conversions may be initiated by one of the fol- lowing: 1. Writing a ‘1’ to the AD2BUSY bit of register ADC2CN 2. A Timer 3 overflow (i.e. timed continuous conversions) 3. A rising edge on the CNVSTR2 input signal (Assigned by the crossbar) 4. A Timer 2 overflow When CNVSTR2 is used as a conversion start source, it must be enabled in the crossbar, and the corre- sponding pin must be set to open-drain, high-impedance mode (see Section “18. Port Input/Output” on page 203 for more details on Port I/O configuration). Writing a ‘1’ to AD2BUSY provides software contro l of ADC2 whereby conversions are performed "on- demand". During conversion, the AD2BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete. The falling edge of AD2BU SY triggers an interrupt (when enabl ed) and sets the ADC2 interrupt flag (AD2INT). Note: When polling for ADC conversi on completions, the ADC2 interrupt flag (AD2INT) should be used. Converted data is available in the ADC2 data registers, ADC2H and ADC2L, when bit AD2INT is logic 1. Note that when Timer 2 or Time r 3 overflows are used as the conversion source, low byte overflows are used if the timer is in 8-bit mode; and high byte overflows are used if the timer is in 16- bit mode. See Section “24. Timers” on page 287 for timer configuration. 0-50 50 100 Temperature (Celsius) Voltage VTEMP = (Slope x TempC) + Offset Offset (V at 0 Celsius) Slope (V / deg C) TempC = (VTEMP - Offset) / Slope Figure 7.2. Temperature Sensor Transfer Function

90 Rev. 1.2 7.2.2. Tracking Modes The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode. In its default state, the ADC2 input is continuously tracked, except when a conversi on is in progress. When the AD2TM bit is logic 1, ADC2 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track- ing period of 3 SAR clocks (after the start-of-conversio n signal). When the CNVSTR2 signal is used to ini- tiate conversions in low-power tracking mode, ADC2 tracks only when CNVSTR2 is low; conversion begins on the rising edge of CNVSTR2 (see Figure 7.3). Tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are frequently changed, due to the settling time requirements described in Section “7.2.3. Settling Time Requirements” on page 91. Figure 7.3. 10-Bit ADC Track and Conversion Example Timing Write '1' to AD2BUSY, Timer 3, Timer 2 Overflow AD2TM=1 Track Convert Low Power Mode AD2TM=0 Track or Convert Convert Track Low Power or Convert SAR Clocks 123456789 1 0 1 1 1 2 123456789 SAR Clocks B. ADC2 Timing for Internal Trigger Source 123456789 CNVSTR2 (AD2CM[1:0]=10) AD2TM=1 A. ADC2 Timing for External Trigger Source SAR Clocks Track or Convert Convert TrackAD2TM=0 Track Convert Low Power Mode Low Power or Convert 10 11 13 14 10 11

Rev. 1.2 93 Figure 7.6. AMX2SL: AMUX2 Channel Select Register Bits 7-4: UNUSED. Read = 0000b; Write = don’t care. Bits 3-0: AMX2AD3-0: AMX2 Address Bits. 0000-1111b: ADC input multiplexer channel selected per chart below. SFR Page: SFR Address: 0xBB R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - AMX2AD3 AMX2AD2 AMX2AD1 AMX2AD0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 AMX2AD3-0 Single-Ended Measurement AMX2AD3-0 Differential Measurement 1xxx Temperature Sensor 1xxx -

94 Rev. 1.2 Figure 7.7. ADC2CF: ADC2 Configuration Register Bits7-3: AD2SC4-0: ADC2 SAR Co nversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where ADSC refers to the 5-bit value held in bits AD2SC4-AD2SC0. SAR Conversion clock requirements are given in Table 7.1. Bits2-0: UNUSED. Read = 000b; Write = don’t care. SFR Page: SFR Address: 0xBC R/W R/W R/W R/W R/W R/W R/W R/W Reset Value AD2SC4 AD2SC3 AD2SC2 AD2SC1 AD2SC0 - - - 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADSC SYSCLK CLK SAR

96 Rev. 1.2 Figure 7.10. ADC2CN: ADC2 Control Register Bit 7: AD2EN: ADC2 Enable Bit. 0: ADC2 Disabled. ADC2 is in low-power shutdown. 1: ADC2 Enabled. ADC2 is active and ready for data conversions. Bit6: AD2TM: ADC2 Track Mode Bit. 0: Normal Track Mode: When ADC2 is enabled, tracking is continuous unless a conversion is in progress. 1: Low-power Track Mode: Tracking Defined by AD2CM2-0 bits (see below). Bit5: AD2INT: ADC2 Conversion Complete Interrupt Flag. 0: ADC2 has not completed a data conversion since the last time AD2INT was cleared. 1: ADC2 has completed a data conversion. Bit 4: AD2BUSY: ADC2 Busy Bit. Read: 0: ADC2 conversion is complete or a conversion is not currently in progress. AD2INT is set to logic 1 on the falling edge of AD2BUSY. 1: ADC2 conversion is in progress. Write: 0: No Effect. 1: Initiates ADC2 Conversion if AD2CM2-0 = 000b Bits 3-2: AD2CM1-0: ADC2 Start of Conversion Mode Select. When AD2TM = 0: 00: ADC2 conversion initiated on every write of ‘1’ to AD2BUSY. 01: ADC2 conversion initiated on overflow of Timer 3. 10: ADC2 conversion initiated on rising edge of external CNVSTR2 pin. 11: ADC2 conversion initiated on overflow of Timer 2. When AD2TM = 1: 00: Tracking initiated on write of ‘1’ to AD2BUSY and lasts 3 SAR clocks, followed by con- version. 01: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conver- sion. 10: ADC2 tracks only when CNVSTR2 input is logic low; conversion starts on rising CNVSTR2 edge. 11: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion. Bit 1: AD2WINT: ADC2 Windo w Compare Interrupt Flag. 0: ADC2 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC2 Window Comparison Data match has occurred. Bit 0: AD2LJST: ADC2 Left Justify Select. 0: Data in ADC2H:ADC2L registers are right-justified. 1: Data in ADC2H:ADC2L registers are left-justified. SFR Page: SFR Address: 0xE8 (bit addressable) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value AD2EN AD2TM AD2INT AD2BUSY AD2CM1 AD2CM0 AD2WINT AD2LJST 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Rev. 1.2 101 Table 7.1. ADC2 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified Parameter Conditions Min Typ Max Units DC Accuracy Resolution 10 bits Integral Nonlinearity ±0.5 ±1 LSB Differential Nonlinearity Guar anteed Monotonic ±0.5 ±1 LSB Offset Error -12 1 12 LSB Full Scale Error Differential mode -15 -5 5 LSB Offset Temperature Coefficient 3.6 ppm/°C DYNAMIC PERFORMANCE (10 kHz sine-wave Differential input, 1 dB below Full Scale, 200 ksps) Signal-to-Noise Plus Distortion 53 55.5 dB Total Harmonic Distortion Up to the 5 th harmonic -67 dB Spurious-Free Dynamic Range 78 dB Conversion Rate SAR Conversion Clock 3 MHz Conversion Time in SAR Clocks 10 clocks Track/Hold Acquisition Time 300 ns Throughput Rate 200 ksps Analog Inputs ADC Input Voltage Range Single Ended (AIN+ - AGND) Differential (AIN+ - AIN-) -VREF VREF VREF V V Absolute Pin Voltage with respect to AGND Single Ended or Differential 0 AV+ V Input Capacitance 5 pF Temperature Sensor Linearity ±0.2 °C Offset Temp = 0 °C 776 mV Offset Error (Note 1) Temp = 0 °C ±8.9 mV Slope 2.89 mV/°C Slope Error (Note 1) ±63 µV/°C Power Specifications Power Supply Current (VDD sup- plied to ADC2) Operating Mode, 200 ksps 400 900 µA Power Supply Rejection ±0.3 mV/V Note 1: Represents one standard deviation from the mean value.

102 Rev. 1.2

Rev. 1.2 103 8. DACs, 12-Bit Voltage Mode (D AC0 and DAC1, C8051F060/1/2/3) The C8051F060/1/2/3 devices include two on-chip 12-bit voltage-mode Digital-to-Analog Converters (DACs). Each DAC has an output swing of 0 V to (VREF-1LSB) for a corresponding input code range of 0x000 to 0xFFF. The DACs may be enabled/disabled via their corresponding control registers, DAC0CN and DAC1CN. While disabled, the DAC output is maintained in a high-impedance state, and the DAC sup- ply current falls to 1 µA or less. The voltage refe rence for each DAC is supplied at the VREFD pin (C8051F060/2 devices) or the VREF2 pin (C8051F061/3 devices). See Section “9. Voltage Reference 2 (C8051F060/2)” on page 111 or Section “10. Voltage Reference 2 (C8051F061/3)” on page 113 for more information on conf iguring the voltage reference for the DACs. Note that th e BIASE bit described in the voltage reference sections must be set to ‘1’ to use the DACs. DAC0 AV+ AGND REF DAC0 DAC0CN DAC0EN DAC0MD1 DAC0MD0 DAC0DF2 DAC0DF1 DAC0DF0 DAC0HDAC0L Dig. MUX Latch Latch DAC1 AV+ AGND REF DAC1 DAC1CN DAC1EN DAC1MD1 DAC1MD0 DAC1DF2 DAC1DF1 DAC1DF0 DAC1HDAC1L Dig. MUX Latch Latch

8 DAC0H

Figure 8.1. DAC Functional Block Diagram

104 Rev. 1.2 8.1. DAC Output Scheduling Each DAC features a flexible output update mechan ism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. The following examples are written in terms of DAC0, but DAC1 operation is identical. 8.1.1. Update Output On-Demand In its default mode (DAC0CN.[4:3] = ‘00’) the DAC0 output is updated “on-demand” on a write to the high- byte of the DAC0 data register (DAC0H). It is important to note that writes to DAC0L are held, and have no effect on the DAC0 output until a wr ite to DAC0H takes place. If writi ng a full 12-bit word to the DAC data registers, the 12-bit data word is written to the low byte (DAC0L) and high by te (DAC0H) data registers. Data is latched into DAC0 after a writ e to the corresponding DAC0H register, so the write sequence should be DAC0L followed by DAC0H if the full 12-bit resolution is required. The DAC can be used in 8- bit mode by initializing DAC0L to th e desired value (typically 0x00), a nd writing data to only DAC0H (also see Section 8.2 for information on formatting the 12-bit DAC data word within the 16-bit SFR space). 8.1.2. Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conv ersion can be initiated by a timer overflow indepen- dently of the processor, the DAC outputs can use a Timer overflow to schedule an output update event. This feature is useful in systems where the DAC is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latenc y and instruction execution on the timing of the DAC output. When the DAC0MD bits (DAC0CN.[4:3]) are set to ‘01’, ‘10’, or ‘11’, writes to both DAC data regis- ters (DAC0L and DAC0H) are held until an associated Timer overflow event (Timer 3, Timer 4, or Timer 2, respectively) occurs, at which time the DAC0H:DAC0L contents are copied to the DAC input latches allow- ing the DAC output to change to the new value. 8.2. DAC Output Scaling/Justification In some instances, input data should be shifted prio r to a DAC0 write operatio n to properly justify data within the DAC input registers. This action would typi cally require one or more load and shift operations, adding software overhead and slowing DAC throughput. To alleviate this problem, the data-formatting fea- ture provides a means for the user to program the orie ntation of the DAC0 data word within data registers DAC0H and DAC0L. The three DAC0DF bits (DAC0CN.[2:0]) allow the user to specify one of five data word orientations as shown in the DAC0CN register definition. DAC1 is functionally the same as DAC0 described above. The electrical specifications for both DAC0 and DAC1 are given in Table 8.1.

106 Rev. 1.2 Figure 8.4. DAC0CN: DAC0 Control Register Bit7: DAC0EN: DAC0 Enable Bit. 0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode. 1: DAC0 Enabled. DAC0 Output pin is active; DAC0 is operational. Bits6-5: UNUSED. Read = 00b; Write = don’t care. Bits4-3: DAC0MD1-0: DAC0 Mode Bits. 00: DAC output updates occur on a write to DAC0H. 01: DAC output updates occur on Timer 3 overflow. 10: DAC output updates occur on Timer 4 overflow. 11: DAC output updates occur on Timer 2 overflow. Bits2-0: DAC0DF2-0: DAC0 Data Format Bits: 000: The most significant nibble of the DAC0 Data Word is in DAC0H[3:0], while the least significant byte is in DAC0L. 001: The most significant 5-bits of the DAC0 Data Word is in DAC0H[4:0], while the least significant 7-bits are in DAC0L[7:1]. 010: The most significant 6-bits of the DAC0 Data Word is in DAC0H[5:0], while the least significant 6-bits are in DAC0L[7:2]. 011: The most significant 7-bits of the DAC0 Data Word is in DAC0H[6:0], while the least significant 5-bits are in DAC0L[7:3]. 1xx: The most significant 8-bits of the DAC0 Data Word is in DAC0H[7:0], while the least significant 4-bits are in DAC0L[7:4]. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value DAC0EN - - DAC0MD1 DAC0MD0 DAC0DF2 DAC0DF1 DAC0DF0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xD4 DAC0H DAC0L MSB LSB DAC0H DAC0L MSB LSB DAC0H DAC0L MSB LSB DAC0H DAC0L MSB LSB DAC0H DAC0L MSB LSB

108 Rev. 1.2 Figure 8.7. DAC1CN: DAC1 Control Register Bit7: DAC1EN: DAC1 Enable Bit. 0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode. 1: DAC1 Enabled. DAC1 Output pin is active; DAC1 is operational. Bits6-5: UNUSED. Read = 00b; Write = don’t care. Bits4-3: DAC1MD1-0: DAC1 Mode Bits: 00: DAC output updates occur on a write to DAC1H. 01: DAC output updates occur on Timer 3 overflow. 10: DAC output updates occur on Timer 4 overflow. 11: DAC output updates occur on Timer 2 overflow. Bits2-0: DAC1DF2: DAC1 Data Format Bits: 000: The most significant nibble of the DAC1 Data Word is in DAC1H[3:0], while the least significant byte is in DAC1L. 001: The most significant 5-bits of the DAC1 Data Word is in DAC1H[4:0], while the least significant 7-bits are in DAC1L[7:1]. 010: The most significant 6-bits of the DAC1 Data Word is in DAC1H[5:0], while the least significant 6-bits are in DAC1L[7:2]. 011: The most significant 7-bits of the DAC1 Data Word is in DAC1H[6:0], while the least significant 5-bits are in DAC1L[7:3]. 1xx: The most significant 8-bits of the DAC1 Data Word is in DAC1H[7:0], while the least significant 4-bits are in DAC1L[7:4]. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value DAC1EN - - DAC1MD1 DAC1MD0 DAC1DF2 DAC1DF1 DAC1DF0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xD4 DAC1H DAC1L MSB LSB DAC1H DAC1L MSB LSB DAC1H DAC1L MSB LSB DAC1H DAC1L MSB LSB DAC1H DAC1L MSB LSB

Rev. 1.2 109 Table 8.1. DAC Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), No Output Load unless otherwise specified Parameter Conditions Min Typ Max Units Static Performance Resolution 12 bits Integral Nonlinearity ±1.5 LSB Differential Nonlinearity ±1 LSB Output Noise No Output Filter 100 kHz Output Filter 10 kHz Output Filter 250 128 µVrms Offset Error Data Word = 0x014 ±3 ±30 mV Offset Tempco 6 ppm/°C Full-Scale Error ±20 ±60 mV Full-Scale Error Tempco 10 ppm/°C VDD Power Supply Rejection Ratio -60 dB Output Impedance in Shutdown Mode DACnEN = 0 100 k Ω Output Sink Current 300 µA Output Short-Circuit Current Data Word = 0xFFF 15 mA Dynamic Performance Voltage Output Slew Rate Load = 40pF 0.44 V/µs Output Settling Time to 1/2 LSB Load = 40pF, Output swing from code 0xFFF to 0x014 10 µs Output Voltage Swing 0 VREF- 1LSB V Startup Time 10 µs Analog Outputs Load Regulation I L = 0.01mA to 0.3mA at code 0xFFF 60 ppm Power Consumption (each DAC) Power Supply Current (AV+ supplied to DAC) Data Word = 0x7FF 300 500 µA

110 Rev. 1.2

Rev. 1.2 111 9. Voltage Reference 2 (C8051F060/2) The voltage reference circuitry offers full flex ibility in operating the ADC2 and DAC modules. Two voltage reference input pins allow ADC2 and the two DACs to reference an external voltage reference or the on- chip voltage reference output. ADC2 may also refere nce the analog power supply voltage, via the VREF multiplexer shown in Figure 9.1. The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system components or to the voltage re ference input pins shown in Figure 9.1. The maximum load seen by the VREF pin must be less than 200 µA to AGND. Bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to AGND, as shown in Figure 9.1. The Reference Control Register 2, REF2CN (defined in Figure 9.2) enables/disables the internal reference generator and selects the reference input for ADC2. The BIASE bit in REF2CN enables the on-board refer- ence generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin. When disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA (typi- cal) and the output of the buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator, BIASE and REFBE must both be set to logic 1. If the internal reference is not used, REFBE may be set to logic 0. Note that the BIASE bi t must be set to logi c 1 if ADC2 or either DAC is used, regardless of the voltage reference used. If neither ADC2 nor the DACs are being used, both of these bits can be set to logic 0 to conserve power. Bit AD2VRS selects between VREF2 and AV+ for the ADC2 voltage reference source. The electrical specifications for the Voltage Reference are given in Table 9.1. Recommended Bypass Capacitors VREF DAC0 DAC1 Ref VREFD AV+ ADC2 VREF2 Ref 4.7µF0 . 1 µF REF2CN REFBE BIASE TEMPE AD2VRS REFBE BIASE Bias to ADC2, DACs 1.2V Band-Gap EN External Voltage Reference Circuit R VDD Figure 9.1. Voltage Reference Functional Block Diagram

112 Rev. 1.2 The temperature sensor connects to the highest order input of the ADC2 input multiplexer (see Section “7. 10-Bit ADC (ADC2, C8051F060/1/2/3)” on page 87). The TEMPE bit within REF2CN enables and dis- ables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state, and any A/D measurements performed on the sensor while disabled result in meaningless data. Table 9.1. Voltage Reference Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, -40 to +85 °C unless otherwise specified Parameter Conditions Min Typ Max Units Internal Reference (REFBE = 1) Output Voltage 25 °C ambient 2.36 2.43 2.48 V VREF Power Supply Current 50 µA VREF Short-Circuit Current 30 mA VREF Temperature Coefficient 15 ppm/°C Load Regulation Load = 0 to 200 µA to AGND 0.5 ppm/µA VREF Turn-on Time 1 4.7 µF tantalum, 0.1 µF ceramic bypass 2m s VREF Turn-on Time 2 0.1 µF ceramic bypass 20 µs VREF Turn-on Time 3 no bypass cap 10 µs External Reference (REFBE = 0) Input Voltage Range 1.00 (AV+) - 0.3 V Input Current 0 1 µA Figure 9.2. REF2CN: Reference Control Register 2 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bit3: AD2VRS: ADC2 Volt age Reference Select. 0: ADC2 voltage reference from VREF2 pin. 1: ADC2 voltage reference from AV+. Bit2: TEMPE: Temperature Sensor Enable Bit. 0: Internal Temperature Sensor Off. 1: Internal Temperature Sensor On. Bit1: BIASE: ADC/DAC Bias Ge nerator Enable Bit. (Must be ‘1’ if using ADC2 or DACs). 0: Internal Bias Generator Off. 1: Internal Bias Generator On. Bit0: REFBE: Internal Refe rence Buffer Enable Bit. 0: Internal Reference Buffer Off. 1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - AD2VRS TEMPE BIASE REFBE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xD1

Rev. 1.2 113 10. Voltage Referen ce 2 (C8051F061/3) The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system components or to the VREF2 input pin shown in Figure 10.1. The maximum load seen by the VREF pin must be less than 200 µA to AGND. Bypass capacitors of 0.1 µF and 4.7 µF are recom- mended from the VREF pin to AGND, as shown in Figure 10.1. The VREF2 pin provides a voltage reference input for ADC2 and the DACs. ADC2 may also reference the analog power supply voltage, via the VREF multiplexers shown in Figure 10.1. The Reference Control Register 2, REF2CN (defined in Figure 10.2) enables/disables the internal refer- ence generator and selects the reference input for ADC2. The BIASE bit in REF2CN enables the on-board reference generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin. When disabled, the supply current drawn by th e bandgap and buffer amplifier falls to less than 1 µA (typical) and the output of the buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator, BIASE and REFBE must both be set to logic 1. If the internal ref- erence is not used, REFBE may be set to logic 0. Note that the BIASE bit must be set to logic 1 if ADC2 or either DAC is used, regardless of the voltage reference used. If neither ADC2 nor the DACs are being used, both of these bits can be set to logic 0 to conserve power. Bit AD2VRS selects between VREF2 and AV+ for the ADC2 voltage reference source. The electr ical specifications for the Voltage Reference are given in Table 10.1. Recommended Bypass Capacitors VREF DAC0 DAC1 Ref AV+ ADC2 Ref VREF2 4.7µF0 . 1 µF REF2CN REFBE BIASE TEMPE AD2VRS REFBE BIASE Bias to ADC2, DACs 1.2V Band-Gap EN External Voltage Reference Circuit R VDD Figure 10.1. Voltage Reference Functional Block Diagram

114 Rev. 1.2 The temperature sensor connects to the highest order input of the ADC2 input multiplexer (see Section “7. 10-Bit ADC (ADC2, C8051F060/1/2/3)” on page 87). The TEMPE bit within REF2CN enables and dis- ables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state, and any A/D measurements performed on the sensor while disabled result in meaningless data. Table 10.1. Voltage Reference Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, -40 to +85 °C unless otherwise specified Parameter Conditions Min Typ Max Units Internal Reference (REFBE = 1) Output Voltage 25 °C ambient 2.36 2.43 2.48 V VREF Power Supply Current 50 µA VREF Short-Circuit Current 30 mA VREF Temperature Coefficient 15 ppm/°C Load Regulation Load = 0 to 200 µA to AGND 0.5 ppm/µA VREF Turn-on Time 1 4.7 µF tantalum, 0.1 µF ceramic bypass 2m s VREF Turn-on Time 2 0.1 µF ceramic bypass 20 µs VREF Turn-on Time 3 no bypass cap 10 µs External Reference (REFBE = 0) Input Voltage Range 1.00 (AV+) - 0.3 V Input Current 0 1 µA Figure 10.2. REF2CN: Reference Control Register 2 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bit3: AD2VRS: ADC2 Volt age Reference Select. 0: ADC2 voltage reference from VREF2 pin. 1: ADC2 voltage reference from AV+. Bit2: TEMPE: Temperature Sensor Enable Bit. 0: Internal Temperature Sensor Off. 1: Internal Temperature Sensor On. Bit1: BIASE: ADC/DAC Bias Ge nerator Enable Bit. (Must be ‘1’ if using ADC2 or DACs). 0: Internal Bias Generator Off. 1: Internal Bias Generator On. Bit0: REFBE: Internal Refe rence Buffer Enable Bit. 0: Internal Reference Buffer Off. 1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - AD2VRS TEMPE BIASE REFBE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xD1

116 Rev. 1.2 Table 11.1. Voltage Reference Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, -40 to +85 °C unless otherwise specified Parameter Conditions Min Typ Max Units Internal Reference (REFBE = 1) Output Voltage 25 °C ambient 2.36 2.43 2.48 V VREF Power Supply Current 50 µA VREF Short-Circuit Current 30 mA VREF Temperature Coefficient 15 ppm/°C Load Regulation Load = 0 to 200 µA to AGND 0.5 ppm/µA VREF Turn-on Time 1 4.7 µF tantalum, 0.1 µF ceramic bypass 2m s VREF Turn-on Time 2 0.1 µF ceramic bypass 20 µs VREF Turn-on Time 3 no bypass cap 10 µs Figure 11.2. REF2CN: Reference Control Register 2 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bits2-3: RESERVED. Must Write to 00b. Bit1: BIASE: ADC/DAC Bias Ge nerator Enable Bit. (Must be ‘1’ if using ADC2 or DACs). 0: Internal Bias Generator Off. 1: Internal Bias Generator On. Bit0: REFBE: Internal Refe rence Buffer Enable Bit. 0: Internal Reference Buffer Off. 1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - 0 0 BIASE REFBE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xD1

118 Rev. 1.2 Comparator inputs can be externally driven from -0 .25 V to (VDD) + 0.25 V without damage or upset. The complete electrical specifications for the Comparator are given in Table 12.1. The Comparator response time may be configured in software using the CPnMD1-0 bits in register CPT- nMD (see Figure 12.4). Selecting a longer response time reduces the amount of power consumed by the comparator. See Table 12.1 for complete timing and current consumption specifications. The hysteresis of the Comparator is software-progr ammable via its Comparator Control register (CPT- nCN). The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. The Comparator hysteresis is programmed using Bi ts3-0 in the Comparator Control Register CPTnCN (shown in Figure 12.3). The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits. As shown in Figure 12.2, the negative hysteresis can be programmed to three different set- tings, or negative hysteresis can be disabled. In a si milar way, the amount of positive hysteresis is deter- mined by the setting the CPnHYP bits. Positive Hysteresis Voltage (Programmed with CPnHYP Bits) Negative Hysteresis Voltage (Programmed by CPnHYN Bits) VIN- VIN+ INPUTS CIRCUIT CONFIGURATION CPn+ CPn- CPn VIN+ VIN- OUT VOH Positive Hysteresis Disabled Maximum Positive Hysteresis Negative Hysteresis Disabled Maximum Negative Hysteresis OUTPUT VOL Figure 12.2. Comparator Hysteresis Plot

Rev. 1.2 119 Comparator interrupts can be genera ted on either rising- edge and falling-edge outp ut transitions. (For Interrupt enable and priority control, see Section “13.3. Interrupt Handler” on page 151). The rising and/or falling -edge interrupts are enabled using the comparator’s Rising/Falling Edge Interrupt Enable Bits (CPn- RIE and CPnFIE) in their respective Comparator Mode Selection Register (CPTnMD), shown in Figure 12.4. These bits allow the user to control wh ich edge (or both) will cause a comparator interrupt. However, the comparator interrupt must also be enabled in the Extended Interrupt Enable Register (EIE1). The CPnFIF flag is set to logic 1 upon a Comparator falling-ed ge interrupt, and the CPnRIF flag is set to logic 1 upon the Comparator rising-edge interrupt. Once set, these bits remain set until cleared by soft- ware. The output state of a Comparator can be obtained at any time by reading the CPnOUT bit. A Com- parator is enabled by setting its respective CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.Upon enabling a comparator, the output of the comparator is not immediately valid. Before using a com- parator as an interrupt or reset source, software should wait for a minimum of the specified “Power-up time” as specified in Table 12.1, “Comparator Electrical Characteristics,” on page 122. 12.1. Comparator Inputs The Port pins selected as comparator inputs should be configured as analog inputs in the Port 2 Input Con- figuration Register (for details on Port configuration, see Section “18.1.3. Configuring Port Pins as Digital Inputs” on page 207). The inputs for Comparator are on Port 2 as follows: Comparator Input Port PIN CP0 + P2.6 CP0 - P2.7 CP1 + P2.2 CP1 - P2.3 CP2 + P2.4 CP2 - P2.5

120 Rev. 1.2 Figure 12.3. CPTnCN: Comparator 0, 1, and 2 Control Register Bit7: CPnEN: Comparat or Enable Bit. (Please see note below.) 0: Comparator Disabled. 1: Comparator Enabled. Bit6: CPnOUT: Comparator Output State Flag. 0: Voltage on CPn+ < CPn-. 1: Voltage on CPn+ > CPn-. Bit5: CPnRIF: Comparator Rising-Edge Interrupt Flag. 0: No Comparator Rising Edge Interrupt has occurred since this flag was last cleared. 1: Comparator Rising Edge Interrupt has occurred. Must be cleared by software. Bit4: CPnFIF: Comparator Falling-Edge Interrupt Flag. 0: No Comparator Falling-Edge Interrupt has occurred since this flag was last cleared. 1: Comparator Falling-Edge Interrupt has occurred. Must be cleared by software. Bits3-2: CPnHYP1-0: Comparator Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1-0: CPnHYN1-0: Comparator N egative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. NOTE: Upon enabling a comparator, the output of the comparator is not immediately valid. Before using a comparator as an interrupt or reset source, software should wait for a minimum of the specified “Power-up time” as specified in Table 12.1, “Comparator Electrical Characteris- tics,” on page 122. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value CPnEN CPnOUT CPnRIF CPnFIF CPnHYP1 CPnHYP0 CPnHYN1 CPnHYN0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: CPT0CN: 0x88; CPT1CN: 0x88; CPT2CN: 0x88 SFR Pages: CPT0CN: page 1; CPT1CN: page 2; CPT2CN: page 3

Rev. 1.2 121 Figure 12.4. CPTnMD: Comparator Mode Selection Register Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit 5: CPnRIE: Comparator Rising-Edge Interrupt Enable Bit. 0: Comparator rising-edge interrupt disabled. 1: Comparator rising-edge interrupt enabled. Bit 4: CPnFIE: Comparator Falli ng-Edge Interrupt Enable Bit. 0: Comparator falling-edge interrupt disabled. 1: Comparator falling-edge interrupt enabled. Bits3-2: UNUSED. Read = 00b, Write = don’t care. Bits1-0: CPnMD1-CPnMD0: Comparator Mode Select These bits select the response time for the Comparator. R/W R/W R/W R/W R R R/W R/W Reset Value - - CPnRIE CPnFIE - - CPnMD1 CPnMD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: CPT0MD: 0x89; CPT1MD: 0x89; CPT2MD: 0x89 SFR Page: CPT0MD: page 1; CPT1MD: page 2; CPT2MD: page 3 Mode CPnMD1 CPnMD0 Notes 0 0 0 Fastest Response Time 101 - 210 -

311 Lowest Power Consump-

122 Rev. 1.2 Table 12.1. Comparator Electrical Characteristics VDD = 3.0 V, -40 to +85 °C unless otherwise specified. Parameter Conditions Min Typ Max Units Response Time, Mode 0 CPn+ - CPn- = 100 mV 100 ns CPn+ - CPn- = 10 mV 250 ns Response Time, Mode 1 CPn+ - CPn- = 100 mV 175 ns CPn+ - CPn- = 10 mV 500 ns Response Time, Mode 2 CPn+ - CPn- = 100 mV 320 ns CPn+ - CPn- = 10 mV 1100 ns Response Time, Mode 3 CPn+ - CPn- = 100 mV 1050 ns CPn+ - CPn- = 10 mV 5200 ns Common-Mode Rejection Ratio 1.5 4 mV/V Positive Hysteresis 1 CPnHYP1-0 = 00 0 1 mV Positive Hysteresis 2 CPnHYP1-0 = 01 3 5 7 mV Positive Hysteresis 3 CPnHYP1-0 = 10 7 10 15 mV Positive Hysteresis 4 CPnHYP1-0 = 11 15 20 25 mV Negative Hysteresis 1 CPnHYN1-0 = 00 0 1 mV Negative Hysteresis 2 CPnHYN1-0 = 01 3 5 7 mV Negative Hysteresis 3 CPnHYN1-0 = 10 7 10 15 mV Negative Hysteresis 4 CPnHYN1-0 = 11 15 20 25 mV Inverting or Non-Inverting Input Voltage Range -0.25 VDD + 0.25 V Input Capacitance 7 pF Input Bias Current -5 0.001 +5 nA Input Offset Voltage -5 +5 mV Power Supply Power Supply Rejection 0.1 1 mV/V Power-up Time 10 µs Supply Current at DC Mode 0 7.6 µA Mode 1 3.2 µA Mode 2 1.3 µA Mode 3 0.4 µA

Rev. 1.2 123 13. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcon troller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are five 16-bit counter/timers (see description in Section 24), two full-duplex UARTs (see description in Section 22 and Section 23), 256 bytes of internal RAM, 128 byte Spec ial Function Register (SFR) address space (see Section 13.2.6), and 59/24 General-Purpose I/O Pins (see description in Section 18). The CIP-51 also includes on-chip debug hardware (see description in Section 26), and interfaces directly with the MCU’s analog and digital subsystems providing a complete da ta acquisition or control-system solution in a single integrated circuit. - Fully Compatible with MCS-51 Instruction Set - 25 MIPS Peak Throughput with 25 MHz Clock - 0 to 25 MHz Clock Frequency - 256 Bytes of Internal RAM - 59/24 General-Purpose I/O Pins - Extended Interrupt Handler - Reset Input - Power Management Modes - On-chip Debug Logic - Program and Data Memory Security

124 Rev. 1.2 The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (s ee Figure 13.1 for a block diagram). The CIP-51 includes the following features: Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture. In a standar d 8051, all instructions except fo r MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximu m system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion time. Clocks to Execute 1 22 / 333 / 444 / 55 8 Number of Instructions 2 6 5 051 47 3 1 2 1 Figure 13.1. CIP-51 Block Diagram DATA BUS TMP1 TMP2 PRGM. ADDRESS REG. PC INCREMENTER ALU PSW DATA BUS DATA BUS MEMORY INTERFACE MEM_ADDRESSD8 PIPELINE BUFFER DATA POINTER INTERRUPT INTERFACE SYSTEM_IRQs DEBUG_IRQ MEM_CONTROL CONTROL LOGIC A16 PROGRAM COUNTER (PC) STOP CLOCK RESET IDLE POWER CONTROL REGISTER DATA BUS SFR BUS INTERFACE SFR_ADDRESS SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA B REGISTER ACCUMULATOR MEM_WRITE_DATA MEM_READ_DATA SRAM ADDRESS REGISTER SRAM (256 X 8) STACK POINTER

Rev. 1.2 125 Programming and Debugging Support A JTAG-based serial interface is provided for in- system programming of the Flash program memory and communication with on-chip debug support logic. The re-programmable Flash can also be read and changed a single byte at a time by the applicatio n software using the MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control. The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware breakpoints and watch points, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of reg- isters and memory. This method of on-chip debug is completely non-intrusive and non-invasive, requiring no RAM, Stack, timers, or other on-chip resources. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro- vides an integrated development environment (IDE) which interfaces to the CIP-51 via its JTAG port to pro- vide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available. 13.1. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc- tion set; standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and fu nctional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on PSW flags. However, in struction timing is different than that of the stan- dard 8051. 13.1.1. Instruction and CPU Timing In many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles. Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. Conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as o pposed to when the branch is taken. Table 13.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 13.1.2. MOVX Instruction and Program Memory In the CIP-51, the MOVX instruction serves three purposes: accessing on-chip XRAM, accessing off-chip XRAM, and writing to on-chip program Flash memory. The Flash access feature provides a mechanism for user software to update program code and use the program memory space for non-volatile data storage (see Section “16. Flash Memory” on page 177). The External Memory Interface provides a fast access to off-chip XRAM (or memory-mapped peripherals) via the MOVX instruction. Refer to Section “17. External Data Memory Interface and On-Chip XRAM” on page 187 for details.

126 Rev. 1.2 Table 13.1. CIP-51 Instruction Set Summary Mnemonic Description Bytes Clock Cycles Arithmetic Operations ADD A, Rn Add register to A 1 1 ADD A, direct Add direct byte to A 2 2 ADD A, @Ri Add indirect RAM to A 1 2 ADD A, #data Add immediate to A 2 2 ADDC A, Rn Add register to A with carry 1 1 ADDC A, direct Add direct byte to A with carry 2 2 ADDC A, @Ri Add indirect RAM to A with carry 1 2 ADDC A, #data Add immediate to A with carry 2 2 SUBB A, Rn Subtract register from A with borrow 1 1 SUBB A, direct Subtract direct byte from A with borrow 2 2 SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2 SUBB A, #data Subtract imme diate from A with borrow 2 2 INC A Increment A 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 2 INC @Ri Increment indirect RAM 1 2 DEC A Decrement A 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 2 DEC @Ri Decrement indirect RAM 1 2 INC DPTR Increment Data Pointer 1 1 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 8 DA A Decimal adjust A 1 1 Logical Operations ANL A, Rn AND Register to A 1 1 ANL A, direct AND direct byte to A 2 2 ANL A, @Ri AND indirect RAM to A 1 2 ANL A, #data AND immediate to A 2 2 ANL direct, A AND A to direct byte 2 2 ANL direct, #data AND immediate to direct byte 3 3 ORL A, Rn OR Register to A 1 1 ORL A, direct OR direct byte to A 2 2 ORL A, @Ri OR indirect RAM to A 1 2 ORL A, #data OR immediate to A 2 2 ORL direct, A OR A to direct byte 2 2 ORL direct, #data OR immediate to direct byte 3 3 XRL A, Rn Exclusive-OR Register to A 1 1 XRL A, direct Exclusive-OR direct byte to A 2 2 XRL A, @Ri Exclusive-OR indirect RAM to A 1 2 XRL A, #data Exclusive-OR immediate to A 2 2 XRL direct, A Exclusive-OR A to direct byte 2 2

Rev. 1.2 127 XRL direct, #data Exclusive-OR immediate to direct byte 3 3 CLR A Clear A 1 1 CPL A Complement A 1 1 RL A Rotate A left 1 1 RLC A Rotate A left through Carry 1 1 RR A Rotate A right 1 1 RRC A Rotate A right through Carry 1 1 SWAP A Swap nibbles of A 1 1 Data Transfer MOV A, Rn Move Register to A 1 1 MOV A, direct Move direct byte to A 2 2 MOV A, @Ri Move indirect RAM to A 1 2 MOV A, #data Move immediate to A 2 2 MOV Rn, A Move A to Register 1 1 MOV Rn, direct Move direct byte to Register 2 2 MOV Rn, #data Move immediate to Register 2 2 MOV direct, A Move A to direct byte 2 2 MOV direct, Rn Move Register to direct byte 2 2 MOV direct, direct Move direct byte to direct byte 3 3 MOV direct, @Ri Move indirect RAM to direct byte 2 2 MOV direct, #data Move immediate to direct byte 3 3 MOV @Ri, A Move A to indirect RAM 1 2 MOV @Ri, direct Move direct byte to indirect RAM 2 2 MOV @Ri, #data Move immediate to indirect RAM 2 2 MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3 MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3 MOVC A, @A+PC Move code byte relative PC to A 1 3 MOVX A, @Ri Move external data (8-bit address) to A 1 3 MOVX @Ri, A Move A to external data (8-bit address) 1 3 MOVX A, @DPTR Move external data (16-bit address) to A 1 3 MOVX @DPTR, A Move A to external data (16-bit address) 1 3 PUSH direct Push direct byte onto stack 2 2 POP direct Pop direct byte from stack 2 2 XCH A, Rn Exchange Register with A 1 1 XCH A, direct Exchange direct byte with A 2 2 XCH A, @Ri Exchange indirect RAM with A 1 2 XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2 Boolean Manipulation CLR C Clear Carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set Carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement Carry 1 1 CPL bit Complement direct bit 2 2 ANL C, bit AND direct bit to Carry 2 2 Table 13.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description Bytes Clock Cycles

128 Rev. 1.2 ANL C, /bit AND complement of direct bit to Carry 2 2 ORL C, bit OR direct bit to carry 2 2 ORL C, /bit OR complement of direct bit to Carry 2 2 MOV C, bit Move direct bit to Carry 2 2 MOV bit, C Move Carry to direct bit 2 2 JC rel Jump if Carry is set 2 2/3 JNC rel Jump if Carry is not set 2 2/3 JB bit, rel Jump if direct bit is set 3 3/4 JNB bit, rel Jump if direct bit is not set 3 3/4 JBC bit, rel Jump if direct bit is set and clear bit 3 3/4 Program Branching ACALL addr11 Absolute subroutine call 2 3 LCALL addr16 Long subroutine call 3 4 RET Return from subroutine 1 5 RETI Return from interrupt 1 5 AJMP addr11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump (relative address) 2 3 JMP @A+DPTR Jump indirect relative to DPTR 1 3 JZ rel Jump if A equals zero 2 2/3 JNZ rel Jump if A does not equal zero 2 2/3 CJNE A, direct, rel Compare direct byte to A and jump if not equal 3 3/4 CJNE A, #data, rel Compare immediate to A and jump if not equal 3 3/4 CJNE Rn, #data, rel Compare immediate to Register and jump if not equal 33 / 4 CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal 34 / 5 DJNZ Rn, rel Decrement Regist er and jump if not zero 2 2/3 DJNZ direct, rel Decrement direct byte and jump if not zero 3 3/4 NOP No operation 1 1 Table 13.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description Bytes Clock Cycles

Rev. 1.2 129 Notes on Registers, Operands and Addressing Modes: Rn - Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00- 0x7F) or an SFR (0x80-0xFF). #data - 8-bit constant #data16 - 16-bit constant bit - Direct-accessed bit in Data RAM or SFR addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 64K-byte program memory space. There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980.

130 Rev. 1.2 13.2. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different in struction types. There are 256 bytes of internal data memory and 64 k bytes (C8051F060/1/2/3/4/5) or 32 k bytes (C8051F066/7) of internal program memory address space implemented within the CIP-51. The CIP-51 memory organization is shown in Figure 13.2. 13.2.1. Program Memory The CIP-51 has a 64 k byte program memory space. The C8051F060/1/2/3/4/5 devices implement 64 k bytes of this program memory space as in-system re-programmable Flash memory, organized in a contig- uous block from addresses 0x0000 to 0xFFFF. Note: 1024 bytes (0xFC00 to 0xFFFF) of this memory are reserved, and are not available for user program stor age. The C8051F066/7 implement 32 k bytes of this program memory space as in-system re-programmable Flas h memory, organized in a contiguous block from addresses 0x0000 to 0x7FFF. Program memory is normally assumed to be read-only (using the MOVC instruction). However, the CIP-51 can write to program memory by enabling Flash writes, and using the MOVX instruction. This feature pro- vides a mechanism for the CIP-51 to update program code and use the program memory space for non- volatile data storage. Refer to Section “16. Flash Memory” on page 177 for further details. PROGRAM/DATA MEMORY (FLASH) (Direct and Indirect Addressing) 0x00 0x7F Upper 128 RAM (Indirect Addressing Only)0x80 0xFF Special Function Registers (Direct Addressing Only) DATA MEMORY (RAM) General Purpose Registers 0x1F 0x20 0x2F Bit Addressable Lower 128 RAM (Direct and Indirect Addressing) 0x30 INTERNAL DATA ADDRESS SPACE EXTERNAL DATA ADDRESS SPACE XRAM - 4096 Bytes (accessable using MOVX instruction)0x0000 0x0FFF Off-chip XRAM space (C8051F060/2/4/6 Only) 0x1000 0xFFFF FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 0xFFFF RESERVED0xFC00 0xFBFF Scrachpad Memory (data only) 0x1007F 0x10000 Up To (In-System Programmable in 512 Byte Sectors) 0x0000 0xFFFF RESERVED 0x8000 0x7FFF Scrachpad Memory (data only) 0x1007F 0x10000 C8051F066/7 Figure 13.2. Memory Map

Rev. 1.2 131 13.2.2. Data Memory The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca- tions 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, loca tions 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Register s (SFRs) but is physically separate from the SFR space. The addressing mode used by an instructio n when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing above 0x7F will access the SFR spac e. Instructions using in direct addressing above 0x7F access the upper 128 bytes of data memory. Figure 13.2 illustrates the data memory organization of the CIP-51. 13.2.3. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen- eral-purpose registers. Each bank consists of ei ght byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in Figure 13.16). This allows fast con- text switching when entering subroutines and interr upt service routines. Indi rect addressing modes use registers R0 and R1 as index registers. 13.2.4. Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (a bit source or destinati on operand as opposed to a byte source or destina- tion). The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22.3h moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag. 13.2.5. Stack A programmer's stack can be located anywhere in the 256 byte data memory. The stack area is designated using the Stack Pointer (SP, address 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07; therefore, the first value pushed on th e stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. The MCUs also have built-in hardware for a stack record which is accessed by the debug logic. The stack record is a 32-bit shift register, where each PUSH or increment SP pushes one record bit onto the register,

132 Rev. 1.2 and each CALL pushes two record bits onto the register. (A POP or decrement SP pops one record bit, and a RET pops two record bits, also.) The stack record circuitry can also detect an overflow or underflow on the 32-bit shift register, and can notify the debug software even with the MCU running at speed. 13.2.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the Special Function Registers (SFRs). The SFRs provide control and data exchang e with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 805 1 implementation as well as implementing additional SFRs used to configure and access the sub-systems uni que to the MCU. This allows the addition of new functionality while retaining compatibility wi th the MCS-51™ instru ction set. Table 13.2 lists the SFRs implemented in the CIP-51 System Controller. The SFRs are accessed whenever the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit- addressable as well as byte-addressable. All ot her SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corr esponding pages of the datasheet, as indicated in Table 13.3, for a detailed description of each register. 13.2.6.1.SFR Paging The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory address space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to 0xFF can access up to 256 SFRs. The C8051F06x family of devices utilizes five SFR pages: 0, 1, 2, 3, and F. SFR pages are selected using the Special Functi on Register Page Select ion register, SFRPAGE (see Figure 13.10). The procedure for reading and writing an SFR is as follows: 1. Select the appropriate SFR page number using the SFRPAGE register. 2. Use direct accessing mode to read or write t he special function register (MOV instruction). 13.2.6.2.Interrupts and SFR Paging When an interrupt occurs, the SFR Page Register will automatically switch to the SFR page containing the flag bit that caused the interrupt. The automatic SFR Page switch function conveniently removes the bur- den of switching SFR pages from the interrupt service routine. Upon execution of the RETI instruction, the SFR page is automatically restored to the SFR Page in use prior to the interrupt. This is accomplished via a three-byte SFR Page Stack. The top byte of the stack is SFRPAGE, the current SFR Page. The second byte of the SFR Page Stack is SFRNEXT. The third, or bottom byte of the SFR Page Stack is SFRLAST. On interrupt, the current SFRPAGE value is pushed to the SFRNEXT byte, and the value of SFRNEXT is pushed to SFRLAST. Hardware then loads SFRPAGE with the SFR Page containing the flag bit associated with the interrupt. On a return from interrupt, the SFR Page Stack is popped resulting in the value of SFRN- EXT returning to the SFRPAGE register, thereby restoring the SFR page context without software interven- tion. The value in SFRLAST (0x00 if there is no SFR Page value in the bottom of the stack) of the stack is placed in SFRNEXT register. If desired, the valu es stored in SFRNEXT and SFRLAST may be modified during an interrupt, enabling the CPU to return to a different SFR Page upon execution of the RETI instruc- tion (on interrupt exit). Modifying registers in the SFR Page Stack does not cause a push or pop of the stack. Only interrupt calls and returns will cause push/pop operations on the SFR Page Stack.

Rev. 1.2 133 Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enab le Bit located in the SFR Page Control Register (SFRPGCN). This function defaults to ‘enabled’ upon reset. In this way, the autoswitching function will be enabled unless dis- abled in software. A summary of the SFR locations (address and SFR page) is provided in Table 13.2. in the form of an SFR memory map. Each memory location in the map has an SFR page row, denoting the page in which that SFR resides. Note that certain SFRs are accessible from ALL SFR pages, and are denoted by the “ (ALL PAGES)” designation. For example, the Port I/O registers P0, P1, P2, and P3 all have the “(ALL PAGES)” designation, indicating these SFRs are accessible from all SFR pages regardless of the SFRPAGE register value. SFRNEXT SFRPAGE SFRLAST CIP-51 Interrupt Logic SFRPGCN Bit Figure 13.3. SFR Page Stack

134 Rev. 1.2 13.2.6.3.SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts. In this example, the SFR Page Cont rol is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51 is executing in-line code that is writing values to Port 5 (SFR “P5”, located at address 0xD8 on SFR Page 0x0F). The device is also using the Programmable Counter Array (PCA) and the 10-bit ADC (ADC2) window comparator to monitor a voltage. The PCA is timing a critical control function in its interrupt service routine (ISR), so its interrupt is enabled and is set to high priority. The ADC2 is monitoring a voltage that is less important, but to minimize the software overhead its window comparator is being used with an associ- ated ISR that is set to low priority. At this point, the SFR page is set to access the Port 5 SFR (SFRPAGE = 0x0F). See Figure 13.4 below. 0x0F (Port 5) SFRPAGE SFRLAST SFRNEXT SFR Page Stack SFR's Figure 13.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5

Rev. 1.2 135 While CIP-51 executes in-line code (writing values to Port 5 in this example), ADC2 Window Comparator Interrupt occurs. The CIP-51 vectors to the ADC2 Window Co mparator ISR and pushes the current SFR Page value (SFR Page 0x0F) into SFRNEXT in the SFR Page Stack. The SFR page needed to access ADC2’s SFRs is then automatically placed in the SFRPAGE register (SFR Page 0x02). SFRPAGE is con- sidered the “top” of the SFR Page Stack. Software can now access the ADC2 SFRs. Software may switch to any SFR Page by writing a new value to the SFRPAGE register at any time during the ADC2 ISR to access SFRs that are not on SFR Page 0x02. See Figure 13.5 below. 0x02 (ADC2) 0x0F (Port 5) SFRPAGE SFRLAST SFRNEXT SFRPAGE pushed to SFRNEXT SFR Page 0x02 Automatically pushed on stack in SFRPAGE on ADC2 interrupt Figure 13.5. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs

136 Rev. 1.2 While in the ADC2 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while the ADC2 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically plac e the SFR page needed to access the PCA’s special function registers into the SFRPAGE register, SFR Page 0x00. The value that was in the SFRPAGE register before the PCA interrupt (SFR Page 2 for ADC2) is pushed down the stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register before the PCA interrupt (in this case SFR Page 0x0F for Port 5) is pushed down to the SFRLAST register, the “bottom” of the stack. Note that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be overwritten. See Figure 13.6 below. 0x00 (PCA) 0x02 (ADC2) 0x0F (Port 5) SFRPAGE SFRLAST SFRNEXT SFR Page 0x00 Automatically pushed on stack in SFRPAGE on PCA interrupt SFRPAGE pushed to SFRNEXT SFRNEXT pushed to SFRLAST Figure 13.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR

Rev. 1.2 137 On exit from the PCA interrupt service routine, the CIP-51 will retu rn to the ADC2 Window Comparator ISR. On execution of the RETI instruction, SFR Page 0x00 used to access the PCA registers will be auto- matically popped off of the SFR Pa ge Stack, and the contents of th e SFRNEXT register will be moved to the SFRPAGE register. Software in the ADC2 ISR can co ntinue to access SFRs as it did prior to the PCA interrupt. Likewise, the contents of SFRLAST are mo ved to the SFRNEXT register. Recall this was the SFR Page value 0x0F being used to access Port 5 before the ADC2 interrupt occurred. See Figure 13.7 below. 0x02 (ADC2) 0x0F (Port 5) SFRPAGE SFRLAST SFRNEXT SFR Page 0x00 Automatically popped off of the stack on return from interrupt SFRNEXT popped to SFRPAGE SFRLAST popped to SFRNEXT Figure 13.7. SFR Page Stack Upon Return From PCA Interrupt

138 Rev. 1.2 On the execution of the RETI instruction in the ADC2 Window Comparator ISR, the value in SFRPAGE register is overwritten with the contents of SFRNEXT. The CIP-51 may now access the Port 5 SFR bits as it did prior to the interrupts occurring. See Figure 13.8 below. Note that in the above example, all three bytes in the SFR Page Stack are accessible via the SFRPAGE, SFRNEXT, and SFRLAST special function registers. If the stack is altered while servicing an interrupt, it is possible to return to a different SFR Page upon interrupt exit than selected prior to the interrupt call. Direct access to the SFR Page stack can be useful to enable real-time operating systems to control and manage context switching between multiple tasks. Push operations on the SFR Page Stack only occur on interrupt service, and pop operations only occur on interrupt exit (execution on the RETI instruction). The automatic switching of the SFRPAGE and operation of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFRPGCN). See Figure 13.9. 0x0F (Port 5) SFRPAGE SFRLAST SFRNEXT SFR Page 0x02 Automatically popped off of the stack on return from interrupt SFRNEXT popped to SFRPAGE Figure 13.8. SFR Page Stack Upon Return From ADC2 Window Interrupt

Rev. 1.2 141 Table 13.2. Special Function Register (SFR) Memory Map A D D R E S S SFR P A G E F SPI0CN CAN0CN DMA0CF PCA0L DMA0CTL PCA0H DMA0CTH PCA0CPL0 DMA0CSL PCA0CPH0 DMA0CSH PCA0CPL1 DMA0BND PCA0CPH1 DMA0ISW WDTCN (ALL PAGES) F B (ALL PAGES) EIP1 (ALL PAGES) EIP2 (ALL PAGES) F ADC0CN ADC1CN ADC2CN PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 PCA0CPL4 PCA0CPH4 RSTSRC F ACC (ALL PAGES) PCA0CPL5 XBR0 PCA0CPH5 XBR1 XBR2 XBR3 EIE1 (ALL PAGES) EIE2 (ALL PAGES) F PCA0CN CAN0DATL DMA0CN PCA0MD CAN0DATH DMA0DAL PCA0CPM0 CAN0ADR DMA0DAH PCA0CPM1 CAN0TST DMA0DSL PCA0CPM2 DMA0DSH PCA0CPM3 DMA0IPT PCA0CPM4 DMA0IDT PCA0CPM5 F PSW (ALL PAGES) REF0CN REF1CN REF2CN DAC0L DAC1L DAC0H DAC1H DAC0CN DAC1CN F TMR2CN TMR3CN TMR4CN TMR2CF TMR3CF TMR4CF RCAP2L RCAP3L RCAP4L RCAP2H RCAP3H RCAP4H TMR2L TMR3L TMR4L TMR2H TMR3H TMR4H SMB0CR F SMB0CN CAN0STA SMB0STA SMB0DAT SMB0ADR ADC0GTL ADC2GTL ADC0GTH ADC2GTH ADC0LTL ADC2LTL ADC0LTH ADC2LTH F IP (ALL PAGES) SADEN0 AMX2CF ADC0CPT AMX0SL AMX2SL ADC0CCF ADC0CF ADC1CF ADC2CF ADC0L ADC1L ADC2L ADC0H ADC1H ADC2H

142 Rev. 1.2 F (ALL PAGES) FLSCL FLACL F IE (ALL PAGES) SADDR0 P1MDIN P2MDIN F (ALL PAGES) EMI0TC EMI0CN EMI0CF P0MDOUT P1MDOUT P2MDOUT P3MDOUT F SCON0 SCON1 SBUF0 SBUF1 SPI0CFG SPI0DAT P4MDOUT SPI0CKR P5MDOUT P6MDOUT P7MDOUT F (ALL PAGES) SSTA0 SFRPGCN CLKSEL F TCON CPT0CN CPT1CN CPT2CN TMOD CPT0MD CPT1MD CPT2MD TL0 OSCICN TL1 OSCICL TH0 OSCXCN TH1 CKCON PSCTL F (ALL PAGES) SP (ALL PAGES) DPL (ALL PAGES) DPH (ALL PAGES) SFRPAGE (ALL PAGES) SFRNEXT (ALL PAGES) SFRLAST (ALL PAGES) PCON (ALL PAGES) Table 13.2. Special Function Register (SFR) Memory Map

Rev. 1.2 143 Table 13.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description Page No. B 0xF0 All Pages B Register page 150 ACC 0xE0 All Pages Accumulator page 150 ADC0CCF 0xBB F ADC0 Calibration Coefficient page 68 ADC0CF 0xBC 0 ADC0 Configuration page 58 ADC0CN 0xE8 0 ADC0 Control page 60 ADC0CPT 0xBA F ADC0 Calibration Pointer page 68 ADC0GTH 0xC5 0 ADC0 Greater-Than High page 69 ADC0GTL 0xC4 0 ADC0 Greater-Than Low page 69 ADC0H 0xBF 0 ADC0 Data Word High page 63 ADC0L 0xBE 0 ADC0 Data Word Low page 63 ADC0LTH 0xC7 0 ADC0 Less-Than High page 70 ADC0LTL 0xC6 0 ADC0 Less-Than Low page 70 ADC1CF 0xBC 1 ADC1 Configuration page 59 ADC1CN 0xE8 1 ADC1 Control page 61 ADC1H 0xBF 1 ADC1 Data Word High page 65 ADC1L 0xBE 1 ADC1 Data Word Low page 65 ADC2CF 0xBC 2 ADC2 Configuration page 94 ADC2CN 0xE8 2 ADC2 Control page 96*5 ADC2GTH 0xC5 2 ADC2 Greater-Than High page 97*5 ADC2GTL 0xC4 2 ADC2 Greater-Than Low page 97*5 ADC2H 0xBF 2 ADC2 Data Word High page 95*5 ADC2L 0xBE 2 ADC2 Data Word Low page 95*5 ADC2LTH 0xC7 2 ADC2 Less-Than High page 98*5 ADC2LTL 0xC6 2 ADC2 Less-Than Low page 98*5 AMX0SL 0xBB 0 ADC0 Multiplexer Channel Select page 57 AMX2CF 0xBA 2 ADC2 Analog Mu ltiplexer Configuration page 94*5 AMX2SL 0xBB 2 ADC2 Analog Multiplexer Channel Select page 93*5 CAN0ADR 0xDA 1 CAN0 Address page 232*5 CAN0CN 0xF8 1 CAN0 Control page 232*5 CAN0DATH 0xD9 1 CAN0 Data High page 231*5 CAN0DATL 0xD8 1 CAN0 Data Low page 231*5 CAN0STA 0xC0 1 CAN0 Status page 233*5 CAN0TST 0xDB 1 CAN0 Test page 233*5 CKCON 0x8E 0 Clock Control page 293 CLKSEL 0x97 F Oscillator Clock Se lection Register page 173 CPT0CN 0x88 1 Comparator 0 Control page 120 CPT0MD 0x89 1 Comparator 0 Configuration page 121 CPT1CN 0x88 2 Comparator 1 Control page 120 CPT1MD 0x89 2 Comparator 1 Configuration page 121 CPT2CN 0x88 3 Comparator 2 Control page 120

144 Rev. 1.2 CPT2MD 0x89 3 Comparator 2 Configuration page 121 DAC0CN 0xD4 0 DAC0 Control page 106*5 DAC0H 0xD3 0 DAC0 High page 105*5 DAC0L 0xD2 0 DAC0 Low page 105*5 DAC1CN 0xD4 1 DAC1 Control page 108*5 DAC1H 0xD3 1 DAC1 High page 107*5 DAC1L 0xD2 1 DAC1 Low page 107*5 DMA0BND 0xFD 3 DMA0 Instruction Boundary page 83 DMA0CF 0xF8 3 DMA0 Configuration page 81 DMA0CN 0xD8 3 DMA0 Control page 80 DMA0CSH 0xFC 3 DMA0 Repeat Counter Status High Byte page 85 DMA0CSL 0xFB 3 DMA0 Repeat Counter Status Low Byte page 85 DMA0CTH 0xFA 3 DMA0 Repeat Counter Limit High Byte page 85 DMA0CTL 0xF9 3 DMA0 Repeat Counter Limit Low Byte page 85 DMA0DAH 0xDA 3 DMA0 Data Address Beginning High Byte page 84 DMA0DAL 0xD9 3 DMA0 Data Addr ess Beginning Low Byte page 84 DMA0DSH 0xDC 3 DMA0 Data Address Pointer High Byte page 84 DMA0DSL 0xDB 3 DMA0 Data Address Pointer Low Byte page 84 DMA0IDT 0xDE 3 DMA0 Instru ction Write Data page 82 DMA0IPT 0xDD 3 DMA0 Instru ction Write Address page 82 DMA0ISW 0xFE 3 DMA0 Inst ruction Status page 83 DPH 0x83 All Pages Data Pointer High page 148 DPL 0x82 All Pages Data Pointer Low page 148 EIE1 0xE6 All Pages Extended Interrupt Enable 1 page 156 EIE2 0xE7 All Pages Extended Interrupt Enable 2 page 157 EIP1 0xF6 All Pages Extended Interrupt Priority 1 page 158 EIP2 0xF7 All Pages Extended Interrupt Priority 2 page 159 EMI0CF 0xA3 0 EMIF Configuration page 189 EMI0CN 0xA2 0 EMIF Control page 189*1 EMI0TC 0xA1 0 EMIF Timing Control page 194*1 FLACL 0xB7 F Flash Access Limit page 182 FLSCL 0xB7 0 Flash Scale page 184 IE 0xA8 All Pages Interrupt Enable page 154 IP 0xB8 All Pages Interrupt Priority page 155 OSCICL 0x8B F Internal Oscillator Calibration page 172 OSCICN 0x8A F Internal Os cillator Control page 172 OSCXCN 0x8C F External O scillator Control page 174 P0 0x80 All Pages Port 0 Latch page 214 P0MDOUT 0xA4 F Port 0 Output Mode Configuration page 214 P1 0x90 All Pages Port 1 Latch page 215 P1MDIN 0xAD F Port 1 Input Mode page 215 P1MDOUT 0xA5 F Port 1 Output Mode Configuration page 216 P2 0xA0 All Pages Port 2 Latch page 216 Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description Page No.

Rev. 1.2 145 P2MDIN 0xAE F Port 2 Input Mode page 217 P2MDOUT 0xA6 F Port 2 Output Mode Configuration page 217 P3 0xB0 All Pages Port 3 Latch page 218*1 P3MDOUT 0xA7 F Port 3 Output Mode Configuration page 218*1 P4 0xC8 F Port 4 Latch page 221*1 P4MDOUT 0x9C F Port 4 Output Mode Configuration page 221*1 P5 0xD8 F Port 5 Latch page 222*1 P5MDOUT 0x9D F Port 5 Output Mode Configuration page 222*1 P6 0xE8 F Port 6 Latch page 223*1 P6MDOUT 0x9E F Port 6 Output Mode Configuration page 223*1 P7 0xF8 F Port 7 Latch page 224*1 P7MDOUT 0x9F F Port 7 Output Mode Configuration page 224*1 PCA0CN 0xD8 0 PCA Control page 312 PCA0CPH0 0xFC 0 PCA Capture 0 High page 316 PCA0CPH1 0xFE 0 PCA Capture 1 High page 316 PCA0CPH2 0xEA 0 PCA Capture 2 High page 316 PCA0CPH3 0xEC 0 PCA Capture 3 High page 316 PCA0CPH4 0xEE 0 PCA Capture 4 High page 316 PCA0CPH5 0xE2 0 PCA Capture 5 High page 316 PCA0CPL0 0xFB 0 PCA Capture 0 Low page 316 PCA0CPL1 0xFD 0 PCA Capture 1 Low page 316 PCA0CPL2 0xE9 0 PCA Capture 2 Low page 316 PCA0CPL3 0xEB 0 PCA Capture 3 Low page 316 PCA0CPL4 0xED 0 PCA Capture 4 Low page 316 PCA0CPL5 0xE1 0 PCA Capture 5 Low page 316 PCA0CPM0 0xDA 0 PCA Module 0 Mode Register page 314 PCA0CPM1 0xDB 0 PCA Module 1 Mode Register page 314 PCA0CPM2 0xDC 0 PCA Module 2 Mode Register page 314 PCA0CPM3 0xDD 0 PCA Module 3 Mode Register page 314 PCA0CPM4 0xDE 0 PCA Module 4 Mode Register page 314 PCA0CPM5 0xDF 0 PCA Module 5 Mode Register page 314 PCA0H 0xFA 0 PCA Counter High page 315 PCA0L 0xF9 0 PCA Counter Low page 315 PCA0MD 0xD9 0 PCA Mode page 313 PCON 0x87 All Pages Power Control page 161 PSCTL 0x8F 0 Program Store R/W Control page 185 PSW 0xD0 All Pages Program Status Word page 149 RCAP2H 0xCB 0 Timer/Counter 2 Capture/Reload High page 301 RCAP2L 0xCA 0 Timer/Counter 2 Capture/Reload Low page 301 RCAP3H 0xCB 1 Timer/Counter 3 Capture/Reload High page 301 RCAP3L 0xCA 1 Timer/Counter 3 Capture/Reload Low page 301 RCAP4H 0xCB 2 Timer/Counter 4 Capture/Reload High page 301 RCAP4L 0xCA 2 Timer/Counter 4 Capture/Reload Low page 301 Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description Page No.

146 Rev. 1.2 REF0CN 0xD1 0 Voltage Reference Control 0 page 62 REF1CN 0xD1 1 Voltage Reference Control 1 page 62 REF2CN 0xD1 2 Voltage Reference Control 2 page 112*2, page 114*3, page 116*5 RSTSRC 0xEF 0 Reset Source page 168 SADDR0 0xA9 0 UART 0 Slave Address page 276 SADEN0 0xB9 0 UART 0 Slave Address Enable page 276 SBUF0 0x99 0 UART 0 Data Buffer page 276 SBUF1 0x99 1 UART 1 Data Buffer page 283 SCON0 0x98 0 UART 0 Control page 274 SCON1 0x98 1 UART 1 Control page 282 SFRLAST 0x86 All Pages SFR Page Stack Access Register page 140 SFRNEXT 0x85 All Pages SFR Page Register page 140 SFRPAGE 0x84 All Pages SFR Page Register page 139 SFRPGCN 0x96 F SFR Page Control Register page 139 SMB0ADR 0xC3 0 SMBus Slave Address page 246 SMB0CN 0xC0 0 SMBus Control page 243 SMB0CR 0xCF 0 SMBus Clock Rate page 244 SMB0DAT 0xC2 0 SMBus Data page 245 SMB0STA 0xC1 0 SMBus Status page 247 SP 0x81 All Pages Stack Pointer page 148 SPI0CFG 0x9A 0 SPI Configuration page 258 SPI0CKR 0x9D 0 SPI Clock Rate Control page 260 SPI0CN 0xF8 0 SPI Control page 259 SPI0DAT 0x9B 0 SPI Data page 261 SSTA0 0x91 0 UART 0 Status page 275 TCON 0x88 0 Timer/Counter Control page 291 TH0 0x8C 0 Timer/Counter 0 High page 294 TH1 0x8D 0 Timer/Counter 1 High page 294 TL0 0x8A 0 Timer/Counter 0 Low page 294 TL1 0x8B 0 Timer/Counter 1 Low page 294 TMOD 0x89 0 Timer/Counter Mode page 292 TMR2CF 0xC9 0 Timer/Counter 2 Configuration page 300 TMR2CN 0xC8 0 Timer/Counter 2 Control page 299 TMR2H 0xCD 0 Timer/Counter 2 High page 302 TMR2L 0xCC 0 Timer/Counter 2 Low page 301 TMR3CF 0xC9 1 Timer/Counter 3 Configuration page 300 TMR3CN 0xC8 1 Timer/Counter 3 Control page 299 TMR3H 0xCD 1 Timer/Counter 3 High page 302 TMR3L 0xCC 1 Timer/Counter 3 Low page 301 TMR4CF 0xC9 2 Timer/Counter 4 Configuration page 300 TMR4CN 0xC8 2 Timer/Counter 4 Control page 299 TMR4H 0xCD 2 Timer/Counter 4 High page 302 Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description Page No.

Rev. 1.2 147 TMR4L 0xCC 2 Timer/Counter 4 Low page 301 WDTCN 0xFF All Pages Watchdog Timer Control page 167 XBR0 0xE1 F Port I/O Crossbar Control 0 page 210 XBR1 0xE2 F Port I/O Crossbar Control 1 page 211 XBR2 0xE3 F Port I/O Crossbar Control 2 page 212 XBR3 0xE4 F Port I/O Crossbar Control 3 page 213 *1 Refers to a register in the C8051F060/2/4/6 only. *2 Refers to a register in the C8051F060/2 only. *3 Refers to a register in the C8051F061/3 only. *4 Refers to a register in the C8051F060/1/2/3 only. *5 Refers to a register in the C8051F064/5/6/7 only. Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description Page No.

Rev. 1.2 149 Figure 13.16. PSW: Program Status Word Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to 0 by all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag. This bit is set when the last arithmetic operation resulted in a carry into (addition) or a bor- row from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic opera- tions. Bit5: F0: User Flag 0. This is a bit-addressable, general purpose flag for use under software control. Bits4-3: RS1-RS0: Register Bank Select. These bits select which register bank is used during register accesses. Bit2: OV: Overflow Flag. This bit is set to 1 under the following circumstances:

• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition. The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. Bit1: F1: User Flag 1. This is a bit-addressable, general purpose flag for use under software control. Bit0: PARITY: Parity Flag. This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value CY AC F0 RS1 RS0 OV F1 PARITY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: SFR Page: 0xD0 All Pages RS1 RS0 Register Bank Address 0 0 0 0x00 - 0x07 0 1 1 0x08 - 0x0F 1 0 2 0x10 - 0x17 1 1 3 0x18 - 0x1F

Rev. 1.2 151 13.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 22 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peri pherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt- pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instructio n is complete, the CPU generates an LCALL to a prede- termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (T he interrupt-pending flag is set to logic 1 regard- less of the interrupt's enable/disable state.) Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR (IE-EIE2). Ho wever, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interr upt request will be gen erated immediately and the CPU will re-enter the ISR after the completion of the next instruction. 13.3.1. MCU Interrupt Sources and Vectors The MCUs support 22 interrupt sources. Software can simulate an interrupt event by setting any interrupt- pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated wit h the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and cont rol bits are summarized in Table 13.4. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 13.3.2. External Interrupts The external interrupt sources (/INT0 and /INT1) are c onfigurable as active-low level-sensitive or active- low edge-sensitive inputs depending on the setting of bits IT0 (TCON.0) and IT1 (TCON.2). IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts, respec- tively. If an /INT0 or /INT1 external interrupt is conf igured as edge-sensitive, the corresponding interrupt- pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag follows the state of the external interrupt's input pin. The exter- nal interrupt source must hold the input active until the interrupt request is recognized. It must then deacti- vate the interrupt request before execution of the ISR completes or another interr upt request will be generated.

152 Rev. 1.2 Table 13.4. Interrupt Summary Interrupt Source Interrupt Vector Priority Order Pending Flag Bit addressable Cleared by HW Enable Flag Priority Control Reset 0x0000 Top None N/A N/A Always Enabled Always Highest External Interrupt 0 (/INT0) 0x0003 0 IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP .0) Timer 0 Overflow 0x000B 1 TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1) External Interrupt 1 (/INT1) 0x0013 2 IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP .2) Timer 1 Overflow 0x001B 3 TF1 (TCON.7) Y Y ET1 (IE.3) PT1 (IP.3) UART0 0x0023 4 RI0 (SCON0.0) TI0 (SCON0.1) Y ES0 (IE.4) PS0 (IP .4) Timer 2 0x002B 5 TF2 (TMR2CN.7) Y ET2 (IE.5) PT2 (IP.5) Serial Peripheral Interface 0x0033 6 SPIF (SPI0CN.7) WCOL (SPI0CN.6) MODF (SPI0CN.5) RXOVRN (SPI0CN.4) Y ESPI0 (EIE1.0) PSPI0 (EIP1.0) SMBus Interface 0x003B 7 SI (SMB0CN.3) Y ESMB0 (EIE1.1) PSMB0 (EIP1.1) ADC0 Window Comparator 0x0043 8 AD0WINT (ADC0CN.1) Y EWADC0 (EIE1.2) PWADC0 (EIP1.2) Programmable Counter Array 0x004B 9 CF (PCA0CN.7) CCFn (PCA0CN.n) Y EPCA0 (EIE1.3) PPCA0 (EIP1.3) Comparator 0 0x0053 10 CP0FIF/CP0RIF (CPT0CN.4/.5) Y CP0IE (EIE1.4) PCP0 (EIP1.4) Comparator 1 0x005B 11 CP1FIF/CP1RIF (CPT1CN.4/.5) Y CP1IE (EIE1.5) PCP1 (EIP1.5) Comparator 2 0x0063 12 CP2FIF/CP2RIF (CPT2CN.4/.5) Y CP2IE (EIE1.6) PCP2 (EIP1.6) ADC0 End of Conversion 0x006B 13 ADC0INT (ADC0CN.5) Y EADC0 (EIE1.7) PADC0 (EIP1.7) Timer 3 0x0073 14 TF3 (TMR3CN.7) Y ET3 (EIE2.0) PT3 (EIP2.0) ADC1 End of Conversion 0x007B 15 ADC1INT (ADC1CN.5) Y EADC1 (EIE2.1) PADC1 (EIP2.1) Timer 4 0x0083 16 TF4 (TMR4CN.7) Y ET4 (EIE2.2) PT4 (EIP2.2) ADC2 Window Comparator 0x008B 17 AD2WINT (ADC2CN.1) Y EWADC2 (EIE2.3) PWADC2 (EIP2.3) ADC2 End of Conversion 0x0093 18 AD2INT (ADC2CN.5) Y EADC2 (EIE2.4) PADC2 (EIP2.4) CAN Interrupt 0x009B 19 CAN0CN.7 Y Y ECAN0 (EIE2.5) PCAN0 (EIP2.5) UART1 0x00A3 20 RI1 (SCON1.0) TI1 (SCON1.1) Y ES1 (EIP2.6) PS1 (EIP2.6) DMA0 Interrupt 0x00AB 21 DMA0INT (DMA0CN.6) Y EDMA0 (EIE2.7) PDMA0 (EIP2.7)

Rev. 1.2 153 13.3.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 13.4. 13.3.4. Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is execut ed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the in terrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycl es to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction.

154 Rev. 1.2 13.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). Figure 13.19. IE: Interrupt Enable Bit7: EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set- tings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. Bit6: IEGF0: General Purpose Flag 0. This is a general purpose flag for use under software control. Bit5: ET2: Enabler Timer 2 Interrupt. This bit sets the masking of the Timer 2 interrupt. 0: Disable Timer 2 interrupt. 1: Enable interrupt requests generated by the TF2 flag. Bit4: ES0: Enable UART0 Interrupt. This bit sets the masking of the UART0 interrupt. 0: Disable UART0 interrupt. 1: Enable UART0 interrupt. Bit3: ET1: Enable Timer 1 Interrupt. This bit sets the masking of the Timer 1 interrupt. 0: Disable all Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag. Bit2: EX1: Enable Exte rnal Interrupt 1. This bit sets the masking of external interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the /INT1 pin. Bit1: ET0: Enable Timer 0 Interrupt. This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. Bit0: EX0: Enable Exte rnal Interrupt 0. This bit sets the masking of external interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 pin. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EA IEGF0 ET2 ES0 ET1 EX1 ET0 EX0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: SFR Page: 0xA8 All Pages

Rev. 1.2 155 Figure 13.20. IP: Interrupt Priority Bits7-6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interr upt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt set to low priority level. 1: Timer 2 interrupt set to high priority level. Bit4: PS0: UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupt set to low priority level. 1: UART0 interrupt set to high priority level. Bit3: PT1: Timer 1 Interr upt Priority Control. This bit sets the priority of the Timer 1 interrupt. 0: Timer 1 interrupt set to low priority level. 1: Timer 1 interrupt set to high priority level. Bit2: PX1: External Interr upt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 0: External Interrupt 1 set to low priority level. 1: External Interrupt 1 set to high priority level. Bit1: PT0: Timer 0 Interr upt Priority Control. This bit sets the priority of the Timer 0 interrupt. 0: Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. Bit0: PX0: External Interr upt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - PT2 PS0 PT1 PX1 PT0 PX0 11000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: SFR Page: 0xB8 All Pages

156 Rev. 1.2 Figure 13.21. EIE1: Extended Interrupt Enable 1 Bit7: EADC0: Enable ADC0 End of Conversion Interrupt. This bit sets the masking of the ADC0 End of Conversion Interrupt. 0: Disable ADC0 Conversion Interrupt. 1: Enable interrupt requests generated by the ADC1 Conversion Interrupt. Bit6: CP2IE: Enable Comparator (CP2) Interrupt. This bit sets the masking of the CP2 interrupt. 0: Disable CP2 interrupts. 1: Enable interrupt requests generated by the CP2IF flag. Bit6: CP1IE: Enable Comparator (CP1) Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 interrupts. 1: Enable interrupt requests generated by the CP1IF flag. Bit6: CP0IE: Enable Comparator (CP0) Interrupt. This bit sets the masking of the CP0 interrupt. 0: Disable CP0 interrupts. 1: Enable interrupt requests generated by the CP0IF flag. Bit3: EPCA0: Enable Programmable Counter Array (PCA0) Interrupt. This bit sets the masking of the PCA0 interrupts. 0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0. Bit2: EWADC0: Enable Window Comparison ADC0 Interrupt. This bit sets the masking of ADC0 Window Comparison interrupt. 0: Disable ADC0 Window Comparison Interrupt. 1: Enable Interrupt requests generated by ADC0 Window Comparisons. Bit1: ESMB0: Enable System Management Bus (SMBus0) Interrupt. This bit sets the masking of the SMBus interrupt. 0: Disable all SMBus interrupts. 1: Enable interrupt requests generated by the SI flag. Bit0: ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt. This bit sets the masking of SPI0 interrupt. 0: Disable all SPI0 interrupts. 1: Enable Interrupt requests generated by the SPI0 flag. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EADC0 CP2IE CP1IE CP0IE EPCA0 EWADC0 ESMB0 ESPI0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xE6 All Pages

Rev. 1.2 157 Figure 13.22. EIE2: Extended Interrupt Enable 2 Bit7: EDMA0: Enable DMA0 Interrupt. This bit sets the masking of the DMA0 Interrupt. 0: Disable DMA0 interrupt. 1: Enable DMA0 interrupt. Bit6: ES1: Enable UART1 Interrupt. This bit sets the masking of the UART1 Interrupt. 0: Disable UART1 interrupt. 1: Enable UART1 interrupt. Bit5: ECAN0: Enable CAN Controller Interrupt. This bit sets the masking of the CAN Controller Interrupt. 0: Disable CAN Controller Interrupt. 1: Enable interrupt requests generated by the CAN Controller. Bit4: EADC2: Enable ADC2 E nd Of Conversion Interrupt. This bit sets the masking of the ADC2 End of Conversion interrupt. 0: Disable ADC2 End of Conversion interrupt. 1: Enable interrupt requests generated by the ADC2 End of Conversion Interrupt. Bit3: EWADC2: Enable Window Comparison ADC1 Interrupt. This bit sets the masking of ADC2 Window Comparison interrupt. 0: Disable ADC2 Window Comparison Interrupt. 1: Enable Interrupt requests generated by ADC2 Window Comparisons. Bit2: ET4: Enable Timer 4 Interrupt This bit sets the masking of the Timer 4 interrupt. 0: Disable Timer 4 interrupt. 1: Enable interrupt requests generated by the TF4 flag. Bit1: EADC1: Enable ADC1 End of Conversion Interrupt. This bit sets the masking of the ADC1 End of Conversion Interrupt. 0: Disable ADC1 Conversion Interrupt. 1: Enable interrupt requests generated by the ADC1 Conversion Interrupt. Bit0: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable all Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3 flag. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EDMA0 ES1 ECAN0 EADC2 EWADC2 ET4 EADC1 ET3 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xE7 All Pages

158 Rev. 1.2 Figure 13.23. EIP1: Extended Interrupt Priority 1 Bit7: PADC0: ADC End of Conversion Interrupt Priority Control. This bit sets the priority of the ADC0 End of Conversion Interrupt. 0: ADC0 End of Conversion interrupt set to low priority level. 1: ADC0 End of Conversion interrupt set to high priority level. Bit6: PCP2: Comparator2 (CP2) Interrupt Priority Control. This bit sets the priority of the CP2 interrupt. 0: CP2 interrupt set to low priority level. 1: CP2 interrupt set to high priority level. Bit5: PCP1: Comparator1 (CP1) Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 interrupt set to low priority level. 1: CP1 interrupt set to high priority level. Bit4: PCP0: Comparator0 (CP0) Interrupt Priority Control. This bit sets the priority of the CP0 interrupt. 0: CP0 interrupt set to low priority level. 1: CP0 interrupt set to high priority level. Bit3: PPCA0: Programmable Counter Arra y (PCA0) Interrupt Priority Control. This bit sets the priority of the PCA0 interrupt. 0: PCA0 interrupt set to low priority level. 1: PCA0 interrupt set to high priority level. Bit2: PWADC0: ADC0 Window Comparator Interrupt Priority Control. This bit sets the priority of the ADC0 Window interrupt. 0: ADC0 Window interrupt set to low priority level. 1: ADC0 Window interrupt set to high priority level. Bit1: PSMB0: System Management Bus (S MBus0) Interrupt Priority Control. This bit sets the priority of the SMBus0 interrupt. 0: SMBus interrupt set to low priority level. 1: SMBus interrupt set to high priority level. Bit0: PSPI0: Serial Periph eral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PADC0 PCP2 PCP1 PCP0 PPCA0 PWADC0 PSMB0 PSPI0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xF6 All Pages

Rev. 1.2 159 Figure 13.24. EIP2: Extended Interrupt Priority 2 Bit7: PDMA0: DMA0 Interr upt Priority Control. This bit sets the priority of the DMA0 interrupt. 0: DMA0 interrupt set to low priority. 1: DMA0 interrupt set to high priority. Bit6: PS1: UART1 Interrupt Priority Control. This bit sets the priority of the UART1 interrupt. 0: UART1 interrupt set to low priority. 1: UART1 interrupt set to high priority. Bit5: PCAN0: CAN Interrup t Priority Control. This bit sets the priority of the CAN Interrupt. 0: CAN Interrupt set to low priority level. 1: CAN Interrupt set to high priority level. Bit4: PADC2: ADC2 End Of Conversion Interrupt Priority Control. This bit sets the priority of the ADC2 End of Conversion interrupt. 0: ADC2 End of Conversion interrupt set to low priority. 1: ADC2 End of Conversion interrupt set to high priority. Bit3: PWADC2: ADC2 Window Comparator Interrupt Priority Control. 0: ADC2 Window interrupt set to low priority. 1: ADC2 Window interrupt set to high priority. Bit2: PT4: Timer 4 Interrupt Priority Control. This bit sets the priority of the Timer 4 interrupt. 0: Timer 4 interrupt set to low priority. 1: Timer 4 interrupt set to high priority. Bit1: PADC1: ADC End of Conversion Interrupt Priority Control. This bit sets the priority of the ADC1 End of Conversion Interrupt. 0: ADC1 End of Conversion interrupt set to low priority level. 1: ADC1 End of Conversion interrupt set to high priority level. Bit0: PT3: Timer 3 Interr upt Priority Control. This bit sets the priority of the Timer 3 interrupts. 0: Timer 3 interrupt set to low priority level. 1: Timer 3 interrupt set to high priority level. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PDMA0 PS1 PCAN0 PADC2 PWADC2 PT4 PADC1 PT3 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xF7 All Pages

160 Rev. 1.2 13.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped. Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes the least power. Figure 13.25 describes the Power Contro l Register (PCON) used to control the CIP-51's power management modes. Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management of the entire MCU is better accomplished by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and put into low power mode. Digital peripherals, such as timers or serial buses, draw littl e power whenever they are not in use. Turning off the oscillator saves even more power, but requires a reset to restart the MCU. 13.4.1. Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes. All internal register s and memory maintain their original data. All analog and digital peripherals can remain active during Idle mode. Idle mode is terminated when an enabled interrupt or /RST is asserted. The assertion of an enabled inter- rupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt will be serviced and the next instru ction to be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins pro- gram execution at address 0x0000. If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT ma y be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the oppor- tunity for additional power savings, allowing the system to remain in the Idle mo de indefinitely, waiting for an external stimulus to wake up the system. Refer to Section 14.7 for more information on the use and configuration of the WDT. Note: Any instruction which sets the IDLE bit should be immediately followed by an instruction which has two or more opcode bytes.For example: // in ‘C’: PCON |= 0x01; // Set IDLE bit PCON = PCON; // ... Followed by a 3-cycle Dummy Instruction ; in assembly: ORL PCON, #01h ; Set IDLE bit MOV PCON, PCON ; ... Followed by a 3-cycle Dummy Instruction If the instruction following the write to the IDLE bit is a single-byte instruction and an interrupt occurs during the execution of the instruction of the instruction which sets the IDLE bit, the CPU may not wake from IDLE mode when a future interrupt occurs.

Rev. 1.2 161 13.4.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CI P-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes. In Stop mode, the CPU and internal oscillators are stopped, effectively shutting down all digital peripherals. Each analog peri pheral must be shut down individually prior to enter- ing Stop Mode. Stop mode can only be terminated by an internal or external rese t. On reset, the CIP-51 performs the normal reset sequence and begins program execution at address 0x0000. If enabled, the Missing Clock Detect or will cause an internal reset and ther eby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of 100 µs. Figure 13.25. PCON: Power Control Bits7-2: Reserved. Bit1: STOP: STOP Mode Select. Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’. 1: CIP-51 forced into power-down mode. (Turns off internal oscillator). Bit0: IDLE: IDLE Mode Select. Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’. 1: CIP-51 forced into IDLE mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, and all peripherals remain active.) See Note in Section “13.4.1. Idle Mode” on page160. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - - STOP IDLE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0x87 All Pages

162 Rev. 1.2

Rev. 1.2 163 14. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:

• CIP-51 halts program execution
• Special Function Registers (SFRs) are initialized to their defined reset values
• External port pins are forced to a known configuration
• Interrupts and timers are disabled. All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data memory are unaffected during a reset; any prev iously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost even though the data on the stack are not altered. The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pull-ups which take the exter- nal I/O pins to a high state. The external I/O pins do not go high immediately, but will go high within four system clock cycles after entering the reset state. This allows power to be conserved while the part is held in reset. For VDD Monitor resets, the /RST pin is driven low until the end of the VDD reset timeout. On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter- nal oscillator running at its lowest frequency. Refer to Section “15. Oscillators” on page171 for information on selecting and configuring the system clock source . The Watchdog Timer is enabled using its longest timeout interval (see Section “14.7. Watchdog Timer Reset” on page 165). Once the system clock source is stable, program execution begins at location 0x0000. There are seven sources for putting the MCU into the reset state: power-on, power-fail, external /RST pin, external CNVSTR2 signal, softwa re command, Comparator0, Missing Clock Detector, and Watchdog Timer. Each reset source is described in the following sections. WDT XTAL1 XTAL2 OSC Internal Clock Generator System Clock CIP-51 Microcontroller Core Missing Clock Detector (one- shot) WDT Strobe Software Reset Extended Interrupt Handler Clock Select /RST+ VDD Supply Reset Timeout (wired-OR) System Reset Supply Monitor PRE Reset Funnel CP0+ Comparator0 CP0- (Port I/O) Crossbar CNVSTR2 (CNVSTR reset enable) (CP0 reset enable) EN WDT Enable ENMCD Enable (wired-OR) VDD Monitor reset enable Figure 14.1. Reset Sources

Rev. 1.2 165 reset until at least 12 clock cycles after the acti ve-low /RST signal is removed. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. 14.4. Missing Clock Detector Reset The Missing Clock Detector is essentia lly a one-shot circuit that is trig gered by the MCU system clock. If the system clock goes away for more than 100 µs, the one-shot will time out and generate a reset. After a Missing Clock Detector re set, the MCDRSF flag (RSTSRC.2) will be set, signifying the MSD as the reset source; otherwise, this bit reads ‘0’. The state of t he /RST pin is unaffected by this reset. Setting the MCDRSF bit, RSTSRC.2 (see Section “15. Oscillators” on page171) enables the Missing Clock Detector. 14.5. Comparator0 Reset Comparator0 can be configured as a reset input by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled using CPT0CN.7 (see Section “ 12. Comparators” on page 117) prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-invertin g input voltage (CP0+ pin) is less than the inverting input voltage (CP0- pin), the MCU is put into the rese t state. After a Comparator0 Reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by this reset. 14.6. External CNVSTR2 Pin Reset The external CNVSTR2 signal can be configured as a reset input by writing a ‘1’ to the CNVRSEF flag (RSTSRC.6). The CNVSTR2 signal can appear on any of the P0, P1, P2 or P3 I/O pins as described in Section “18.1. Ports 0 through 3 and the Priority Crossbar Decoder ” on page 205. Note that the Crossbar must be configured for the CNVSTR2 signal to be routed to the appropriate Port I/O. The Crossbar should be configured and enabled before the CNVRSEF is set. CNVSTR2 cannot be used to start ADC2 conver- sions when it is configured as a reset source. When configured as a reset, CNVSTR2 is active-low and level sensitive. After a CNVSTR2 reset, the CNVRSEF flag (RSTSRC.6) will read ‘1’ signifying CNVSTR2 as the reset source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by this reset. 14.7. Watchdog Timer Reset The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. A WDT overflow will force the MCU into the reset state. To prevent the reset, the WDT must be restarted by application soft- ware before overflow. If the system experiences a soft ware or hardware malfuncti on preventing the soft- ware from restarting the WDT, the WDT will overfl ow and cause a reset. This should prevent the system from running out of control. Following a reset the WDT is automatically enabled and running with the default maximum time interval. If desired the WDT can be disabled by system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset. The state of the /RST pin is unaffected by this reset. The WDT consists of a 21-bit timer running from th e programmed system clock. The timer measures the period between specific writes to its control register. If this period exceeds the programmed limit, a WDT reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently enabled if desired. Watchdog features are contro lled via the Watchdog Timer Control Register (WDTCN) shown in Figure 14.3.

166 Rev. 1.2 14.7.1. Enable/Reset WDT The watchdog timer is both enabled and reset by writ ing 0xA5 to the WDTCN register. The user's applica- tion software should include periodic writes of 0x A5 to WDTCN as needed to prevent a watchdog timer overflow. The WDT is enabled and reset as a result of any system reset. 14.7.2. Disable WDT Writing 0xDE followed by 0xAD to the WDTCN regi ster disables the WDT. The following code segment illustrates disabling the WDT: CLR EA ; disable all interrupts MOV WDTCN,#0DEh ; disable software watchdog timer MOV WDTCN,#0ADh SETB EA ; re-enable interrupts The writes of 0xDE and 0xAD must occur within 4 clo ck cycles of each other, or the disable operation is ignored. Interrupts should be disabled during this procedure to avoid delay between the two writes. 14.7.3. Disable WDT Lockout Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always intending to use the watchdog should write 0xFF to WDTCN in the initialization code. 14.7.4. Setting WDT Interval WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation: ; where Tsysclk is the system clock period. 43 WDTCN 20–[]+ Tsysclk×

Rev. 1.2 167 For a 3 MHz system clock, this provides an interval range of 0.021 ms to 349.5 ms. WDTCN.7 must be logic 0 when setting this interval . Reading WDTCN returns the progra mmed interval. WDTCN.[2:0] reads 111b after a system reset. Bits7-0: WDT Control. Writing 0xA5 both enables and reloads the WDT. Writing 0xDE followed within 4 system clocks by 0xAD disables the WDT. Writing 0xFF locks out the disable feature. Bit4: Watchdog Status Bit (when Read). Reading the WDTCN.[4] bit indicates the Watchdog Timer Status. 0: WDT is inactive. 1: WDT is active. Bits2-0: Watchdog Timeout Interval Bits. The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits, WDTCN.7 must be set to 0. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value xxxxx111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xFF All Pages Figure 14.3. WDTCN: Watchdog Timer Control Register

168 Rev. 1.2 Figure 14.4. RSTSRC: Reset Source Register Bit7: Reserved. Bit6: CNVRSEF: Convert Start Reset Source Enable and Flag Write: 0: CNVSTR2 is not a reset source. 1: CNVSTR2 is a reset source (active low). Read: 0: Source of prior reset was not CNVSTR2. 1: Source of prior reset was CNVSTR2. Bit5: C0RSEF: Comparator0 Reset Enable and Flag. Write: 0: Comparator0 is not a reset source. 1: Comparator0 is a reset source (active low). Read: 0: Source of last reset was not Comparator0. 1: Source of last reset was Comparator0. Bit4: SWRSF: Software Reset Force and Flag. Write: 0: No effect. 1: Forces an internal reset. /RST pin is not effected. Read: 0: Source of last reset was not a write to the SWRSF bit. 1: Source of last reset was a write to the SWRSF bit. Bit3: WDTRSF: Watchdog Timer Reset Flag. 0: Source of last reset was not WDT timeout. 1: Source of last reset was WDT timeout. Bit2: MCDRSF: Missing Clock Detector Flag. Write: 0: Missing Clock Detector disabled. 1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected. Read: 0: Source of last reset was not a Missing Clock Detector timeout. 1: Source of last reset was a Missing Clock Detector timeout. Bit1: PORSF: Power-On Reset Flag. Write: If the VDD monitor circuitry is enabled (b y tying the MONEN pin to a logic high state), this bit can be written to select or de-select the VDD monitor as a reset source. 0: De-select the VDD monitor as a reset source. 1: Select the VDD monitor as a reset source. Important: At power-on, the VDD monitor is enabled/disabled using the external VDD monitor enable pin (MONEN). The PORSF bit does not disable or enable the VDD monitor circuit. It simply selects the VDD monitor as a reset source. Read: This bit is set whenever a power-on reset occurs. This may be due to a true power-on reset or a VDD monitor reset. In either case, data memory should be considered indeterminate following the reset. 0: Source of last reset was not a power-on or VDD monitor reset. 1: Source of last reset was a power-on or VDD monitor reset. Note: When this flag is read as '1', all other reset flags are indeterminate. Bit0: PINRSF: HW Pin Reset Flag. Write: 0: No effect. 1: Forces a Power-On Reset. /RST is driven low. Read: 0: Source of prior reset was not /RST pin. 1: Source of prior reset was /RST pin. R R/W R/W R/W R R/W R/W R/W Reset Value - CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF PORSF PINRSF 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xEF

Rev. 1.2 169 Table 14.1. Reset Electrical Characteristics -40 to +85 °C unless otherwise specified. Parameter Conditions Min Typ Max Units /RST Output Low Voltage IOL = 8.5 mA, VDD = 2.7 V to 3.6 V 0.6 V /RST Input High Voltage 0.7 x VDD V /RST Input Low Voltage 0.3 x VDD /RST Input Leakage Current /RST = 0.0 V 50 µA VDD for /RST Output Valid 1.0 V AV+ for /RST Output Valid 1.0 V VDD POR Threshold (V RST) 2.40 2.55 2.70 V Minimum /RST Low Time to Generate a System Reset 10 ns Reset Time Delay /RST rising edge after VDD crosses VRST threshold 80 100 120 ms Missing Clock Detector Time- out Time from last system clock to reset initiation 100 220 500 µs

170 Rev. 1.2

Rev. 1.2 171 15. Oscillators C8051F060/1/2/3/4/5/6/7 de vices include a programmabl e internal oscillator and an external oscillator drive circuit. The intern al oscillator can be enabled, disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 15.1. The system clock can be sourced by the external oscillator cir- cuit, the internal oscillator, or a scaled version of the internal oscilla tor. The internal oscillator's electrical specifications are given in Table 15.1. 15.1. Programmable Internal Oscillator All C8051F060/1/2/3/4/5/6/7 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator pe riod can be adjusted via the OSCICL register as defined by Figure 15.2. OSCICL is factory calibrated to obtain a 24.5 MHz base frequency (fBASE). Electrical specifications for the precision internal oscillator are given in Table 15.1. The programmed inter- nal oscillator frequency must not exceed 25 MHz. Note that the system clock may be derived from the pro- grammed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. Figure 15.1. Oscillator Diagram OSC Programmable Internal Clock Generator Input Circuit EN SYSCLK n OSCICL OSCICN IOSCEN IFRDY IFCN1 IFCN0 XTAL1 XTAL2 Option 2 VDD XTAL1 Option 1 Option 4 XTAL1 OSCXCN XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 CLKSEL CLKSL Option 3 XTAL1 XTAL2

174 Rev. 1.2 Figure 15.5. OSCXCN: External Oscillator Control Register Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Valid only when XOSCMD = 11x.). 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. Bits6-4: XOSCMD2-0: Extern al Oscillator Mode Bits. 00x: External Oscillator circuit off. 010: External CMOS Clock Mode (External CMOS Clock input on XTAL1 pin). 011: External CMOS Clock Mode with divide by 2 stage (External CMOS Clock input on XTAL1 pin). 10x: RC/C Oscillator Mode with divide by 2 stage. 110: Crystal Oscillator Mode. 111: Crystal Oscillator Mode with divide by 2 stage. Bit3: Unused. Read = 0, Write = don't care. Bits2-0: XFCN2-0: External Osc illator Frequency Control Bits. 000-111: see table below: CRYSTAL MODE (Circuit from Figure 15.1, Option 1; XOSCMD = 11x). Choose XFCN value to match crystal frequency. RC MODE (Circuit from Figure 15.1, Option 2; XOSCMD = 10x). Choose XFCN value to match frequency range: f = 1.23(10 3) / (R * C), where f = frequency of oscillation in MHz C = capacitor value in pF R = Pull-up resistor value in kΩ C MODE (Circuit from Figure 15.1, Option 3; XOSCMD = 10x). Choose K Factor (KF) for the oscillation frequency desired: f = KF / (C * VDD), where f = frequency of oscillation in MHz C = capacitor value on XTAL1, XTAL2 pins in pF VDD = Power Supply on MCU in volts R R/W R/W R/W R R/W R/W R/W Reset Value XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 - XFCN2 XFCN1 XFCN0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0x8C F XFCN Crystal (XOSCMD = 11x) RC (XOSCMD = 10x) C (XOSCMD = 10x) 000 f ≤ 32 kHz f ≤ 25 kHz K Factor = 0.87 001 32 kHz < f ≤ 84 kHz 25 kHz < f ≤ 50 kHz K Factor = 2.6 010 84 kHz < f ≤ 225 kHz 50 kHz < f ≤ 100 kHz K Factor = 7.7 011 225 kHz < f ≤ 5 9 0k H z 1 0 0k H z < f ≤ 200 kHz K Factor = 22 100 590 kHz < f ≤ 1.5 MHz 200 kHz < f ≤ 400 kHz K Factor = 65 101 1.5 MHz < f ≤ 4M H z 4 0 0k H z < f ≤ 800 kHz K Factor = 180 110 4 MHz < f ≤ 10 MHz 800 kHz < f ≤ 1.6 MHz K Factor = 664 111 10 MHz < f ≤ 30 MHz 1.6 MHz < f ≤ 3.2 MHz K Factor = 1590

Rev. 1.2 175 15.4. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 15.1, Option 1. The External Oscillato r Frequency Cont rol value (XFCN) should be chosen from the Crystal column of the table in Figure 15.5 (OSCXCN register). For example, an 11.0592 MHz crystal requires an XFCN setting of 111b. When the crystal oscillator is enabl ed, the oscillator amplit ude detection circuit requires a settle time to achieve proper bias. Introducing a bl anking interval of at least 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the external oscillato r before the crystal oscillator has st abilized can result in unpredictable behavior. The recommended procedure is: Step 1. Enable the external oscillator. Step 2. Wait at least1 ms. Step 3. Poll for XTLVLD => ‘1’. Step 4. Switch the system clo ck to the external oscillator. Important Note on External Crystals: Crystal oscillator circuits are qu ite sensitive to PCB layout and external noise. The crystal should be placed as clos e as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. Crystal loading capacitors should be referenced to AGND. 15.5. External RC Example If an RC network is used as an external oscillator so urce for the MCU, the circ uit should be configured as shown in Figure 15.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter- mine the required External Oscilla tor Frequency Control va lue (XFCN) in the OSCXCN Register, first select the RC network value to pr oduce the desired frequency of osc illation. If the frequency desired is 100 kHz, let R = 246 kΩ and C = 50 pF: f = 1.23( 10 3 ) / RC = 1.23 ( 103 )/[2 4 6*5 0] = 0 . 1M H z = 1 0 0k H z Referring to the table in Figure 15.5, the required XFCN setting is 010. 15.6. External Capacitor Example If a capacitor is used as an external oscillator for t he MCU, the circuit should be configured as shown in Figure 15.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasiti c capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in th e OSCXCN Register, select the capaci- tor to be used and find the frequency of oscillation from the equations below. Assume VDD = 3.0 V and C = 50 pF: f = KF / 150 If a frequency of roughly 50 kHz is desired, select the K Factor from the table in Figure 15.5 as KF = 7.7: f = 7.7 / 150 = 0.051 MHz, or 51 kHz Therefore, the XFCN value to use in this example is 010.

176 Rev. 1.2

Rev. 1.2 177 16. Flash Memory The C8051F060/1/2/3/4/5/6/7 devices include on-chip, reprogrammable Flash memory for program code and non-volatile data storage. The C8051F060/1/2/3/4/5 include 64 k + 128 bytes of Flash, and the C8051F066/7 include 32 k + 128 bytes of Flash. The Flash memory can be programmed in-system, a sin- gle byte at a time, through the JTAG interface or by software using the MO VX write instructions. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. The bytes would typically be erased (set to 0xFF) before being reprogrammed. Flash wr ite and erase operations are automatically timed by hardware for proper execution; da ta polling to determine the end of the write/erase op eration is not required. The CPU is stalled during write/erase opera tions while the device peripherals remain active. Interrupts that occur during Flash write/erase operati ons are held, and are then serviced in their priority order once the Flash operation has completed. Refer to Table 16.1 for the electrical characteristics of the Flash memory. 16.1. Programming The Flash Memory The simplest means of programming the Flash memory is through the JTAG interface using programming tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial- ized device. For details on the JTAG co mmands to program Flash memory, see Section “26. JTAG (IEEE 1149.1)” on page 317. The Flash memory can be programmed from software using the MOVX write instruction with the address and data byte to be programmed provided as norma l operands. Before writing to Flash memory using MOVX, Flash write operations must be enabled by setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1. This direct s the MOVX writes to Flash memory instead of to XRAM, which is the default target. The PSWE bit remains set until cleared by software. To avoid errant Flash writes, it is rec- ommended that interrupts be disabled while the PSWE bit is logic 1. Flash memory is read using the MOVC instruction. MOVX reads are always directed to XRAM, regardless of the state of PSWE. NOTE: To ensure the integrity of Flash memory contents, it is strongly recommended that the on- chip VDD monitor be enabled by connecting the VDD monitor enable pin (MONEN) to VDD and set- ting the PORSF bit in the RSTSRC register to ‘1’ in any system that writes and/or erases Flash memory from software. See “Reset Sources” on page 163 for more information. A write to Flash memory can clear bits but cannot set them; only an erase operation can set bits in Flash. A byte location to be programmed must be erased before a new value can be written . The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). The following steps illustrate the algorithm for programming Flash from user software. Step 1. Disable interrupts. Step 2. Set FLWE (FLSCL.0) to enable Fl ash writes/erases via user software. Step 3. Set PSEE (PSCTL.1) to enable Flash erases. Step 4. Set PSWE (PSCTL.0 ) to redirect MOVX commands to write to Flash. Step 5. Use the MOVX command to write a data byte to any location within the 512-byte page to be erased. Step 6. Clear PSEE to disable Flash erases Step 7. Use the MOVX command to write a data by te to the desired byte location within the erased 512-byte page. Repeat this step until all desired bytes are written (within the target page).

178 Rev. 1.2 Step 8. Clear the PSWE bit to redirect MOVX write commands to the XRAM data space. Step 9. Re-enable interrupts. Write/Erase timing is automatically controlled by hardware. Note that code execution in the 8051 is stalled while the Flash is being programmed or erased. 16.2. Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX write instruction (as described in the previous section) and read using the MOVC instruction. An additional 128-byte sector of Flash memory is incl uded for non-volatile data storage. Its smaller sector size makes it particularly well suited as general purpose, non-volatile scratchpad memory. Even though Flash memory can be written a single byte at a time , an entire sector must be erased first. In order to change a single byte of a multi-byte data set, the data must be moved to temporary storage. The 128-byte sector size facilitates updating data without wasting program memory or RAM space. The 128-byte sector is double-mapped over the normal Flash memory ar ea; its address ranges from 0x00 to 0x7F (see Figure 16.1 and Figure 16.2). To access this 128-byte sector, the SFLE bit in PSCTL must be set to logic 1. Code execution from this 128-byte scratchpad sector is not supported. Table 16.1. Flash Electrical Characteristics Parameter Conditions Min Typ Max Units Flash Size * C8051F060/1/2/3/4/5 65664 † Bytes Flash Size * C8051F066/7 32896 Bytes Endurance 20 k 100 k Erase/Write Erase Cycle Time 10 12 14 ms Write Cycle Time 40 50 60 µs * Includes 128-byte Scratch Pad Area † 1024 Bytes at location 0xFC00 to 0xFFFF are reserved.

Rev. 1.2 179 16.3. Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft- ware as well as prevent the viewing of proprietary program code and constants. The Program Store Write Enable (PSCTL.0) and the Program Store Erase Enable (PSCTL.1) bits protect the Flash memory from accidental modification by software. These bits must be explicitly set to logic 1 before software can write or erase the Flash memory. Additional security features prevent proprietary program code and data constants from being read or altered across the JTAG interface or by software running on the system controller. A set of security lock bytes protect the Flash program memory from being read or altered across the JTAG interface. Each bit in a security lock-byte protects one 8k-byte block of memory. Clearing a bit to logic 0 in a Read Lock Byte prevents the corresponding block of Flash memory from being read across the JTAG interface. Clearing a bit in the Write/Erase Lock Byte protects the block from JTAG erasures and/or writes. The Scratchpad area is read or write/ erase locked when all bits in t he corresponding security byte are cleared to logic 0. On the C8051F060/1/2/3/4/5, the security lock bytes are located at 0xFBFE (Write/Erase Lock) and 0xFBFF (Read Lock), as shown in Figure 16.1. On the C8051F066/7, the security lock bytes are located at 0x7FFE (Write/Erase Lock) and 0x7FFF (Read Lock), as shown in Figure 16.2. The 512-byte sector con- taining the lock bytes can be written to, but not erased, by software. An attempted read of a read-locked byte returns undefined data. Debugging code in a read-locked sector is not possible through the JTAG interface. The lock bits can always be read from and written to logic 0 regardle ss of the security setting applied to the block containing the security bytes. Th is allows additional blocks to be protected after the block containing the security bytes has been locked. Important Note: To ensure protection from external access, the block containing the lock bytes must be Write/Erase locked. On the 64 k byte devices (C8051F060/1/2/3/4/5), the page containing the security bytes is 0xFA00-0xFBFF, and is lock ed by clearing bit 7 of the Write/Erase Lock Byte. On the 32 k byte devices (C8051F066/7), the page containing the security bytes is 0x7E00-0x7FFF, and is locked by clearing bit 3 of the Write/Erase Lock Byte. If the page containing the security bytes is not Write/Erase locked, it is still possible to erase this page of Flash memory through the JTAG port and reset the security bytes. When the page containing the security bytes has been Write/Erase locked, a JTAG full device erase must be performed to unlock any areas of Flash protected by the security bytes. A JTAG full device erase is initiated by performing a normal JTAG erase operation on either of the security byte locations. This operation must be initiated through the JTAG port, and cannot be performed from firmware running on the device.

182 Rev. 1.2 ing at 0x0000 up to (but excluding) the FAL address. Software in the upper partition can execute code in the lower partition, but is prohibited from reading locations in th e lower partition using the MOVC instruc- tion. (Executing a MOVC instruction from the upper pa rtition with a source address in the lower partition will always return a data value of 0x00.) Software running in the lower partition can access locations in both the upper and lower partition without restriction. The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value- added firmware via the reset vector. Once the value- added firmware completes its initial execution, it branches to a predetermined location in the upper partition. If entry points are published, software running in the upper partition may execute program code in the lower partition, but it ca nnot read the contents of the lower partition. Parameters may be passed to the program code running in the lower partition either through the typical method of placing them on the stack or in registers before the call or by placing them in prescribed memory locations in the upper partition. The FAL address is specified using the contents of the Flash Access Limit Register. The 16-bit FAL address is calculated as 0xNN00, where NN is the co ntents of the FAL Security Register. Thus, the FAL can be located on 256-byte boundaries anywhere in program memory space. However, the 512-byte erase sector size essentially requires that a 512 boundary be used. The contents of a non-initialized FAL security byte is 0x00, thereby setting the FAL address to 0x0 000 and allowing read access to all locations in pro- gram memory space by default. Bits 7-0: FLACL: Flash Access Limit. This register holds the high byte of the 16-bit program memory read/write/erase limit address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is replaced by contents of FLACL. A write to this register sets the Flash Access Limit. This register can only be written once after any reset. Any subsequent writes are ignored until the next reset. To fully protect all addresses below this limit, bit 0 of FLACL should be set to ‘0’ to align the FAL on a 512-byte Flash page boundary. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Address: SFR Page: 0xB7 F Figure 16.3. FLACL: Flash Access Limit

Rev. 1.2 183 16.3.1. Summary of Flash Security Options There are three Flash access methods supported on the C8051F060/1/2/3/4/5/ 6/7; 1) Accessing Flash through the JTAG debug interface, 2) Accessing Fl ash from firmware residing below the Flash Access Limit, and 3) Accessing Flash from firmware residing at or above the Flash Access Limit. Accessing Flash through the JTAG debug interface: 1. The Read and Write/Erase Lock bytes (securit y bytes) provide secu rity for Flash access through the JTAG interface. 2. Any unlocked page may be read from, written to, or erased. 3. Locked pages cannot be read from, written to, or erased. 4. Reading the security bytes is always permitted. 5. Locking additional pages by writing to the security bytes is always permitted. 6. If the page containing the security bytes is unlocked, it can be directly erased. Doing so will reset the security bytes and unlock all pages of Flash. 7. If the page containing the security bytes is locked, it cannot be directly erased. To unlock the page containing the security bytes, a full JTAG device erase is required. A full JTAG device erase will erase all Flash pages, includi ng the page containing the security bytes and the security bytes themselves. 8. The Reserved Area cannot be read from, written to, or erased at any time. Accessing Flash from firmware residing below the Flash Access Limit: 1. The Read and Write/Erase Lock bytes (security bytes) do not restrict Flash access from user firmware. 2. Any page of Flash except the page containing the security bytes may be read from, written to, or erased. 3. The page containing the security bytes cannot be erased. Unlocking pages of Flash can only be performed via the JTAG interface. 4. The page containing the security bytes may be read from or written to. Pages of Flash can be locked from JTAG access by writing to the security bytes. 5. The Reserved Area cannot be read from, written to, or erased at any time. Accessing Flash from firmware residing at or above the Flash Access Limit: 1. The Read and Write/Erase Lock bytes (security bytes) do not restrict Flash access from user firmware. 2. Any page of Flash at or above the Flash Access Limit except the page containing the security bytes may be read from, written to, or erased. 3. Any page of Flash below the Flash Access Limit cannot be read from, written to, or erased. 4. Code branches to locations below the Flash Access Limit are permitted. 5. The page containing the security bytes cannot be erased. Unlocking pages of Flash can only be performed via the JTAG interface. 6. The page containing the security bytes may be read from or written to. Pages of Flash can be locked from JTAG access by writing to the security bytes. 7. The Reserved Area cannot be read from, written to, or erased at any time.

184 Rev. 1.2 Figure 16.4. FLSCL: Flash Memory Control Bit 7: FOSE: Flash On e-Shot Timer Enable This is the timer that turns off the sense amps after a Flash read. 0: Flash One-Shot Timer disabled. 1: Flash One-Shot Timer enabled (recommended setting.) Bit 6: FRAE: Flash Read Always Enable 0: Flash reads occur as necessary (recommended setting.). 1: Flash reads occur every system clock cycle. Bits 5-1: RESERVED. Read = 00000b. Must Write 00000b. Bit 0: FLWE: Flash Write/Erase Enable This bit must be set to allow Flash writes/erases from user software. 0: Flash writes/erases disabled. 1: Flash writes/erases enabled. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value FOSE FRAE Reserved Reserved Reserved Reserved Reserved FLWE 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Address: SFR Page: 0xB7

Rev. 1.2 185 Figure 16.5. PSCTL: Program Store Read/Write Control Bits 7-3: UNUSED. Read = 00000b, Write = don't care. Bit 2: SFLE: Scratchpad Flash Memory Access Enable When this bit is set, Flash MOVC reads and writes from user software are directed to the 128-byte Scratchpad Flash sector. When SFLE is set to logic 1, Flash accesses out of the address range 0x00-0x7F should not be attempted. Reads/Writes out of this range will yield undefined results. 0: Flash access from user software directed to the Program/Data Flash sector. 1: Flash access from user software directed to the Scratchpad sector. Bit 1: PSEE: Program Store Erase Enable. Setting this bit allows an entire page of the Flash program memory to be erased provided the PSWE bit is also set. After setting this bit, a write to Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter. Note: The Flash page con- taining the Read Lock Byte and Write/Erase Lock Byte cannot be erased by software. 0: Flash program memory erasure disabled. 1: Flash program memory erasure enabled. Bit 0: PSWE: Program Store Write Enable. Setting this bit allows writing a byte of data to the Flash program memory using the MOVX write instruction. The location must be erased prior to writing data. 0: Write to Flash program memory disabled. MOVX write operations target External RAM. 1: Write to Flash program memory enabled. MOVX write operations target Flash memory. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - SFLE PSEE PSWE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Address: SFR Page: 0x8F

186 Rev. 1.2

Rev. 1.2 187 17. External Data Memory Interface and On-Chip XRAM The C8051F060/1/2/3/4/5/6/7 MCUs include 4 k bytes of on-chip RAM mapped into the external data memory space (XRAM). In addition, the C8051F060/2/4/6 include an External Data Memory Interface which can be used to access off-chip memories and memory-mapped devices connected to the GPIO ports. The external memory space may be accessed us ing the external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing mode using R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Regist er (EMI0CN, shown in Figure 17.1). Note: the MOVX instruction can also be used for writing to the Flash memory. See Section “16. Flash Memory” on page 177 for details. The MOVX instruction accesses XRAM by default. 17.1. Accessing XRAM The XRAM memory space (both internal and extern al) is accessed using the MOVX instruction. The MOVX instruction has two forms, both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit register which contai ns the effective address of the XRAM location to be read or written. The second method uses R0 or R1 in combination with the EM I0CN register to generate the effective XRAM address. Examples of both of these methods are given below. 17.1.1. 16-Bit MOVX Example The 16-bit form of the MOVX instructi on accesses the memory location pointed to by the contents of the DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the accumulator A: MOV DPTR, #1234h ; load DPTR with 16-bit address to read (0x1234) MOVX A, @DPTR ; load contents of 0x1234 into accumulator A The above example uses the 16-bit immediate MOV inst ruction to set the contents of DPTR. Alternately, the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and DPL, which contains the lower 8-bits of DPTR. 17.1.2. 8-Bit MOVX Example The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the effective address to be accessed. The following series of instructions read the contents of the byte at address 0x1234 into the accumulator A. MOV EMI0CN, #12h ; load high byte of address into EMI0CN MOV R0, #34h ; load low byte of address into R0 (or R1) MOVX a, @R0 ; load contents of 0x1234 into accumulator A

188 Rev. 1.2 17.2. Configuring the External Memory Interface Configuring the External Memory Interface consists of four steps: 1. Enable the EMIF on the High Ports (P7, P6, P5, and P4). 2. Configure the Output Modes of the port pins as either push-pull or open-drain (push-pull is most common). 3. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic ‘1’). 4. Select Multiplexed mode or Non-multiplexed mode. 5. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or off-chip only). 6. Set up timing to interface with off-chip memory or peripherals. Each of these four steps is explained in detail in the following sections. The Po rt enable bit, Multiplexed mode selection, and Mode bits are located in the EMI0CF register shown in Figure 17.2. 17.3. Port Selection and Configuration When enabled, the External Memory Interface appears on Ports 7, 6, 5, and 4 in non-multiplexed mode, or Ports 7, 6, and 4 in multiplexed mode. The External Memory Interface claims the associated Port pins for memory oper ations ONLY during the execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port pins reverts to the Port latches. See Section “18. Port Input/Output” on page 203 for more information about the Port operation and configuration. The Port latches should be explicitly configured to ‘park’ the External Memory Interface pins in a dormant state when not in use, most commonly by setting them to a logic 1. During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the driv- ers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the External Memory Interface operation, and rema ins controlled by the PnMDOUT registers. See Section “18. Port Input/Output” on page 203 for more information about Port output mode configuration.

Rev. 1.2 191 17.4.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Addr ess Bus pins are not shared. An example of a Non- page 196 for more information about Non-multiplexed operation. ADDRESS BUS E M I F A[15:0] (P5 and P6) 64K X 8 SRAM A[15:0] DATA BUSD[7:0] (P7) I/O[7:0] VDD /WR (P4.7) /RD (P4.6) OE WE CE (Optional) Figure 17.4. Non-multiplexed Configuration Example

192 Rev. 1.2 17.5. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 17.5, based on the EMIF Mode bits in the EMI0CF register (Figure 17.2). These modes are summarized below. More infor- mation about the different modes can be found in Section “17.6. Timing” on page 194. 17.5.1. Internal XRAM Only When EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will ta rget the internal XRAM space on the device. Memory accesses to addresses beyond the populated space will wrap on 4 k byte boundaries. As an example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip XRAM space.

• 8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address and R0 or R1 to determine the low-byte of the effective address.
• 16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address. 17.5.2. Split Mode without Bank Select When EMI0CF.[3:2] are set to ‘01’, the XRAM memory map is split into two areas, on-chip space and off- chip space.
• Effective addresses below the 4 kB bo undary will access on-chip XRAM space.
• Effective addresses beyond the 4 kB boundary will access off-chip space.
• 8-bit MOVX operations use the contents of EMI0 CN to determine whether the memory access is on- chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate the upper address bits at will by setting the Port state directly. This behavior is in contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus A[7:0] are driven, deter- mined by R0 or R1.
• 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on- chip or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction. EMI0CF[3:2] = 00 0xFFFF 0x0000 EMI0CF[3:2] = 11 0xFFFF 0x0000 EMI0CF[3:2] = 01 0xFFFF 0x0000 EMI0CF[3:2] = 10 On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM Off-Chip Memory (No Bank Select) On-Chip XRAM 0xFFFF 0x0000 Off-Chip Memory (Bank Select) On-Chip XRAM Off-Chip Memory Figure 17.5. EMIF Operating Modes

Rev. 1.2 193 17.5.3. Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off- chip space.

• Effective addresses below the 4 kB bo undary will access on-chip XRAM space.
• Effective addresses beyond the 4 kB boundary will access off-chip space.
• 8-bit MOVX operations use the contents of EMI0 CN to determine whether the memory access is on- chip or off-chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the lower 8-bits of the Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus A[15:0] are driven in “Bank Select” mode.
• 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on- chip or off-chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transac- tion. 17.5.4. External Only When EMI0CF[3:2] are set to ‘11’, all MOVX operations are directed to off-chip space. On-chip XRAM is not visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the 4 kB boundary.
• 8-bit MOVX operations ignore the contents of EMI0 CN. The upper Address bits A[15:8] are not driven (identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower 8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.
• 16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.

194 Rev. 1.2 17.6. Timing The timing parameters of the External Memory In terface can be configured to enable connection to devices having different setup and hold time requirements. The Address Setup time, Address Hold time, / RD and /WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods through EMI0TC, shown in Figure 17.6, and EMI0CF[1:0]. The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for /RD or /WR pulse + 4 SYSCLKs). For multiplexed oper ations, the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in multiplexed mode is 7 SYSCLK cycles (2 for /ALE + 1 for /RD or /WR + 4). The programm able setup and hold times default to the maximum delay settings after a reset. Figure 17.6. EMI0TC: External Memory Timing Control Bits7-6: EAS1-0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: Address setup time = 1 SYSCLK cycle. 10: Address setup time = 2 SYSCLK cycles. 11: Address setup time = 3 SYSCLK cycles. Bits5-2: EWR3-0: EMIF /WR and /RD Pulse-Width Control Bits. 0000: /WR and /RD pulse width = 1 SYSCLK cycle. 0001: /WR and /RD pulse width = 2 SYSCLK cycles. 0010: /WR and /RD pulse width = 3 SYSCLK cycles. 0011: /WR and /RD pulse width = 4 SYSCLK cycles. 0100: /WR and /RD pulse width = 5 SYSCLK cycles. 0101: /WR and /RD pulse width = 6 SYSCLK cycles. 0110: /WR and /RD pulse width = 7 SYSCLK cycles. 0111: /WR and /RD pulse width = 8 SYSCLK cycles. 1000: /WR and /RD pulse width = 9 SYSCLK cycles. 1001: /WR and /RD pulse width = 10 SYSCLK cycles. 1010: /WR and /RD pulse width = 11 SYSCLK cycles. 1011: /WR and /RD pulse width = 12 SYSCLK cycles. 1100: /WR and /RD pulse width = 13 SYSCLK cycles. 1101: /WR and /RD pulse width = 14 SYSCLK cycles. 1110: /WR and /RD pulse width = 15 SYSCLK cycles. 1111: /WR and /RD pulse width = 16 SYSCLK cycles. Bits1-0: EAH1-0: EMIF Address Hold Time Bits. 00: Address hold time = 0 SYSCLK cycles. 01: Address hold time = 1 SYSCLK cycle. 10: Address hold time = 2 SYSCLK cycles. 11: Address hold time = 3 SYSCLK cycles. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EAS1 EAS0 ERW3 EWR2 EWR1 EWR0 EAH1 EAH0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xA1

Rev. 1.2 195 Table 17.1 lists the AC parameters for the Exter nal Memory Interface, and Figure 17.7 through Figure 17.12 show the timing diagrams for the different External Memory Interface modes and MOVX operations.

196 Rev. 1.2 17.6.1. Non-multiplexed Mode EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPLP6 P4.7 P4.6 P7 EMIF WRITE DATA P4.7 P4.6 TACH TWDH TACWTACS TWDS ADDR[15:8] ADDR[7:0] DATA[7:0] /WR /RD EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPLP6 P4.6 P4.7 P4.6 P4.7 TACH TRDH TACWTACS TRDS ADDR[15:8] ADDR[7:0] DATA[7:0] /RD /WR EMIF READ DATA Nonmuxed 16-bit WRITE Nonmuxed 16-bit READ Figure 17.7. Non-multiplexed 16-bit MOVX Timing

Rev. 1.2 197 EMIF ADDRESS (8 LSBs) from R0 or R1P6 P4.7 P4.6 P7 EMIF WRITE DATA P4.7 P4.6 TACH TWDH TACWTACS TWDS ADDR[15:8] ADDR[7:0] DATA[7:0] /WR /RD EMIF ADDRESS (8 LSBs) from R0 or R1P6 P4.6 P4.7 P4.6 P4.7 TACH TRDH TACWTACS TRDS ADDR[15:8] ADDR[7:0] DATA[7:0] /RD /WR EMIF READ DATA Nonmuxed 8-bit WRITE without Bank Select Nonmuxed 8-bit READ without Bank Select Figure 17.8. Non-multiplexed 8-bit MOVX without Bank Select Timing

198 Rev. 1.2 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1P6 P4.7 P4.6 P7 EMIF WRITE DATA P4.7 P4.6 TACH TWDH TACWTACS TWDS ADDR[15:8] ADDR[7:0] DATA[7:0] /WR /RD EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1P6 P4.6 P4.7 P4.6 P4.7 TACH TRDH TACWTACS TRDS ADDR[15:8] ADDR[7:0] DATA[7:0] /RD /WR EMIF READ DATA Nonmuxed 8-bit WRITE with Bank Select Nonmuxed 8-bit READ with Bank Select Figure 17.9. Non-multiplexed 8-bit MOVX with Bank Select Timing

Rev. 1.2 199 17.6.2. Multiplexed Mode ADDR[15:8] AD[7:0] P4.7 P4.6 P4.5 P4.7 P4.6 P4.5 TACH TWDH TACWTACS TWDS ALE /WR /RD EMIF ADDRESS (8 MSBs) from DPH EMIF WRITE DATAEMIF ADDRESS (8 LSBs) from DPL TALEH TALEL ADDR[15:8] AD[7:0] P4.6 P4.7 P4.5 P4.6 P4.7 P4.5 TACHTACWTACS ALE /RD /WR EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL TALEH TALEL TRDHTRDS EMIF READ DATA Muxed 16-bit WRITE Muxed 16-bit READ Figure 17.10. Multiplexed 16-bit MOVX Timing

200 Rev. 1.2 ADDR[15:8] AD[7:0] P4.7 P4.6 P4.5 P4.7 P4.6 P4.5 TACH TWDH TACWTACS TWDS ALE /WR /RD EMIF WRITE DATAEMIF ADDRESS (8 LSBs) from R0 or R1 TALEH TALEL ADDR[15:8] AD[7:0] P4.6 P4.7 P4.5 P4.6 P4.7 P4.5 TACHTACWTACS ALE /RD /WR EMIF ADDRESS (8 LSBs) from R0 or R1 TALEH TALEL TRDHTRDS EMIF READ DATA Muxed 8-bit WRITE Without Bank Select Muxed 8-bit READ Without Bank Select Figure 17.11. Multiplexed 8-bit MOVX without Bank Select Timing

Rev. 1.2 201 ADDR[15:8] AD[7:0] P4.7 P4.6 P4.5 P4.7 P4.6 P4.5 TACH TWDH TACWTACS TWDS ALE /WR /RD EMIF ADDRESS (8 MSBs) from EMI0CN EMIF WRITE DATAEMIF ADDRESS (8 LSBs) from R0 or R1 TALEH TALEL ADDR[15:8] AD[7:0] P4.6 P4.7 P4.5 P4.6 P4.7 P4.5 TACHTACWTACS ALE /RD /WR EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 TALEH TALEL TRDHTRDS EMIF READ DATA Muxed 8-bit WRITE with Bank Select Muxed 8-bit READ with Bank Select Figure 17.12. Multiplexed 8-bit MOVX with Bank Select Timing

202 Rev. 1.2 Table 17.1. AC Parameters for External Memory Interface Parameter Description Min Max Units TSYSCLK System Clock Period 40 ns TACS Address / Control Setup Time 0 3*T SYSCLK ns TACW Address / Control Pulse Width 1*T SYSCLK 16*TSYSCLK ns TACH Address / Control Hold Time 0 3*T SYSCLK ns TALEH Address Latch Enable High Time 1*T SYSCLK 4*TSYSCLK ns TALEL Address Latch Enable Low Time 1*T SYSCLK 4*TSYSCLK ns TWDS Write Data Setup Time 1*T SYSCLK 19*TSYSCLK ns TWDH Write Data Hold Time 0 3*T SYSCLK ns TRDS Read Data Setup Time 20 ns TRDH Read Data Hold Time 0 ns

Rev. 1.2 203 18. Port Input/Output The C8051F06x family of devices are fully integrated mixed-signal System on a Chip MCUs with 59 digital I/O pins (C8051F060/2/4/6) or 24 digital I/O pins (C8051F061/3/5/7), organized as 8-bit Ports. All ports are both bit- and byte-addressable through their correspondi ng Port Data registers. All Port pins support con- figurable Open-Drain or Push-Pull output modes and we ak pull-ups. Additionally, Port 0 pins are 5 V-toler- ant. A block diagram of the Port I/O cell is shown in Figure 18.1. Complete Electrical Specifications for the Port I/O pins are given in Table 18.1. DGND /PORT-OUTENABLE PORT-OUTPUT PUSH-PULL VDD VDD /WEAK-PULLUP (WEAK) PORT PAD ANALOG INPUT Analog Select (Port 1 and 2 Only) PORT-INPUT Figure 18.1. Port I/O Cell Block Diagram Table 18.1. Port I/O DC Electrical Characteristics VDD = 2.7 to 3.6 V, -40 to +85 °C unless otherwise specified. Parameter Conditions Min Typ Max Units Output High Voltage OH) IOH = -3 mA, Port I/O Push-Pull IOH = -10 µA, Port I/O Push-Pull VDD - 0.7 VDD - 0.1 V Output Low Voltage (VOL) IOL = 8.5 mA IOL = 10 µA 0.6 0.1 V Input High Voltage (VIH) 0.7 x VDD Input Low Voltage (VIL) 0.3 x VDD Input Leakage Current DGND < Port Pin < VDD, Pin Tri-state Weak Pull-up Off Weak Pull-up On 10 ±1 µ A µA Input Capacitance 5 pF

204 Rev. 1.2 The C8051F06x family of devices hav e a wide array of digital resources which are available through the four lower I/O Ports: P0, P1, P2, and (on the C8051F060/2/4/6) P3. Each of the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GPIO) pin or can be controlled by a digital peripheral or function (like UART0 or /INT1 for example), as show n in Figure 18.2. The system designer controls which digital functions are assigned pins, limited only by the number of pins available. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read from its associated Data register regardless of whether that pin has been assigned to a digital peripheral or behaves as GPIO. The Port pins on Port 2 can be used as analog inputs to the ana- log Voltage comparators. On the C8051F060/1/2/3, the pins of Port 1 can be used as analog inputs for ADC2. The upper Ports (available on C8051F060/2/4/6) can be byte-accessed as GPIO pins, or used as part of an External Memory Interface which is active duri ng a MOVX instruction whose target address resides in off-chip memory. See Section “17. External Data Memory Interface and On-Chip XRAM” on page 187 for more information about the External Memory Interface. External Pins Digital Crossbar Priority Decoder SMBus SPI 4 UART0 PCA T0, T1, T2, T2EX, T3, T3EX, T4,T4EX, /INT0, /INT1 P1.0 P1.7 P2.0 P2.7 P0.0 P0.7 Highest Priority Lowest Priority Comptr. Outputs (Internal Digital Signals) Highest Priority Lowest Priority UART1 P3.0 P3.7 P0MDOUT, P1MDOUT, P2MDOUT, P3MDOUT Registers XBR0, XBR1, XBR2, XBR3 P1MDIN, P2MDIN, P3MDIN Registers I/O Cells I/O Cells I/O Cells I/O Cells Port Latches (P2.0-P2.7) (P1.0-P1.7) (P0.0-P0.7) (P3.0-P3.7) To ADC2 Input To Comparators /SYSCLK CNVSTR2 C8051F060/2 Only Figure 18.2. Port I/O Functional Block Diagram

206 Rev. 1.2 eral’s enable bits are not set to a logic 1, then its ports are not accessible at the Port pins of the device. Also note that the Crossbar assigns pins to all associated functions when the SMBus, UART0 or UART1 are selected (i.e. SMBus, SPI, UART). It would be impo ssible, for example, to assign TX0 to a Port pin without assigning RX0 as well. The SPI can operate in 3 or 4-wire mode (with or without NSS). Each com- bination of enabled peripherals results in a unique device pinout. All Port pins on Ports 0 through 3 that are not allocated by the Crossbar can be accessed as General-Pur- pose I/O (GPIO) pins by reading and writing the associated Port Data registers (See Figure 18.9, Figure 18.11, Figure 18.14, and Figure 18.17), a set of SFRs which are both byte- and bit-addressable. The output states of Port pins that are allocated by the Crossbar are controlled by the digital peripheral that is mapped to those pins. Writes to the Port Data re gisters (or associated Port bits) will have no effect on the states of these pins. A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regard- less of whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs during the execution of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC, CLR, SETB, and the bitwise MOV write operation). During the read cycle of the read-modify-write instruc- tion, it is the contents of the Port Data register, not the state of the Port pins themselves, which is read. Because the Crossbar registers affect the pinout of the peripherals of the device, they are typically config- ured in the initialization code of the system before the peripherals themselves are configured. Once config- ured, the Crossbar registers are typically left alone. Once the Crossbar registers have been properly co nfigured, the Crossbar is enabled by setting XBARE (XBR2.4) to a logic 1. Until XBARE is set to a logic 1, the output drivers on Ports 0 through 3 are explicitly disabled in order to prevent possible contention on the Port pins while the Crossbar reg- isters and other registers which can affect the device pinout are being written. The output drivers on Crossbar-assigned input signals ( like RX0, for example) are explicitly disabled; thus the values of the Port Data registers and the PnMD OUT registers have no effect on the states of these pins. 18.1.2. Configuring the Output Modes of the Port Pins The output drivers on Ports 0 through 3 remain disabl ed until the Crossbar is enabled by setting XBARE (XBR2.4) to a logic 1. The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull configuration, writing a logic 0 to the associated bit in the Port Data register will cause the Port pin to be driven to GND, and writing a logic 1 will cause the Port pin to be driven to VDD. In the Open-Drain configu- ration, writing a logic 0 to the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to assume a high-impedance state. The Open-Drain configura- tion is useful to prevent contention between devices in systems where the Port pin participates in a shared interconnection in which multiple ou tputs are connected to the same ph ysical wire (like the SDA signal on an SMBus connection). The output modes of the Port pins on Ports 0 through 3 are determined by the bits in the associated PnM- in P3MDOUT.7 will configure the output mode of P3.7 to Push-Pull; a logic 0 in P3MDOUT.7 will configure the output mode of P3.7 to Open-Drain. All Port pins default to Open-Drain output.

Rev. 1.2 207 The PnMDOUT registers control the output modes of the port pins regardless of whether the Crossbar has allocated the Port pin for a digital peripheral or not. The exceptions to this rule are: the Port pins connected to SDA, SCL, RX0 (if UART0 is in Mode 0), and RX 1 (if UART1 is in Mode 0) are always configured as Open-Drain outputs, regardless of the settings of the associated bits in the PnMDOUT registers. 18.1.3. Configuring Port Pins as Digital Inputs A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to the associated bit in the Port Data register. For exampl e, P3.7 is configured as a digital input by setting P3MDOUT.7 to a logic 0 and P3.7 to a logic 1. If the Port pin has been assigned to a digital peripheral by the Crossbar and that pin functions as an input (for example RX0, the UART0 receive pin), then the output drivers on that pin are automatically disabled. 18.1.4. Weak Pull-ups By default, each Port pin has an internal weak pu ll-up device enabled which pr ovides a resistive connec- tion (about 100 kΩ) between the pin and VDD. The weak pull-up devices can be globally disabled by writ- ing a logic 1 to the Weak Pull-up Disable bit, (WEAKPUD, XBR2.7). The weak pull-up is automatically deactivated on any pin that is driv ing a logic 0; that is, an output pin will not contend with its own pull-up device. The weak pull-up device can also be explicitly disabled on a Port 1 pin by configuring the pin as an Analog Input, as described below. 18.1.5. Configuring Port 1 and 2 pins as Analog Inputs The pins on Port 1 can serve as analog inputs to the ADC2 analog MUX (C8051F060/1/2/3 only) and the pins on Port 2 can serve as analog inputs to the Comparators (all devices). A Port pin is configured as an Analog Input by writing a logic 0 to the associated bit in the PnMDIN registers. All Port pins default to a Digital Input mode. Configuring a Port pin as an analog input: 1. Disables the digital input path from the pin. Th is prevents additional power supply current from being drawn when the voltage at the pin is near VDD / 2. A read of the Port Data bit will return a logic 0 regardless of the voltage at the Port pin. 2. Disables the weak pull-up device on the pin. 3. Causes the Crossbar to “skip over” the pin when allocating Port pins for digital peripherals. Note that the output drivers on a pin configured as an Analog Input are not explicitly disabled. Therefore, the associated PnMDOUT bits of pins configured as Analog Inputs should explicitly be set to logic 0 (Open-Drain output mode), and the as sociated Port Data bits should be set to logic 1 (high-impedance). Also note that it is not required to configure a Port pi n as an Analog Input in order to use it as an input to ADC2 or the Comparators, however, it is strongly recommended. See the analog peripheral’s correspond- ing section in this datasheet for further information.

208 Rev. 1.2 18.1.6. Crossbar Pin Assignment Example In this example (Figure 18.4), we configure the Crossbar to allocate Port pins for UART0, the SMBus, all 6 PCA modules, /INT0, and /INT1 (12 pins total). Additi onally, we configure P1.2, P1.3, and P1.4 for Analog Input mode so that the voltages at these pins can be measured by ADC2. The configuration steps are as follows: XBR0, XBR1, and XBR2 are set such that UART0EN = 1, SMB0EN = 1, PCA0ME = ‘110’, INT0E = 1, and INT1E = 1. Thus: XBR0 = 0x3D, XBR1 = 0x14, and XBR2 = 0x40. 1. We configure the desired Port 1 pins to Analog Input mode by setting P1MDIN to 0xE3 (P1.4, P1.3, and P1.2 are Analog Inputs, so their associated P1MDIN bits are set to logic 0). 2. We enable the Crossbar by setting XBARE = 1: XBR2 = 0x40. - UART0 has the highest priority, so P0.0 is assigned to TX0, and P0.1 is assigned to RX0. - The SMBus is next in priority order, so P0.2 is assigned to SDA, and P0.3 is assigned to SCL. - PCA0 is next in priority order, so P0.4 through P1.1 are assigned to CEX0 through CEX5 - P1MDIN is set to 0xE3, which configures P1 .2, P1.3, and P1.4 as Analog Inputs, causing the Crossbar to skip these pins. - /INT0 is next in priority order, so it is assi gned to the next non-skipped pin, which is P1.5. - /INT1 is next in priority order, so it is assigned to P1.6. 3. We set the UART0 TX pin (TX0, P0.0) output and the CEX0-3 outputs to Push-Pull by setting P0MDOUT = 0xF1. 4. We explicitly disable the outp ut drivers on the 3 Analog Input pins by setting the corresponding bits in the P1MDOUT register to ‘0’, and in P1 to ‘1’. Additionally, the CEX5-4 output pins are set to Push-Pull mode. Therefore, P1MDOUT = 0x 03 (configure unused pins to Open-Drain) and P1 = 0xFF (a logic 1 selects the high-impedance state).

Rev. 1.2 209 Figure 18.4. Crossbar Example: (P1MDIN = 0xE3; XBR0 = 0x3D; XBR1 = 0x14; XBR2 = 0x40) PIN I/O 01234567012345670123456701234567 TX0 ● RX0 ● SCK ●● MISO ●● MOSI ●● NSS ●● AIN2.0 AIN2.1 AIN2.2 AIN2.3 AIN2.4 AIN2.5 AIN2.6 AIN2.7 CP1+ CP1- CP2+ CP2- CP0+ CP0- P0 P1 P2 P3 Crossbar Register Bits XBR0.2 XBR0.1 XBR0.0SMB0EN: XBR2.2 XBR0.[5:3] UART0EN: SPI0EN: UART1EN: PCA0ME:

210 Rev. 1.2 Figure 18.5. XBR0: Port I/O Crossbar Register 0 Bit7: CP0E: Comparator 0 Output Enable Bit. 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. Bit6: ECI0E: PCA0 External Counter Input Enable Bit. 0: PCA0 External Counter Input unavailable at Port pin. 1: PCA0 External Counter Input (ECI0) routed to Port pin. Bits5-3: PCA0ME: PCA0 Mo dule I/O Enable Bits. 000: All PCA0 I/O unavailable at port pins. 001: CEX0 routed to port pin. 010: CEX0, CEX1 routed to 2 port pins. 011: CEX0, CEX1, and CEX2 routed to 3 port pins. 100: CEX0, CEX1, CEX2, and CEX3 routed to 4 port pins. 101: CEX0, CEX1, CEX2, CEX3, and CEX4 routed to 5 port pins. 110: CEX0, CEX1, CEX2, CEX3, CEX4, and CEX5 routed to 6 port pins. Bit2: UART0EN: UART0 I/O Enable Bit. 0: UART0 I/O unavailable at Port pins. 1: UART0 TX routed to P0.0, and RX routed to P0.1. Bit1: SPI0EN: SPI0 Bus I/O Enable Bit. 0: SPI0 I/O unavailable at Port pins. 4-wire mode: 1: SPI0 SCK, MISO, MOSI, and NSS routed to 4 Port pins. 3-wire mode: 1: SPI0 SCK, MISO and MOSI routed to 3 Port pins. Bit0: SMB0EN: SMBus0 Bus I/O Enable Bit. 0: SMBus0 I/O unavailable at Port pins. 1: SMBus0 SDA and SCL routed to 2 Port pins. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value CP0E ECI0E PCA0ME UART0EN SPI0EN SMB0EN 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xE1 F

Rev. 1.2 211 Figure 18.6. XBR1: Port I/O Crossbar Register 1 Bit7: SYSCKE: /SYSCLK Output Enable Bit. 0: /SYSCLK unavailable at Port pin. 1: /SYSCLK routed to Port pin. Bit6: T2EXE: T2EX Input Enable Bit. 0: T2EX unavailable at Port pin. 1: T2EX routed to Port pin. Bit5: T2E: T2 Input Enable Bit. 0: T2 unavailable at Port pin. 1: T2 routed to Port pin. Bit4: INT1E: /INT1 Input Enable Bit. 0: /INT1 unavailable at Port pin. 1: /INT1 routed to Port pin. Bit3: T1E: T1 Input Enable Bit. 0: T1 unavailable at Port pin. 1: T1 routed to Port pin. Bit2: INT0E: /INT0 Input Enable Bit. 0: /INT0 unavailable at Port pin. 1: /INT1 routed to Port pin. Bit1: T0E: T0 Input Enable Bit. 0: T0 unavailable at Port pin. 1: T1 routed to Port pin. Bit0: CP1E: CP1 Output Enable Bit. 0: CP1 unavailable at Port pin. 1: CP1 routed to Port pin. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SYSCKE T2EXE T2E INT1E T1E INT0E T0E CP1E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xE2 F

212 Rev. 1.2 Figure 18.7. XBR2: Port I/O Crossbar Register 2 Bit7: WEAKPUD: Weak Pu ll-Up Disable Bit. 0: Weak pull-ups globally enabled. 1: Weak pull-ups globally disabled. Bit6: XBARE: Crossb ar Enable Bit. 0: Crossbar disabled. All pins on Ports 0, 1, 2, and 3, are forced to Input mode. 1: Crossbar enabled. Bit5: UNUSED. Read = 0, Write = don't care. Bit4: T4EXE: T4EX Input Enable Bit. 0: T4EX unavailable at Port pin. 1: T4EX routed to Port pin. Bit3: T4E: T4 Input Enable Bit. 0: T4 unavailable at Port pin. 1: T4 routed to Port pin. Bit2: UART1E: UART1 I/O Enable Bit. 0: UART1 I/O unavailable at Port pins. 1: UART1 TX and RX routed to 2 Port pins. Bits1-0: Reserved R/W R/W R/W R/W R/W R/W R/W R/W Reset Value WEAKPUD XBARE - T4EXE T4E UART1E - - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xE3 F

Rev. 1.2 213 Figure 18.8. XBR3: Port I/O Crossbar Register 3 Bit7: CTXOUT: CAN Transmit Pin (CTX) Output Mode. 0: CTX pin output mode is configured as open-drain. 1: CTX pin output mode is configured as push-pull. Bit6-4: Reserved Bit3: CP2E: CP2 Output Enable Bit. 0: CP2 unavailable at Port pin. 1: CP2 routed to Port pin. Bit2: CNVST2E: ADC2 External Convert Start Input Enable Bit. 0: CNVST2 for ADC2 unavailable at Port pin. 1: CNVST2 for ADC2 routed to Port pin. Bit1: T3EXE: T3EX Input Enable Bit. 0: T3EX unavailable at Port pin. 1: T3EX routed to Port pin. Bit0: T3E: T3 Input Enable Bit. 0: T3 unavailable at Port pin. 1: T3 routed to Port pin. R R R R/W R/W R/W R/W R/W Reset Value CTXOUT - - CP2E CNVST2E T3EXE T3E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xE4 F

Rev. 1.2 219 18.2. Ports 4 through 7 (C8051F060/2/4/6 only) All Port pins on Ports 4 through 7 can be accessed as General-Purpose I/O (GPIO) pins by reading and writing the associated Port Data registers (S ee Figure 18.19, Figure 18.21, Figure 18.23, and Figure 18.25), a set of SFRs which are byte-addressable. Note that Port 4 has only three pins: P4.5, P4.6, and P4.7. Note also that the Port 4, 5, 6, and 7 registers are located on SFR Page F. The SFRPAGE reg- ister must be set to 0x0F to access these Port registers. A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regard- less of whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs during the execution of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC, CLR, SETB, and the bitwise MOV write operation). During the read cycle of the read-modify-write instruc- tion, it is the contents of the Port Data register, not the state of the Port pins themselves, which is read. 18.2.1. Configuring Ports which are not Pinned Out Although P3, P4, P5, P6, and P7 are not brought out to pins on the C8051F0 61/3/5/7 devices, the Port Data registers are still present and can be used by software. Because the digital input paths also remain active, it is recommended that these pins not be left in a ‘floating’ state in order to avoid unnecessary power dissipation arising from the inputs floating to non-valid logic levels. This condition can be prevented by any of the following: 1. Leave the weak pull-up de vices enabled by setting WEAKPUD (XBR2.7) to a logic 0. 2. Configure the output modes of P3, P4, P5, P6, and P7 to “Push-Pull” by writing 0xFF to the associated output mode register (PnMDOUT). 3. Force the output states of P3, P4, P5, P6, and P7 to logic 0 by writin g zeros to the Port Data registers: P3 = 0x00, P4 = 0x00, P5 = 0x00, P6= 0x00, and P7 = 0x00. 18.2.2. Configuring the Output Modes of the Port Pins The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull configuration, a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to be driven to VDD. In the Open-Drain configuration, a logic 0 in the associated bit in the Po rt Data register will cause the Port pi n to be driven to GND, and a logic 1 will cause the Port pin to assume a high-impedance state. The Open-Drain configuration is useful to prevent contention between devices in syst ems where the Port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire. The output modes of the Port pins on Ports 4 through 7 are determined by the bits in their respective PnM- DOUT Output Mode Registers. Each bit in PnMDOUT controls the output mode of its corresponding port push-pull mode (digital output), se t P5MDOUT.3 to logic 1. All port pins default to open-drain mode upon device reset. 18.2.3. Configuring Port Pins as Digital Inputs A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to the associated bit in the Port Data register. For exampl e, P7.7 is configured as a digital input by setting P7MDOUT.7 to a logic 0 and P7.7 to a logic 1. 18.2.4. Weak Pull-ups By default, each Port pin has an internal weak pu ll-up device enabled which pr ovides a resistive connec- tion (about 100 kΩ) between the pin and VDD. The weak pull-up devices can be globally disabled by writ-

220 Rev. 1.2 ing a logic 1 to the Weak Pull-up Disable bit, (WEAKPUD, XBR2.7). The weak pull-up is automatically deactivated on any pin that is driv ing a logic 0; that is, an output pin will not contend with its own pull-up device. 18.2.5. External Memory Interface If the External Memory Interface is enabled on the High ports and an off-chip MOVX operation occurs, the External Memory Interface will contro l the output states of the affected Port pins during the execution phase of the MOVX instruction, regardless of the settings of the Port Data registers. The output configura- tion of the Port pins is not affected by the EMIF oper ation, except that Read operations will explicitly dis- able the output drivers on the Data Bus during the MOVX execution. See Section “17. External Data Memory Interface and On-Chip XRAM” on page 187 for more information about the External Memory Inter- face.

Rev. 1.2 225 19. Controller Area Networ k (CAN0, C8051F060/1/2/3) IMPORTANT DOCUMENTATION NOTE: The Bosch CAN Controller is integrated in the C8051F060/1/2/3 devices. This section of the data sheet gives a description of the CAN controller as an overview and offers a description of how the Silicon Labs CIP-51 MCU in terfaces with the on-chip Bosch CAN controller. In order to use the CAN controller, please refer to Bosch’s C_CAN User’s Manual (revision 1.2) as an accom- panying manual to Silicon Labs’ C8051F060/1/2/3/4/5/6/7 Data sheet. The C8051F060/1/2/3 family of devices feature a Co ntrol Area Network (CAN) controller that enables serial communication using the CAN protocol. Silicon Labs CAN controller facilit ates communication on a CAN network in accordance with the Bosch specification 2.0A (bas ic CAN) and 2.0B (full CAN). The CAN controller consists of a CAN Core, Message RAM (separate from the CIP-51 RAM), a message handler state machine, and control registers. Silicon Labs CAN is a protocol controller and does not provide physi- Silicon Labs CAN operates at bit rates of up to 1 Mb it/second, though this can be limited by the physical layer chosen to transmit data on the CAN bus. The CAN processor has 32 Message Objects that can be configured to transmit or receive data. Incoming data, message objects and their identifier masks are stored in the CAN message RAM. All protocol functions for transmission of data and acceptance filtering is performed by the CAN controller and not by the CIP-51 MCU. In this way, minimal CPU bandwidth is needed to use CAN communication. The CIP-51 config ures the CAN controller, accesses received data, and passes data for transmission via Special Functi on Registers (SFR) in the CIP-51. The CAN control- ler’s clock (f sys, or CAN_CLK in the C_CAN User’s Guide) is equal to the CIP-51 MCU’s clock (SYSCLK).

Rev. 1.2 227 19.1. Bosch CAN Cont roller Operation The CAN Controller featured in the C8051F060/1/2/3 devices is a full implementation of Bosch’s full CAN module and fully complies with CAN specification 2.0B. The function and use of the CAN Controller is detailed in the Bosch CAN User’s Guide. The User’s Guide should be used as a re ference to configure and use the CAN co ntroller. This Silicon Labs datasheet describes how to access the CAN controller. The CAN Control Register (CAN0CN), CAN Test Register (CAN0TST), an d CAN Status Register (CAN0STA) in the CAN controller can be accessed dire ctly or indirectly via CIP-51 SFRs. All other CAN registers must be accessed via an indirect inde xing method. See “Using CAN0ADR, CAN0DATH, and CANDATL To Access CAN Registers” on page 229.

228 Rev. 1.2 19.2. CAN Registers CAN registers are classified as follows: 1. CAN Controller Protocol Registers : CAN control, interrupt, error control, bus status, test modes. 2. Message Object Interface Registers : Used to configure 32 Message Objects, send and receive data to and from Message Objects. The C8051 MCU accesses the CAN message RAM via the Message Object Interface Registers. Upon writing a message object number to an IF1 or IF2 Command Request Register, the contents of the associated Interface Registers (IF1 or IF2) will be transferred to or from the message object in CAN RAM. 3. Message Handler Registers : These read only registers are used to provide information to the CIP-51 MCU about the message object s (MSGVLD flags, Transmission Request Pending, New Data Flags) and Interrupts Pending (which Message Objects have caused an interrupt or status interrupt condition). 4. C8051 MCU Special Function Registers (SFR) : Five registers located in the C8051 MCU memory map that allow direct access to ce rtain CAN Controller Protocol Registers, and Indexed indirect access to all CAN registers. 19.2.1. CAN Controller Protocol Registers The CAN Control Protocol Registers are used to config ure the CAN controller, process interrupts, monitor bus status, and place the controller in test modes. The CAN controller protocol registers are accessible using C8051 MCU SFRs by an indexed method, and some can be accessed directly by addressing the SFRs in the C8051 SFR map for convenience. The registers are: CAN Control Register (CAN0CN), CAN Status Register (CAN0STA), CAN Test Register (CAN0TST), Error Counter Register, Bit Timing Regi ster, and the Baud Rate Prescaler (BRP) Extension Register. CAN0STA, CAN0CN, and CAN0TST can be accessed via C8051 MCU SFRs. All others are accessed indirectly using the CAN address indexed method via CAN0ADR, CAN0DATH, and CAN0DATL. Please refer to the Bosch CAN User’s Guide for information on the function and use of the CAN Control Protocol Registers. 19.2.2. Message Object Interface Registers There are two sets of Message Object Interface Registers used to configure the 32 Message Objects that transmit and receive data to and from the CAN bus. Message objects can be configured for transmit or receive, and are assigned arbitration message identifiers for acceptance filtering by all CAN nodes. Message Objects are stored in Message RAM, and are accessed and configured using the Message Object Interface Registers. These registers are accessed via the C8051’s CAN0ADR and CAN0DAT regis- ters using the indirect indexed address method. Please refer to the Bosch CAN User’s Guide for information on the function and use of the Mes- sage Object Interface Registers. 19.2.3. Message Handler Registers The Message Handler Registers are read only registers. Their flags can be read via the indexed access method with CAN0ADR, CAN0DATH, and CAN0DATL. The message handler registers provide interrupt, error, transmit/receive requests, and new data information.

Rev. 1.2 229 Please refer to the Bosch CAN User’s Guide for information on the function and use of the Mes- sage Handler Registers. 19.2.4. CIP-51 MCU Special Function Registers C8051F060/1/2/3 peripherals are modified, monitored, and controlled using Special Function Registers (SFRs). Most of the CAN Controlle r registers cannot be accessed directly using the SFRs. Three of the CAN Controller’s registers may be accessed directly with SFRs. All other CAN Controller registers are accessed indirectly using three CIP-51 MCU SFRs: the CAN Data Registers (CAN0DATH and CAN0DATL) and CAN Address Register (CAN0ADR). In this way, there are a total of five CAN registers used to configure and run the CAN Controller. 19.2.5. Using CAN0ADR, CAN0DATH, and CANDATL To Access CAN Registers Each CAN Controller Register has an index number (see Table below). The CAN register address space is 128 words (256 bytes). A CAN register is a ccessed via the CAN Data Registers (CAN0DATH and CAN0DATL) when a CAN register’s index number is placed into the CAN Address Register (CAN0ADR). For example, if the Bit Timing Regi ster is to be configured with a new value, CAN0ADR is loaded with 0x03. The low byte of the desired value is accessed using CAN0DATL and the high byte of the bit timing register is accessed using CAN0DATH. CAN0DATL is bit addressable for convenience. To load the value 0x2304 into the Bit Timing Register: CAN0ADR = 0x03; // Load Bit Timing Register’s index (Table 18.1) CAN0DATH = 0x23; // Move the upper byte into data reg high byte CAN0DATL = 0x04; // Move the lower byte into data reg low byte Note: CAN0CN, CAN0STA, and CAN0TST may be accessed either by using the index method, or by direct access with the CIP-51 MCU SFRs. CAN0CN is located at SFR locati on 0xF8/SFR page 1 (Figure 19.6), CAN0TST at 0xDB/SFR page 1 (Figure 19.7), and CAN0STA at 0xC0/SFR page 1 (Figure 19.8). 19.2.6. CAN0ADR Autoincrement Feature For ease of programming message objects, CAN0ADR features autoincrementing for the index ranges 0x08 to 0x12 (Interface Registers 1) and 0x20 to 0x2A (Interface Registers 2). When the CAN0ADR regis- ter has an index in these ranges, the CAN0ADR will autoincrement by 1 to point to the next CAN reg- ister 16-bit word upon a read/write of CAN0DATL . This speeds programming of the frequently programmed interface registers when configuring message objects. NOTE: Table below supersedes Figure 5 in section 3, “Programmer’s Model” of the Bosch CAN User’s Guide. Table 19.1. CAN Register Index and Reset Values CAN Register Index Register name Reset Value Notes 0x00 CAN Control Register 0x0001 Accessible in CIP-51 SFR Map 0x01 Status Register 0x0000 Accessible in CIP-51 SFR Map 0x02 Error Register 0x0000 Read Only 0x03 Bit Timing Register 0x2301 Write Enabled by CCE Bit in CAN0CN

230 Rev. 1.2 0x04 Interrupt Register 0x0000 Read Only 0x05 Test Register 0x0000 Bit 7 (R X) is determined by CAN bus 0x06 BRP Extension Register 0x0000 Write Enabled by TEST bit in CAN0CN 0x08 IF1 Command Request 0x0001 CAN0ADR autoincrements in IF1 index space (0x08 - 0x12) upon write to CAN0DATL 0x09 IF1 Command Mask 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x0A IF1 Mask 1 0xFFFF CAN0ADR autoin crement upon write to CAN0DATL 0x0B IF1 Mask 2 0xFFFF CAN0ADR autoin crement upon write to CAN0DATL 0x0C IF1 Arbitration 1 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x0D IF1 Arbitration 2 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x0E IF1 Message Control 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x0F IF1 Data A1 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x10 IF1 Data A2 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x11 IF1 Data B1 0x0000 CAN0ADR auto increment upon write to CAN0DATL 0x12 IF1 Data B2 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x20 IF2 Command Request 0x0001 CAN0ADR autoincrements in IF1 index space (0x08 - 0x12) upon write to CAN0DATL 0x21 IF2 Command Mask 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x22 IF2 Mask 1 0xFFFF CAN0ADR autoin crement upon write to CAN0DATL 0x23 IF2 Mask 2 0xFFFF CAN0ADR autoin crement upon write to CAN0DATL 0x24 IF2 Arbitration 1 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x25 IF2 Arbitration 2 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x26 IF2 Message Control 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x27 IF2 Data A1 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x28 IF2 Data A2 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x29 IF2 Data B1 0x0000 CAN0ADR autoincrement upon write to CAN0DATL 0x2A IF2 Data B2 0x0000 CAN0ADR auto increment upon write to CAN0DATL 0x40 Transmission Request 1 0x0000 Transmiss ion request flags for message objects (read only) 0x41 Transmission Request 2 0x0000 Transmiss ion request flags for message objects (read only) 0x48 New Data 1 0x0000 New Data flags for message objects (read only) 0x49 New Data 2 0x0000 New Data flags for message objects (read only) 0x50 Interrupt Pending 1 0x0000 Interrupt pending flags for message objects (read only) 0x51 Interrupt Pending 2 0x0000 Interrupt pending flags for message objects (read only) 0x58 Message Valid 1 0x0000 Message valid flags for message objects (read only) Table 19.1. CAN Register Index and Reset Values (Continued) CAN Register Index Register name Reset Value Notes

234 Rev. 1.2

Rev. 1.2 235 20. System Management BUS / I2C BUS (SMBUS0) The SMBus0 I/O interface is a two-wire, bi-direction al serial bus. SMBus0 is compliant with the System Management Bus Specification, version 1.1, and compat ible with the I2C serial bus. Reads and writes to the interface by the system controller are byte ori ented with the SMBus0 interface autonomously control- ling the serial transfer of the data. A method of ext ending the clock-low duration is available to accommo- date devices with different speed capabilities on the same bus. SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0 provides control of SDA (serial data), SCL (serial cl ock) generation and synchron ization, arbitration logic, and START/STOP control and generation. Figure 20.1. SMBus0 Block Diagram SFR Bus Data Path Control SFR Bus Write to SMB0DAT SMBUS CONTROL LOGIC Read SMB0DATSMB0ADR S L V G C S L V S L V S L V S L V S L V S L V C R O S S B A R Clock Divide Logic SYSCLK SMB0CR C R C R C R C R C R C R C R C R SCL FILTER N SDA Control 0000000b

7 MSBs 8

A=B 01234567 SMB0DAT SMB0CN S T A S I A A F T E T O E E N S M B B U S Y S T O SMB0STA S T A S T A S T A S T A S T A SCL ControlStatus Generation Arbitration SCL Synchronization SCL Generation (Master Mode) IRQ Generation S T A S T A S T A AB A=B SMBUS IRQ Interrupt Request Port I/O SDA FILTER N

Rev. 1.2 237 The direction bit (R/W) occupies the least-significant bi t position of the address. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE operation from th e master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte. For READ operations , the slave transmits the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master generates a STOP condition to term inate the transaction and free the bu s. Figure 20.3 illustrates a typical SMBus transaction. 20.2.1. Arbitration A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time (see Section 20.2.4). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be pulled LOW. The master attempting the HIGH will detect a LOW SDA and give up the bus. The winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer. This arbitration scheme is non- destructive: one device always wins, and no data is lost. 20.2.2. Clock Low Extension SMBus provides a clock synchronizati on mechanism, similar to I2C, wh ich allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. 20.2.3. SCL Low Timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct th e error condition. To solve this problem, the SMBus protocol specifies that devices participating in a tran sfer must detect any clock cycle held low longer than 25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi- cation no later than 10 ms after detecting the timeout condition. 20.2.4. SCL High (SMBus Free) Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is designated as free. If an SMBus device is waiting to generat e a Master START, the START will be gen- erated following the bus free timeout. SLA6 SDA SLA5-0 R/W D7 D6-0 SCL Slave Address + R/W Data ByteSTART ACK NACK STOP Figure 20.3. SMBus Transaction

Rev. 1.2 239 20.3.3. Slave Transmitter Mode Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START followed by data byte containing the slave address and direction bit. If the received slave address matches the address held in regi ster SMB0ADR, the SM Bus0 interface generates an ACK. SMBus0 will also ACK if the general call address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to logic 1. In this case the data direction bit (R/W) will be logic 1 to indicate a "READ" operation. The SMBus0 interface receives the clock on SCL and transmits one or more bytes of serial data, waiting for an ACK from the master after each byte. SMBus0 exits slave mode after receiving a STOP condition from the master.20.3.4. Slave Receiver Mode Serial data is received on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START followed by data byte containing the slave addr ess and direction bit. If the received slave address matches the address held in register SMB0ADR, the interface generates an ACK. SMBus0 will also ACK if the general call address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to logic 1. In this case the data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The SMBus0 interface receives one or more bytes of seri al data; after each byte is received, the interface PRSLAS Data ByteData Byte A NA S = START P = STOP N = NACK R = READ SLA = Slave Address Received by SMBus Interface Transmitted by SMBus Interface Interrupt Interrupt Interrupt Interrupt Figure 20.6. Typical Slave Transmitter Sequence

240 Rev. 1.2 transmits an ACK or NACK depending on the state of the AA bit in SMB0CN. SMBus0 exits Slave Receiver Mode after receiving a STOP condition from the master. PWSLAS Data ByteData Byte A AA S = START P = STOP A = ACK W = WRITE SLA = Slave Address Received by SMBus Interface Transmitted by SMBus Interface Interrupt Interrupt Interrupt Interrupt Figure 20.7. Typical Slave Receiver Sequence

Rev. 1.2 241 20.4. SMBus Special Function Registers The SMBus0 serial interface is accessed and cont rolled through five SFRs: SMB0CN Control Register, SMB0CR Clock Rate Register, SMB0ADR Address Register, SMB0DAT Data Register and SMB0STA Sta- tus Register. The five special function registers related to the operation of the SMBus0 interface are described in the following sections. 20.4.1. Control Register The SMBus0 Control register SMB0CN is used to conf igure and control the SMBus0 interface. All of the bits in the register can be read or written by software. Two of the control bits are also affected by the SMBus0 hardware. The Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by the hardware when a valid serial interrupt condition occurs. It can only be cleared by software. The Stop flag (STO, SMB0CN.4) is set to logic 1 by software. It is cleared to logic 0 by hardware when a STOP condition is detected on the bus. Setting the ENSMB flag to logic 1 enables the SMBus0 interface. Clearing the ENSMB flag to logic 0 dis- ables the SMBus0 interface and removes it from the bus. Momentarily clearing the ENSMB flag and then resetting it to logic 1 will reset SMBu s0 communication. However, ENSMB should not be used to tempo- rarily remove a device from the bus since the bus state information will be lo st. Instead, the Assert Acknowledge (AA) flag should be used to temporarily remove the device from the bus (see description of AA flag below). Setting the Start flag (STA, SMB0CN.5) to logic 1 will put SMBus0 in a master mode. If the bus is free, SMBus0 will generate a START condition. If the bus is not free, SMBus0 waits for a STOP condition to free the bus and then generates a START condition after a 5 µs delay per the SMB0CR value (In accordance with the SMBus protocol, the SMBus0 interface also considers the bus free if the bus is idle for 50 µs and no STOP condition was recognized). If STA is set to logic 1 while SMBus0 is in master mode and one or more bytes have been transferred, a repeated START condition will be generated. When the Stop flag (STO, SMB0CN.4) is set to logic 1 while the SMBus0 interface is in master mode, the interface generates a STOP condition. In a slave mode, the STO flag may be used to recover from an error condition. In this case, a STOP condition is not generated on the bus, but the SMBus hardware behaves as if a STOP condition has been received and enters the "not addressed" slave receiver mode. Note that this simulated STOP will not cause the bus to appear free to SMBus0. The bus will remain occupied until a STOP appears on the bus or a Bus Free Timeout occurs. Hardware automatically clears the STO flag to logic 0 when a STOP condition is detected on the bus. The Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by hard ware when the SMBu s0 interface enters one of 27 possible states. If interrupts are enabled for the SMBus0 interface, an interrupt request is gener- ated when the SI flag is set. The SI flag must be cleared by software. Important Note: If SI is set to logic 1 while the SCL line is low, the clock-low period of the serial clock will be stretched and the serial transfer is suspended until SI is cleared to logic 0. A high level on SCL is not affected by the setting of the SI flag. The Assert Acknowledge flag (AA, SMB0CN.2) is used to set the level of the SDA line during the acknowl- edge clock cycle on the SCL line. Setting the AA flag to logic 1 will cause an ACK (low level on SDA) to be sent during the acknowledge cycle if the device has been addressed. Setting the AA flag to logic 0 will cause a NACK (high level on SDA) to be sent during acknowledge cycle. After the transmission of a byte in slave mode, the slave can be temporarily removed from the bus by clearing the AA flag. The slave's own address and general ca ll address will be ignored. To resume operation on the bus, the AA flag must be reset to logic 1 to allow the slave's address to be recognized.

242 Rev. 1.2 Setting the SMBus0 Free Timer Enable bit (FTE, SMB0CN.1) to logic 1 enables the timer in SMB0CR. When SCL goes high, the timer in SMB0CR counts up. A timer overflow indica tes a free bus timeout: if SMBus0 is waiting to generate a START, it will do so after this timeout. The bus free period should be less than 50 µs (see Figure 20.9, SMBus0 Clock Rate Register). When the TOE bit in SMB0CN is set to logic 1, Time r 4 is used to detect SCL low timeouts. If Timer 4 is enabled (see Section “24.2. Timer 2, Timer 3, and Timer 4” on page 295), Timer 4 is forced to reload when SCL is high, and forced to count when SCL is low. Wi th Timer 4 enabled and configured to overflow after

Rev. 1.2 243 25 ms (and TOE set), a Timer 4 overflow indicates a SCL low timeout; the Timer 4 interrupt service routine can then be used to reset SMBus0 communication in the event of an SCL low timeout. Figure 20.8. SMB0CN: SMBus0 Control Register Bit7: BUSY: Busy Status Flag. 0: SMBus0 is free. 1: SMBus0 is busy. Bit6: ENSMB: SMBus Enable. This bit enables/disables the SMBus serial interface. 0: SMBus0 disabled. 1: SMBus0 enabled. Bit5: STA: SMBus Start Flag. 0: No START condition is transmitted. 1: When operating as a master, a START condition is transmitted if the bus is free. (If the bus is not free, the START is transmitted after a STOP is received.) If STA is set after one or more bytes have been transmitted or received and before a STOP is received, a repeated START condition is transmitted. Bit4: STO: SMBus Stop Flag. 0: No STOP condition is transmitted. 1: Setting STO to logic 1 causes a STOP condition to be transmitted. When a STOP condi- tion is received, hardware clears STO to logic 0. If both STA and STO are set, a STOP con- dition is transmitted followed by a START condition. In slave mode, setting the STO flag causes SMBus to behave as if a STOP condition was received. Bit3: SI: SMBus Seri al Interrupt Flag. This bit is set by hardware when one of 27 possible SMBus0 states is entered. (Status code 0xF8 does not cause SI to be set.) When the SI interrupt is enabled, setting this bit causes the CPU to vector to the SMBus interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit2: AA: SMBus Assert Acknowledge Flag. This bit defines the type of acknowledge returned during the acknowledge cycle on the SCL line. 0: A "not acknowledge" (high level on SDA) is returned during the acknowledge cycle. 1: An "acknowledge" (low level on SDA) is returned during the acknowledge cycle. Bit1: FTE: SMBus Free Timer Enable Bit. 0: No timeout when SCL is high. 1: Timeout when SCL high time exceeds limit specified by the SMB0CR value. Bit0: TOE: SMBus Timeout Enable Bit. 0: No timeout when SCL is low. 1: Timeout when SCL low time exceeds limit specified by Timer 4, if enabled. R R/W R/W R/W R/W R/W R/W R/W Reset Value BUSY ENSMB STA STO SI AA FTE TOE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: SFR Page: 0xC0

244 Rev. 1.2 20.4.2. Clock Rate Register Figure 20.9. SMB0CR: SMBus0 Clock Rate Register Bits7-0: SMB0CR.[7:0]: SMBu s0 Clock Rate Preset. The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. The timer counts up, and when it rolls over to 0x00, the SCL logic state toggles. The SMB0CR setting should be bounded by the following equation , where SMB0CR is the unsigned 8-bit value in register SMB0CR, and SYSCLK is the system clock frequency in Hz: The resulting SCL signal high and low times are given by the following equations: Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the following equation: R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xCF TLOW 256 SMB 0CR–() SYSCLK⁄= THIGH 258 SMB 0CR–() SYSCLK⁄ 625ns+≅ TBFT 10 256 SMB 0CR–() 1+

Rev. 1.2 245 20.4.3. Data Register The SMBus0 Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software can read or write to this register while the SI flag is set to logic 1; software should not attempt to access the SMB0DAT register when t he SMBus is enabled and the SI flag reads logic 0 since the hardware may be in the process of shifting a byte of data in or out of the register. Data in SMB0DAT is always shifted ou t MSB first. After a byte has been received, the first bit of received data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in. Therefore, SMB0DAT always contains t he last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in SMB0DAT. 20.4.4. Address Register The SMB0ADR Address register holds the slave addre ss for the SMBus0 interface. In slave mode, the seven most-significant bits hold the 7-bit slave address. The least significant bit (Bit0) is used to enable the recognition of the general call address (0x00). If Bit0 is set to logic 1, the general call address will be recog- Figure 20.10. SMB0DAT: SMBus0 Data Register Bits7-0: SMB0DAT: SMBus0 Data. The SMB0DAT register contains a byte of data to be transmitted on the SMBus0 serial inter- face or a byte that has just been received on the SMBus0 serial interface. The CPU can read from or write to this register whenever the SI serial interrupt flag (SMB0CN.3) is set to logic 1. When the SI flag is not set, the system may be in the process of shifting data and the CPU should not attempt to access this register. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xC2

246 Rev. 1.2 nized. Otherwise, the general call address is ignor ed. The contents of this register are ignored when SMBus0 is operating in master mode. 20.4.5. Status Register The SMB0STA Status register holds an 8-bit status c ode indicating the current state of the SMBus0 inter- face. There are 28 possible SMBus0 states, each wit h a corresponding unique status code. The five most significant bits of the status code vary while the three least-significant bits of a valid status code are fixed at zero when SI = ‘1’. Therefore, all possible status codes are multiples of eight. This facilitates the use of sta- tus codes in software as an index used to branch to appropriate service routines (allowing 8 bytes of code to service the state or jump to a more extensive service routine). Figure 20.11. SMB0ADR: SMBus0 Address Register Bits7-1: SLV6-SLV0: SMBus0 Slave Address. These bits are loaded with the 7-bit slave address to which SMBus0 will respond when oper- ating as a slave transmitter or slave receiver. SLV6 is the most significant bit of the address and corresponds to the first bit of the address byte received. Bit0: GC: General Call Address Enable. This bit is used to enable general call address (0x00) recognition. 0: General call address is ignored. 1: General call address is recognized. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SLV6 SLV5 SLV4 SLV3 SLV2 SLV1 SLV0 GC 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xC3

Rev. 1.2 247 For the purposes of user software, the contents of the SMB0STA register is only defined when the SI flag is logic 1. Software should never write to the SMB0STA register; doing so will yield indeterminate results. The 28 SMBus0 states, along with their corresponding status codes, are given in Table 1.1. Figure 20.12. SMB0STA: SMBus0 Status Register Bits7-3: STA7-STA3: SMBus0 Status Code. These bits contain the SMBus0 Status Code. There are 28 possible status codes; each sta- tus code corresponds to a single SMBus state. A valid status code is present in SMB0STA when the SI flag (SMB0CN.3) is set to logic 1. The content of SMB0STA is not defined when the SI flag is logic 0. Writing to the SMB0STA register at any time will yield indeterminate results. Bits2-0: STA2-STA0: The three least significant bi ts of SMB0STA are always read as logic 0 when the SI flag is logic 1. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value STA7 STA6 STA5 STA4 STA3 STA2 STA1 STA0 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xC1

248 Rev. 1.2 Table 20.1. SMB0STA Status Codes and States Mode Status Code SMBus State Typical Action MT/ MR 0x08 START condition transmitted. Load SMB0DAT with Slave Address + R/W. Clear STA. 0x10 Repeated START condition transmitted. Load SMB0DAT with Slave Address + R/W. Clear STA. Master Transmitter 0x18 Slave Address + W transmitted. ACK received. Load SMB0DAT with data to be transmit- ted. 0x20 Slave Address + W transmitted. NACK received. Acknowledge poll to retry. Set STO + STA. 0x28 Data byte transmitted. ACK received. 1) Load SMB0DAT with next byte, OR 2) Set STO, OR 3) Clear STO then set STA for repeated START. 0x30 Data byte transmitted. NACK received. 1) Retry transfer OR 2) Set STO. 0x38 Arbitration Lost. Save current data. Master Receiver 0x40 Slave Address + R transmitted. ACK received. If only receiving one byte, clear AA (send NACK after received byte). Wait for received data. 0x48 Slave Address + R transmitted. NACK received. Acknowledge poll to retry. Set STO + STA. 0x50 Data byte received. ACK transmitted. Read SMB0DAT. Wait for next byte. If next byte is last byte, clear AA. 0x58 Data byte received. NACK transmitted. Set STO.

Rev. 1.2 249 Slave Receiver 0x60 Own slave address + W received. ACK trans- mitted. Wait for data. 0x68 Arbitration lost in sending SLA + R/W as mas- ter. Own address + W received. ACK transmit- ted. Save current data for retry when bus is free. Wait for data. 0x70 General call address received. ACK transmit- ted. Wait for data. 0x78 Arbitration lost in sending SLA + R/W as mas- ter. General call address received. ACK trans- mitted. Save current data for retry when bus is free. 0x80 Data byte received. ACK transmitted. Read SMB0DAT. Wait for next byte or STOP . 0x88 Data byte received. NACK transmitted. Set STO to reset SMBus. 0x90 Data byte received after general call address. ACK transmitted. Read SMB0DAT. Wait for next byte or STOP . 0x98 Data byte received after general call address. NACK transmitted. Set STO to reset SMBus. 0xA0 STOP or repeated START received. No action necessary. Slave Transmitter 0xA8 Own address + R received. ACK transmitted. Load SMB0DAT with data to transmit. 0xB0 Arbitration lost in transmitting SLA + R/W as master. Own address + R received. ACK transmitted. Save current data for retry when bus is free. Load SMB0DAT with data to trans- mit. 0xB8 Data byte transmitted. ACK received. Load SMB0DAT with data to transmit. 0xC0 Data byte transmitted. NACK received. Wait for STOP. 0xC8 Last data byte transmitted (AA=0). ACK received. Set STO to reset SMBus. Slave 0xD0 SCL Clock High Timer per SMB0CR timed out Set STO to reset SMBus. All 0x00 Bus Error (illegal START or STOP) Set STO to reset SMBus. 0xF8 Idle State does not set SI. Table 20.1. SMB0STA Status Codes and States Mode Status Code SMBus State Typical Action

250 Rev. 1.2

Rev. 1.2 251 21. Enhanced Serial Peri pheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) pr ovides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen- eral purpose port I/O pins can be used to select multiple slave devices in master mode. Figure 21.1. SPI Block Diagram SFR Bus Data Path Control SFR Bus Write SPI0DAT Receive Data Buffer SPI0DAT 01234567 Shift Register SPI CONTROL LOGIC SPI0CKR SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 SPI0CFG SPI0CN Pin Interface Control Pin Control Logic C R O S S B A R Port I/O Read SPI0DAT SPI IRQ Tx Data Rx Data SCK MOSI MISO NSS Transmit Data Buffer Clock Divide Logic SYSCLK CKPHA CKPOL SLVSEL NSSMD1 NSSMD0 SPIBSY MSTEN NSSIN SRMT RXBMT SPIF WCOL MODF RXOVRN TXBMT SPIEN

252 Rev. 1.2 21.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 21.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output fr om a master device and an input to slave devices. It is used to serially transfer data from the master to th e slave. This signal is an output when SPI0 is operat- ing as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode. 21.1.2. Master In, Slave Out (MISO) The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operat- ing as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is not select ed. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register. 21.1.3. Serial Clock (SCK) The serial clock (SCK) signal is an output from the ma ster device and an input to slave devices. It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 gen- erates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is not selected (NSS = 1) in 4-wire slave mode. 21.1.4. Slave Select (NSS) The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register. There are three possible modes that can be selected with these bits: 1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is disabled. When operating as a slave de vice, SPI0 is always sele cted in 3-wire mode. Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-point communication between a master and one slave. 2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Ma ster Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can be used on the same SPI bus. 3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 o perates in 4-wire mode, and NSS is enabled as an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should only be used when operating SPI0 as a master device. See Figure 21.2, Figure 21.3, and Figure 21.4 for typica l connection diagrams of the various operational modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device. See Section “ 18. Port Input/Output” on page 203 for general purpose port I/O and crossbar information.

Rev. 1.2 253 21.2. SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data serially on the MOSI line while provid ing the serial clock on SCK. The SPI F (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabl ed, an interrupt request is generated when the SPIF flag is set. While the SPI0 master transf ers data to a slave on the MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The data byte received from the slave is transferred MSB- first into the master's shift register. When a byte is fully shifted into the register, it is moved to the re ceive buffer where it can be read by the processor by reading SPI0DAT. When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is used to disable the master SPI0 when another ma ster is accessing the bus. When NSS is pulled low in this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) ar e set to 0 to disable the SPI master device, and a Mode Fault is generate d (MODF, SPI0CN.5 = 1). Mode Fault will gen erate an interrupt if enabled. SPI0 must be manually re-enabled in software under these circumstances. In multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. In multi-mas- ter mode, slave devices can be addressed individua lly (if needed) using general-purpose I/O pins. Figure 21.2 shows a connection diagram between two master devices in multiple-master mode. 3-wire single-master mode is active when NSSMD1 (S PI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 21.3 shows a connection diagram between a master device in 3-wire master mode and a slave device. 4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value of NSS is controlled (in software) with the bit N SSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 21.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices.

Rev. 1.2 255 21.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a ma ster device controlling the SCK sig- nal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift reg- ister, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double- buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. When the sh ift register already contains data, the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or current) SPI transfer. When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0, and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS sig- nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer. Figure 21.4 shows a connection diagram between tw o slave devices in 4-wire slave mode and a master device. 3-wire slave mode is active when NSSMD1 (SPI0CN. 3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of uniquely addressing the device in 3-wire slave mode , SPI0 must be the only slav e device present on the bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. Th e bit counter can only be reset by disabling and re- enabling SPI0 with the SPIEN bit. Figure 21.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 21.4. SPI0 Interrupt Sources When SPI0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: Note that all of the following bits must be cleared by software. 1. The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can occur in all SPI0 modes. 2. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0 modes. 3. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus. 4. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost.

256 Rev. 1.2 21.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0C FG). The CKPHA bit ( SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave devices must be config ured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN bit, SPI0 CN.0) when changing the clock phase or polarity. The clock and data line relationships for master mode are shown in Figure 21.5. For slave mode, the clock and data relationships are shown in Figure 21.6 and Figure 2 1.7. Note that CKPHA must be set to ‘0’ on both the master and slave SPI when communicating betw een two of the following devices: C8051F04x, C8051F06x, C8051F12x, C8051F31x, C8051F32x, and C8051F33x The SPI0 Clock Rate Register (SPI0CKR) as shown in Figure 21.10 controls the master mode serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock. SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO/MOSI NSS (Must Remain High in Multi-Master Mode) Figure 21.5. Master Mode Data/Clock Timing

258 Rev. 1.2 21.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CF G Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. Figure 21.8. SPI0CFG: SPI0 Configuration Register Bit 7: SPIBSY: SPI Busy (read only). This bit is set to logic 1 when a SPI transfer is in progress (Master or slave Mode). Bit 6: MSTEN: Master Mode Enable. 0: Disable master mode. Operate in slave mode. 1: Enable master mode. Operate as a master. Bit 5: CKPHA: SPI0 Clock Phase. This bit controls the SPI0 clock phase. 0: Data centered on first edge of SCK period. 1: Data centered on second edge of SCK period.† Bit 4: CKPOL: SPI0 Clock Polarity. This bit controls the SPI0 clock polarity. 0: SCK line low in idle state. 1: SCK line high in idle state. Bit 3: SLVSEL: Slave Selected Flag (read only). This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input. Bit 2: NSSIN: NSS Instantaneous Pin Input (read only). This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read. This input is not de-glitched. Bit 1: SRMT: Shift Register Empty (Valid in Slave Mode, read only). This bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK. NOTE: SRMT = 1 when in Master Mode. Bit 0: RXBMT: Receive Buffer Empty (Valid in Slave Mode, read only). This bit will be set to logic 1 when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been read, this bit will return to logic 0. NOTE: RXBMT = 1 when in Master Mode. †In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device. See Table 21.1 for timing parameters. R R/W R/W R/W R R R R Reset Value SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0x9A

Rev. 1.2 259 Figure 21.9. SPI0CN: SPI0 Control Register Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software. Bit 6: WCOL: Write Collision Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to the SPI0 data register was attempted while a data transfer was in progress. It must be cleared by software. Bit 5: MODF: Mode Fault Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not auto- matically cleared by hardware. It must be cleared by software. Bit 4: RXOVRN: Receive Overru n Flag (Slave Mode only). This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must be cleared by software. Bits 3-2: NSSMD1-NSSMD0 : Slave Select Mode. Selects between the following NSS operation modes: (See Section “21.2. SPI0 Master Mode Operation” on page 253 and Section “21.3. SPI0 Slave Mode Operation” on page 255). 00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin. 01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device. 1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will assume the value of NSSMD0. Bit 1: TXBMT: Transmit Buffer Empty. This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. Bit 0: SPIEN: SPI0 Enable. This bit enables/disables the SPI. 0: SPI disabled. 1: SPI enabled. R / WR / WR / WR / WR / WR / W R R / W R e s e t V a l u e SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 TXBMT SPIEN 00000110 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: SFR Page: 0xF8

260 Rev. 1.2 Figure 21.10. SPI0CKR: SPI0 Clock Rate Register Bits 7-0: SCR7-SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register. for 0 <= SPI0CKR <= 255 Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04, R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0x9D fSCK 2000000 fSCK 200kHz= fSCK SYSCLK

Rev. 1.2 261 Figure 21.11. SPI0DAT: SPI0 Data Register Bits 7-0: SPI0DAT: SPI0 Transmit and Receive Data. The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT places the data into the transmit buffer and initiates a transfer when in Master Mode. A read of SPI0DAT returns the contents of the receive buffer. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0x9B

264 Rev. 1.2 Table 21.1. SPI Slave Timing Parameters Parameter Description Min Max Units Master Mode Timing† (See Figure 21.12 and Figure 21.13) TMCKH SCK High Time 1*T SYSCLK ns TMCKL SCK Low Time 1*T SYSCLK ns TMIS MISO Valid to SCK Shift Edge 1*T SYSCLK + ns TMIH SCK Shift Edge to MISO Change 0 ns Slave Mode Timing† (See Figure 21.14 and Figure 21.15) TSE NSS Falling to First SCK Edge 2*T SYSCLK ns TSD Last SCK Edge to NSS Rising 2*T SYSCLK ns TSEZ NSS Falling to MISO Valid 4*T SYSCLK ns TSDZ NSS Rising to MISO High-Z 4*T SYSCLK ns TCKH SCK High Time 5*T SYSCLK ns TCKL SCK Low Time 5*T SYSCLK ns TSIS MOSI Valid to SCK Sample Edge 2*T SYSCLK ns TSIH SCK Sample Edge to MOSI Change 2*T SYSCLK ns TSOH SCK Shift Edge to MISO Change 4*T SYSCLK ns TSLH Last SCK Edge to MISO Change (CKPHA = 1 ONLY) 6*TSYSCLK 8*TSYSCLK ns †TSYSCLK is equal to one period of the device system clock (SYSCLK).

Rev. 1.2 265 22. UART0 UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0 may operate in full-duplex asynchronous or half-d uplex synchronous modes, and mutiproccessor commu- nication is fully supported. Receive data is buffered in a holding register, allowing UART0 to start reception of a second incoming data byte before software has finished reading the previ ous data byte. A Receive Overrun bit indicates when new received data is latc hed into the receive buffer before the previously received byte has been read. UART0 is accessed via its associated SFRs, Serial Control (SCON0) and Serial Data Buffer (SBUF0). The single SBUF0 location provides access to both tr ansmit and receive registers. Reading SCON0 accesses the Receive register and writing SCON0 accesses the Transmit register. UART0 may be operated in polled or interrupt mode. UART0 has two sources of interrupts: a Transmit Interrupt flag, TI0 (SCON0.1 ) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI0 (SCON0.0) set when reception of a data byte is complete. UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine; they must be cleared manually by soft- ware. This allows software to determine the cause of the UART0 in terrupt (transmit complete or receive complete). Figure 22.1. UART0 Block Diagram Tx Control Tx Clock Tx IRQ Zero Detector Send Shift SET QD CLR Stop Bit Gen. TB80 Start Data Write to SBUF0 CrossbarTX0 Port I/O Serial Port (UART0) Interrupt Rx Control Start Rx Clock Load SBUF 0x1FFShift EN Rx IRQ UART0 Baud Rate Generation Logic SFR Bus Input Shift Register (9 bits) Frame Error Detection SBUF0 Read SBUF0 SFR Bus SADDR0 SADEN0 Match Detect RB80 Load SBUF0 CrossbarRX0 SBUF0 Address Match SCON0 S M T B R B T I R I S M S M R E N SSTA0 T X C O L S T C L K S T C L K S R C L K S R C L K R X O V F E S M O D TI0 RI0

266 Rev. 1.2 22.1. UART0 Operational Modes UART0 provides four operating modes (one synchronous and three asynchronous) selected by setting configuration bits in the SCON0 register. These four modes offer different baud rates and communication protocols. The four modes are summarized in Table 22.1. 22.1.1. Mode 0: Synchronous Mode Mode 0 provides synchronous, half-duplex communicati on. Serial data is transmitted and received on the RX0 pin. The TX0 pin provides the shift clock for both transmit and receive. The MCU must be the master since it generates the shift clock for transmission in both directions (see the interconnect diagram in Figure 22.3). Data transmission begins when an instruction writes a data byte to the SBUF0 register. Eight data bits are transferred LSB first (see the timing diagram in Figure 22.2), and the TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the eighth bit time. Data reception begins when the REN0 Receive Enable bit (SCON0.4) is set to logic 1 and the RI0 Receive In terrupt Flag (SCON0.0) is cleared. One cycle after the eighth bit is shifted in, the RI0 flag is set and rece ption stops until software clears the RI0 bit. An inter- rupt will occur if enabled when either TI0 or RI0 are set. Table 22.1. UART0 Modes Mode Synchronization Baud Clock Data Bits Start/Stop Bits

0 Synchronous SYSCLK / 12 8 None

1 Asynchronous Timer 1, 2, 3, or 4 Overflow 8 1 Start, 1 Stop

2 Asynchronous SYSCLK / 32 or SYSCLK / 64 9 1 Start, 1 Stop

3 Asynchronous Timer 1, 2, 3, or 4 Overflow 9 1 Start, 1 Stop

Rev. 1.2 267 The Mode 0 baud rate is SYSCLK / 12. RX0 is forced to open-drain in Mode 0, and an external pull-up will typically be required. 22.1.2. Mode 1: 8-Bit UART, Variable Baud Rate Mode 1 provides standard asynchronous, full duplex communication using a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted from the TX0 pin and received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2). Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the tran smission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: RI0 must be logic 0, and if SM20 is logic 1, the stop bit must be logic 1. If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 are set. Figure 22.2. UART0 Mode 0 Timing Diagram D1D0 D2 D3 D4 D5 D6 D7RX (data out) MODE 0 TRANSMIT MODE 0 RECEIVE RX (data in) D1 D2 D3 D4 D5 D6 D7 TX (clk out) TX (clk out) Figure 22.3. UART0 Mode 0 Interconnect Shift Reg. CLK C8051Fxxx RX TX DATA

8 Extra Outputs

Figure 22.4. UART0 Mode 1 Timing Diagram D1D0 D2 D3 D4 D5 D6 D7 START BIT MARK STOP BIT BIT TIMES BIT SAMPLING SPACE

268 Rev. 1.2 The baud rate generated in Mode 1 is a function of timer overflow. UART0 can use Timer 1 operating in 8- Bit Auto-Reload Mode, or Timer 2, 3, or 4 operating in Auto-reload Mode to generate the baud rate (note that the TX and RX clocks are selected separately). On each timer overflow event (a rollover from all ones - (0xFF for Timer 1, 0xFFFF for Timer 2, 3, or 4) - to zero) a clock is sent to the baud rate logic. Timers 1, 2, 3, or 4 are selected as the baud rate source with bits in the SSTA0 register (see Figure 22.9). The transmit baud rate clock is selected using the S0TCLK1 and S0TCLK0 bits, and the receive baud rate clock is selected using the S0RCLK1 and S0RCLK0 bits. When Timer 1 is selected as a baud rate source, the SMOD0 bit (SSTA0.4) selects whether or not to divide the Timer 1 overflow rate by two. On reset, the SMOD0 bit is logic 0, thus selecting the lower speed baud rate by default. The SMOD0 bit affects the baud rate generated by Timer 1 as shown in Equation 22.1. The Timer 1 overflow rate is determined by the Timer 1 clock source (T1CLK) and reload value (TH1). The frequency of T1CLK is se lected as described in Section “24.1. Timer 0 and Timer 1” on page 287 . The Timer 1 overflow rate is calculated as shown in Equation 22.2. When Timers 2, 3, or 4 are selected as a baud rate source, the baud rate is generated as shown in Equation 22.3. The overflow rate for Timer 2, 3, or 4 is determin ed by the clock source for the timer (TnCLK) and the 16- bit reload value stored in the RCAPn register (n = 2, 3, or 4), as shown in Equation 22.4. Equation 22.1. Mode 1 Baud Rate using Timer 1 Mode1_BaudRate 1 32 ⁄ Timer1_OverflowRate⋅= When SMOD0 = 0: Mode1_BaudRate 1 16 ⁄ Timer1_OverflowRate⋅= When SMOD0 = 1: Equation 22.2. Timer 1 Overflow Rate Timer1_OverflowRate T1CLK 256 TH1 –()⁄= Equation 22.3. Mode 1 Baud Rate using Timer 2, 3, or 4 Mode1_BaudRate 1 16 ⁄ Timer234_OverflowRate⋅= Equation 22.4. Timer 2, 3, or 4 Overflow Rate Timer234_OverflowRate TnCLK 65536 RCAPn–()⁄=

Rev. 1.2 269 22.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth da ta bit, and a stop bit. Mode 2 supports multiprocessor communications and hardware address recognition (see Section 22.2). On transmit, the ninth data bit is determined by the value in TB80 (SCON0.3). It can be assigned the value of the parity flag P in the PSW or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and the stop bit is ignored. Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the tran smission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if RI0 is logic 0 and one of the following requirements are met: 1. SM20 is logic 0 2. SM20 is logic 1, the received 9th bit is l ogic 1, and the received ad dress matches the UART0 address as described in Section 22.2. If the above conditions are satisfied, the eight bits of data are stored in SBUF0, the ninth bit is stored in RB80 and the RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 are set. The baud rate in Mode 2 is either SYSCLK / 32 or SYSCLK / 64, according to the value of the SMOD0 bit in register SSTA0. Equation 22.5. Mode 2 Baud Rate BaudRate 2SMOD 0 SYSCLK ×= Figure 22.5. UART0 Modes 2 and 3 Timing Diagram D1D0 D2 D3 D4 D5 D6 D7 START BIT MARK STOP BIT BIT TIMES BIT SAMPLING SPACE

270 Rev. 1.2 22.1.4. Mode 3: 9-Bit UART, Variable Baud Rate Mode 3 uses the Mode 2 transmission protocol with the Mode 1 baud ra te generation. Mode 3 operation transmits 11 bits: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The baud rate is derived from Timer 1 or Timer 2, 3, or 4 overfl ows, as defined by Equation 22.1 and Equation 22.3. Multiprocessor communications and hardware address recognition are supported, as described in Section 22.2. Figure 22.6. UART0 Modes 1, 2, and 3 Interconnect Diagram OR RS-232 C8051Fxxx RS-232 LEVEL XLTR TX RX C8051Fxxx RX TX MCU RX TX

Rev. 1.2 271 22.2. Multiprocessor Communications Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit and the built-in UART0 address recognition hardware. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the tar- get(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. UART0 will recognize as “v alid” (i.e., capable of causing an interrupt) two types of addresses: (1) a masked address and (2) a broadcast address at any given time . Both are described below. 22.2.1. Configuration of a Masked Address The UART0 address is configured via two SFRs: SA DDR0 (Serial Address) and SADEN0 (Serial Address Enable). SADEN0 sets the bit mask for the address he ld in SADDR0: bits set to logic 1 in SADEN0 corre- spond to bits in SADDR0 that are checked against the received address byte; bits set to logic 0 in SADEN0 correspond to “don’t care” bits in SADDR0. Setting the SM20 bit (SCON0.5) configures UART0 such that when a stop bit is received, UART0 will gen- erate an interrupt only if the ninth bit is logic 1 (RB80 = ‘1’) and the received data byte matches the UART0 slave address. Following th e received address interr upt, the slave will clear it s SM20 bit to enable inter- rupts on the reception of the following data byte(s). Once the entire message is received, the addressed slave resets its SM20 bit to ignore all transmissions until it receives the next address byte. While SM20 is logic 1, UART0 ignores all bytes that do not match th e UART0 address and include a ninth bit that is logic 22.2.2. Broadcast Addressing Multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The broadcast address is the logical OR of registers SADDR0 and SADEN0, and ‘0’s of the result are treated as “don’t cares”. Typically a broadcast address of 0xFF (hex adecimal) is acknowledged by all slaves, assuming “don’t care” bits as ‘1’s. The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex trans- mission between the original master and slave(s).. Note in the above examples 4, 5, and 6, each slave woul d recognize as “valid” an address of 0xFF as a broadcast address. Also note that examples 4, 5, and 6 uses t he same SADDR0 and SADEN0 register values as shown in the examples 1, 2, and 3 respec tively (slaves #1, 2, and 3). Thus, a master could address each slave device individually using a masked address, and also broadcast to all three slave devices. For example, if a Master were to send an address “11110101”, only slave #1 would recognize the Example 1, SLAVE #1 Example 2, SLAVE #2 Example 3, SLAVE #3 SADDR0 = 00110101 SADDR0 = 00110101 SADDR0 = 00110101 SADEN0 = 00001111 SADEN0 = 11110011 SADEN0 = 11000000 UART0 Address = xxxx0101 UART0 Address = 0011xx01 UART0 Address = 00xxxxxx Example 4, SLAVE #1 Example 5, SLAVE #2 Example 6, SLAVE #3 SADDR0 = 00110101 SADDR0 = 00110101 SADDR0 = 00110101 SADEN0 = 00001111 SADEN0 = 11110011 SADEN0 = 11000000 Broadcast Address = 00111111 Broadcast Address = 11110111 Broadcast Address = 11110101 Where all ZEROES in the Broadcast address are don’t cares.

272 Rev. 1.2 address as valid. If a master were to then send an address of “11111111”, all three slave devices would rec- ognize the address as a valid broadcast address. 22.3. Frame and Transmi ssion Error Detection All Modes: The Transmit Collision bit (T XCOL0 bit in register SCON0) reads ‘1’ if user software writes data to the SBUF0 register while a transmit is in progress. Note that the TXCOL0 bit is also used as the SM20 bit when written by user software. This bit does not generate an interrupt. Modes 1, 2, and 3: The Receive Overrun bit (RXOV0 in register SCON0) reads ‘1’ if a new data byte is latched into the receive buffer before software has read the previous byte. No te that the RXOV0 bit is also used as the SM10 bit when written by user software. The Frame Error bit (FE0 in register SSTA0) reads ‘1’ if an invalid (low) STOP bit is detected. Note that the FE0 bit is also used as the SM00 bit when written by user software. The RXOV0 and FE0 bits do not generate interrupts. Figure 22.7. UART Multi-Processor Mode Interconnect Diagram Master Device Slave Device TXRX RX TX Slave Device RX TX Slave Device RX TX +5V

Rev. 1.2 273 Table 22.2. Oscillator Frequencies for Standard Baud Rates Oscillator frequency (MHz) Divide Fac- tor Timer 1 Reload Value* T i m e r2 ,3 ,o r

4 Reload

Resulting Baud Rate (Hz)** 24.0 208 0xF3 0xFFF3 115200 (115384) 22.1184 192 0xF4 0xFFF4 115200 18.432 160 0xF6 0xFFF6 115200 11.0592 96 0xFA 0xFFFA 115200 3.6864 32 0xFE 0xFFFE 115200 1.8432 16 0xFF 0xFFFF 115200 24.0 832 0xCC 0xFFCC 28800 (28846) 22.1184 768 0xD0 0xFFD0 28800 18.432 640 0xD8 0xFFD8 28800 11.0592 348 0xE8 0xFFE8 28800 3.6864 128 0xF8 0xFFF8 28800 1.8432 64 0xFC 0xFFFC 28800 24.0 2496 0x64 0xFF64 9600 (9615) 22.1184 2304 0x70 0xFF70 9600 18.432 1920 0x88 0xFF88 9600 11.0592 1152 0xB8 0xFFB8 9600 3.6864 384 0xE8 0xFFE8 9600 1.8432 192 0xF4 0xFFF4 9600 * Assumes SMOD0=1 and T1M=1. ** Numbers in parenthesis show the actual baud rate.

274 Rev. 1.2 Figure 22.8. SCON0: UART0 Control Register Bits7-6: SM00-SM10: Serial Port Operation Mode: Write: When written, these bits select the Serial Port Operation Mode as follows: Reading these bits returns the current UART0 mode as defined above. Bit5: SM20: Multiprocesso r Communication Enable. The function of this bit is dependent on the Serial Port Operation Mode. Mode 0: No effect. Mode 1: Checks for valid stop bit. 0: Logic level of stop bit is ignored. 1: RI0 will only be activated if stop bit is logic level 1. Mode 2 and 3: Multiprocessor Communications Enable. 0: Logic level of ninth bit is ignored. 1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1 and the received address matches the UART0 address or the broadcast address. Bit4: REN0: Receive Enable. This bit enables/disables the UART0 receiver. 0: UART0 reception disabled. 1: UART0 reception enabled. Bit3: TB80: Ninth Transmission Bit. The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It is not used in Modes 0 and 1. Set or cleared by software as required. Bit2: RB80: Ninth Receive Bit. The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if SM20 is logic 0, RB80 is assigned the logic level of the received stop bit. RB8 is not used in Mode 0. Bit1: TI0: Transmit Interrupt Flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in Mode 0, or at the beginning of the stop bit in other modes). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. Bit0: RI0: Receive Interrupt Flag. Set by hardware when a byte of data has been received by UART0 (as selected by the SM20 bit). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SM00 SM10 SM20 REN0 TB80 RB80 TI0 RI0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: SFR Page: 0x98 SM00 SM10 Mode 0 0 Mode 0: Synchronous Mode 0 1 Mode 1: 8-Bit UART, Variable Baud Rate 1 0 Mode 2: 9-Bit UART, Fixed Baud Rate 1 1 Mode 3: 9-Bit UART, Variable Baud Rate

Rev. 1.2 275 Figure 22.9. SSTA0: UART0 Status and Clock Selection Register Bit7: FE0: Frame Error Flag. † This flag indicates if an invalid (low) STOP bit is detected. 0: Frame Error has not been detected. 1: Frame Error has been detected. Bit6: RXOV0: Receive Overrun Flag. This flag indicates new data has been latched into the receive buffer before software has read the previous byte. 0: Receive overrun has not been detected. 1: Receive Overrun has been detected. Bit5: TXCOL0: Transmit Collision Flag. This flag indicates user software has written to the SBUF0 register while a transmission is in progress. 0: Transmission Collision has not been detected. 1: Transmission Collision has been detected. Bit4: SMOD0: UART0 Baud Rate Doubler Enable. This bit enables/disables the divide-by-two function of the UART0 baud rate logic for config- urations described in the UART0 section. 0: UART0 baud rate divide-by-two enabled. 1: UART0 baud rate divide-by-two disabled. Bits3-2: UART0 Transmit Baud Rate Clock Selection Bits. Bits1-0: UART0 Receive Baud Rate Clock Selection Bits. † Note: FE0, RXOV0, and TXCOL0 are flags only, and no interrupt is generated by these conditions. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value FE0 RXOV0 TXCOL0 SMOD0 S0TCLK1 S0TCLK0 S0RCLK1 S0RCLK0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0x91 S0TCLK1 S0TCLK0 Serial Transmit Baud Rate Clock Source 0 0 Timer 1 generates UART0 TX Baud Rate 0 1 Timer 2 Overflow generates UART0 TX baud rate 1 0 Timer 3 Overflow generates UART0 TX baud rate 1 1 Timer 4 Overflow generates UART0 TX baud rate S0RCLK1 S0RCLK0 Serial Receive Baud Rate Clock Source 0 0 Timer 1 generates UART0 RX Baud Rate 0 1 Timer 2 Overflow generates UART0 RX baud rate 1 0 Timer 3 Overflow generates UART0 RX baud rate 1 1 Timer 4 Overflow generates UART0 RX baud rate

Rev. 1.2 277 23. UART1 UART1 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “23.1. Enhanced Baud Rate Generation” on page 278). Received data buffering allows UART1 to start reception of a second incoming data byte be fore software has finished reading the previous data byte. UART1 has two associated SFRs: Serial Control Regist er 1 (SCON1) and Serial Data Buffer 1 (SBUF1). The single SBUF1 location provides access to both transmit and receive registers. Reading SBUF1 accesses the buffered Receive register; writing SBUF1 accesses the Transmit register. With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive complete). Figure 23.1. UART1 Block Diagram UART1 Baud Rate Generator RI1 SCON1 RI1 TI1 RB81 TB81 REN1 MCE1 S1MODE Tx Control Tx Clock Send SBUF1 (TX Shift) Start Data Write to SBUF1 CrossbarTX1 Shift Zero Detector Tx IRQ SET QD CLR Stop Bit TB81 SFR Bus Serial Port Interrupt TI1 Port I/O Rx Control Start Rx Clock Load SBUF1Shift 0x1FF RB81 Rx IRQ Input Shift Register (9 bits) Load SBUF1 Read SBUF1 SFR Bus CrossbarRX1 SBUF1 (RX Latch)

278 Rev. 1.2 23.1. Enhanced Baud Rate Generation The UART1 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 23.2), which is not user- accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to begin any time a START is detected, independent of the TX Timer state. Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “24.1.3. Mode 2: 8-bit Counter/ Timer with Auto-Reload” on page 289). The Timer 1 reload value should be set so that overflows will occur at two times the desired baud rate. Note that Timer 1 may be clocked by one of five sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, or the external o scillator clock / 8. For any given Timer 1 clock source, the UART1 baud rate is determined by Equation 23.1. Where T1 CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload value). Timer 1 clock frequency is selected as described in Section “24.1. Timer 0 and Timer 1” on page 287. A quick reference for typical baud rates and system clock frequencies is given in Table 23.1 through Table 23.6. Note that the internal oscillator may still generate the syst em clock when the external oscillator is driving Timer 1 (see Section “24.1. Timer 0 and Timer 1” on page 287 for more details). Figure 23.2. UART1 Baud Rate Logic RX Timer Start Detected Overflow Overflow TH1 TL1 TX Clock2 RX Clock2 Timer 1 UART1 Equation 23.1. UART1 Baud Rate UartBaudRate T1CLK 2---×=

280 Rev. 1.2 23.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB81 (SCON1.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg- ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit goes into RB81 (SCON1.2) and the stop bit is ignored. Data transmission begins when an instruction writes a data byte to the SBUF1 register. The TI1 Transmit Interrupt Flag (SCON1.1) is set at the end of the tran smission (the beginning of the stop-bit time). Data reception can begin any time after the REN1 Receive En able bit (SCON1.4) is set to ‘1’. After the stop bit is received, the data byte will be loaded into the SBUF1 receive register if the following conditions are met: (1) RI1 must be logic 0, and (2) if MCE1 is logic 1, the 9th bit must be logic 1 (when MCE1 is logic 0, the state of the ninth data bit is unimportant). If these co nditions are met, the eight bits of data are stored in SBUF1, the ninth bit is stored in RB81, and the RI1 flag is set to ‘1’. If the above conditions are not met, SBUF1 and RB81 will not be loaded and the RI1 flag will not be set to ‘1’. A UART1 interrupt will occur if enabled when either TI1 or RI1 is set to ‘1’. Figure 23.5. 9-Bit UART Timing Diagram D1D0 D2 D3 D4 D5 D6 D7 START BIT MARK STOP BIT BIT TIMES BIT SAMPLING SPACE

Rev. 1.2 281 23.3. Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. Setting the MCE1 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is received, the UART will generate an interrupt only if the ninth bit is logic one (RB81 = 1) signifying an address byte has been received. In the UART interrupt handler, software should compare the received address with the slave's own assigned 8-bit address. If the addresses match, the slave should clear its MCE1 bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE1 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed slave should reset its MCE1 bit to ignore all transmissions until it receives the next address byte. Multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). Figure 23.6. UART Multi-Processor Mode Interconnect Diagram Master Device Slave Device TXRX RX TX Slave Device RX TX Slave Device RX TX +5V

282 Rev. 1.2 Figure 23.7. SCON1: Serial Port 1 Control Register Bit7: S1MODE: Serial Port 1 Operation Mode. This bit selects the UART1 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. Bit6: UNUSED. Read = 1b . Write = don’t care. Bit5: MCE1: Multiprocessor Communication Enable. The function of this bit is dependent on the Serial Port 0 Operation Mode. S1MODE = 0: Checks for valid stop bit. 0: Logic level of stop bit is ignored. 1: RI1 will only be activated if stop bit is logic level 1. S1MODE = 1: Multiprocessor Communications Enable. 0: Logic level of ninth bit is ignored. 1: RI1 is set and an interrupt is generated only when the ninth bit is logic 1. Bit4: REN1: Receive Enable. This bit enables/disables the UART receiver. 0: UART1 reception disabled. 1: UART1 reception enabled. Bit3: TB81: Ninth Transmission Bit. The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It is not used in 8-bit UART Mode. Set or cleared by software as required. Bit2: RB81: Ninth Receive Bit. RB81 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th data bit in Mode 1. Bit1: TI1: Transmit Interrupt Flag. Set by hardware when a byte of data has been transmitted by UART1 (after the 8th bit in 8- bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART1 interrupt is enabled, setting this bit causes the CPU to vector to the UART1 interrupt service routine. This bit must be cleared manually by software. Bit0: RI1: Receive Interrupt Flag. Set to ‘1’ by hardware when a byte of data has been received by UART1 (set at the STOP bit sampling time). When the UART1 interrupt is enabled, setting this bit to ‘1’ causes the CPU to vector to the UART1 interrupt service routine. This bit must be cleared manually by soft- ware. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value S1MODE - MCE1 REN1 TB81 RB81 TI1 RI1 01000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: SFR Page: 0x98

Rev. 1.2 283 Figure 23.8. SBUF1: Serial (UART1) Port Data Buffer Register Bits7-0: SBUF1[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB). This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF1, it goes to the transmit shift register and is held for serial transmis- sion. Writing a byte to SBUF1 is what initiates the transmission. A read of SBUF1 returns the contents of the receive latch. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0x99

284 Rev. 1.2 Table 23.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator Frequency: 24.5 MHz Target Baud Rate (bps) Baud Rate % Error Oscilla- tor Divide Factor Timer Clock Source SCA1-SCA0 (pre-scale select)† T1M† Timer 1 Reload Value (hex) SYSCLK from Internal Osc. 230400 -0.32% 106 SYSCLK XX 1 0xCB 115200 -0.32% 212 SYSCLK XX 1 0x96 57600 0.15% 426 SYSCLK XX 1 0x2B 28800 -0.32% 848 SYSCLK / 4 01 0 0x96 14400 0.15% 1704 SYSCLK / 12 00 0 0xB9 9600 -0.32% 2544 SYSCLK / 12 00 0 0x96 2400 -0.32% 10176 SYSC LK / 48 10 0 0x96 1200 0.15% 20448 SYSCLK / 48 10 0 0x2B X = Don’t care †SCA1-SCA0 and T1M bit definitions can be found in Section 24.1. Table 23.2. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 25.0 MHz Target Baud Rate (bps) Baud Rate % Error Oscilla- tor Divide Factor Timer Clock Source SCA1-SCA0 (pre-scale select)† T1M† Timer 1 Reload Value (hex) SYSCLK from External Osc. 230400 -0.47% 108 SYSCLK XX 1 0xCA 115200 0.45% 218 SYSCLK XX 1 0x93 57600 -0.01% 434 SYSCLK XX 1 0x27 28800 0.45% 872 SYSCLK / 4 01 0 0x93 14400 -0.01% 1736 SYSCLK / 4 01 0 0x27 9600 0.15% 2608 EXTCLK / 8 11 0 0x5D 2400 0.45% 10464 SYSC LK / 48 10 0 0x93 1200 -0.01% 20832 SYSCLK / 48 10 0 0x27 SYSCLK from Internal Osc. 57600 -0.47% 432 EXTCLK / 8 11 0 0xE5 28800 -0.47% 864 EXTCLK / 8 11 0 0xCA 14400 0.45% 1744 EXTCLK / 8 11 0 0x93 9600 0.15% 2608 EXTCLK / 8 11 0 0x5D X = Don’t care †SCA1-SCA0 and T1M bit definitions can be found in Section 24.1.

Rev. 1.2 285 Table 23.3. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 22.1184 MHz Target Baud Rate (bps) Baud Rate % Error Oscilla- tor Divide Factor Timer Clock Source SCA1-SCA0 (pre-scale select)† T1M† Timer 1 Reload Value (hex) SYSCLK from External Osc. 230400 0.00% 96 SYSCLK XX 1 0xD0 115200 0.00% 192 SYSCLK XX 1 0xA0 57600 0.00% 384 SYSCLK XX 1 0x40 28800 0.00% 768 SYSCLK / 12 00 0 0xE0 14400 0.00% 1536 SYSCLK / 12 00 0 0xC0 9600 0.00% 2304 SYSCLK / 12 00 0 0xA0 2400 0.00% 9216 SYSCLK / 48 10 0 0xA0 1200 0.00% 18432 SYSCLK / 48 10 0 0x40 SYSCLK from Internal Osc. 230400 0.00% 96 EXTCLK / 8 11 0 0xFA 115200 0.00% 192 EXTCLK / 8 11 0 0xF4 57600 0.00% 384 EXTCLK / 8 11 0 0xE8 28800 0.00% 768 EXTCLK / 8 11 0 0xD0 14400 0.00% 1536 EXTCLK / 8 11 0 0xA0 9600 0.00% 2304 EXTCLK / 8 11 0 0x70 X = Don’t care †SCA1-SCA0 and T1M bit definitions can be found in Section 24.1. Table 23.4. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 18.432 MHz Target Baud Rate (bps) Baud Rate % Error Oscilla- tor Divide Factor Timer Clock Source SCA1-SCA0 (pre-scale select)† T1M† Timer 1 Reload Value (hex) SYSCLK from External Osc. 230400 0.00% 80 SYSCLK XX 1 0xD8 115200 0.00% 160 SYSCLK XX 1 0xB0 57600 0.00% 320 SYSCLK XX 1 0x60 28800 0.00% 640 SYSCLK / 4 01 0 0xB0 14400 0.00% 1280 SYSCLK / 4 01 0 0x60 9600 0.00% 1920 SYSCLK / 12 00 0 0xB0 2400 0.00% 7680 SYSCLK / 48 10 0 0xB0 1200 0.00% 15360 SYSCLK / 48 10 0 0x60 SYSCLK from Internal Osc. 230400 0.00% 80 EXTCLK / 8 11 0 0xFB 115200 0.00% 160 EXTCLK / 8 11 0 0xF6 57600 0.00% 320 EXTCLK / 8 11 0 0xEC 28800 0.00% 640 EXTCLK / 8 11 0 0xD8 14400 0.00% 1280 EXTCLK / 8 11 0 0xB0 9600 0.00% 1920 EXTCLK / 8 11 0 0x88 X = Don’t care †SCA1-SCA0 and T1M bit definitions can be found in Section 24.1.

286 Rev. 1.2 Table 23.5. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 11.0592 MHz Target Baud Rate (bps) Baud Rate % Error Oscilla- tor Divide Factor Timer Clock Source SCA1-SCA0 (pre-scale select)† T1M† Timer 1 Reload Value (hex) SYSCLK from External Osc. 230400 0.00% 48 SYSCLK XX 1 0xE8 115200 0.00% 96 SYSCLK XX 1 0xD0 57600 0.00% 192 SYSCLK XX 1 0xA0 28800 0.00% 384 SYSCLK XX 1 0x40 14400 0.00% 768 SYSCLK / 12 00 0 0xE0 9600 0.00% 1152 SYSCLK / 12 00 0 0xD0 2400 0.00% 4608 SYSCLK / 12 00 0 0x40 1200 0.00% 9216 SYSCLK / 48 10 0 0xA0 SYSCLK from Internal Osc. 230400 0.00% 48 EXTCLK / 8 11 0 0xFD 115200 0.00% 96 EXTCLK / 8 11 0 0xFA 57600 0.00% 192 EXTCLK / 8 11 0 0xF4 28800 0.00% 384 EXTCLK / 8 11 0 0xE8 14400 0.00% 768 EXTCLK / 8 11 0 0xD0 9600 0.00% 1152 EXTCLK / 8 11 0 0xB8 X = Don’t care †SCA1-SCA0 and T1M bit definitions can be found in Section 24.1. Table 23.6. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 3.6864 MHz Target Baud Rate (bps) Baud Rate % Error Oscilla- tor Divide Factor Timer Clock Source SCA1-SCA0 (pre-scale select)† T1M† Timer 1 Reload Value (hex) SYSCLK from External Osc. 230400 0.00% 16 SYSCLK XX 1 0xF8 115200 0.00% 32 SYSCLK XX 1 0xF0 57600 0.00% 64 SYSCLK XX 1 0xE0 28800 0.00% 128 SYSCLK XX 1 0xC0 14400 0.00% 256 SYSCLK XX 1 0x80 9600 0.00% 384 SYSCLK XX 1 0x40 2400 0.00% 1536 SYSCLK / 12 00 0 0xC0 1200 0.00% 3072 SYSCLK / 12 00 0 0x80 SYSCLK from Internal Osc. 230400 0.00% 16 EXTCLK / 8 11 0 0xFF 115200 0.00% 32 EXTCLK / 8 11 0 0xFE 57600 0.00% 64 EXTCLK / 8 11 0 0xFC 28800 0.00% 128 EXTCLK / 8 11 0 0xF8 14400 0.00% 256 EXTCLK / 8 11 0 0xF0 9600 0.00% 384 EXTCLK / 8 11 0 0xE8 X = Don’t care †SCA1-SCA0 and T1M bit definitions can be found in Section 24.1.

Rev. 1.2 287 24. Timers Each MCU includes 5 counter/timers: Timer 0 and Timer 1 are 16-bit counter/timers compatible with those found in the standard 8051. Timer 2, Timer 3, and Timer 4 are 16-bit auto-reload and capture counter/tim- ers for use with the ADC’s, DAC’s, square-wave generation, or for general-purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Timers 2, 3, and 4 are identi- cal, and offer not only 16-bit auto -reload and capture, but have the ability to produce a 50% duty-cycle square-wave (toggle output) at an external port pin. Timers 0 and 1 may be clocked by one of five source s, determined by the Timer Mode Select bits (T1M- T0M) and the Clock Scale bits (SCA1-SCA0). The Cl ock Scale bits define a pre-scaled clock by which Timer 0 and/or Timer 1 may be clocked (See Figure 24.6 for pre-scaled clock selection). Timers 0 and 1 can be configured to use either the pre-scaled clock signal or the system clock directly. Timers 2, 3, and 4 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. Timer 0 and Timer 1 may also be operated as counte rs. When functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin. Events with a frequency of up to one-fourth the system clock's frequency can be counted. The input signal need not be periodic, but it should be held at a given logic level for at least two fu ll system clock cycles to ensure the level is properly sampled. 24.1. Timer 0 and Timer 1 Each timer is implemented as a 16-bit register ac cessed as two separate 8-bit SFRs: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Time r Control register (TCON) is used to enable Timer 0 and Timer 1 as well as indicate their status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register ( Section “13.3.5. Interrupt Register Descriptions” on page 154 ); Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register (Section 13.3.5). Both counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1-T0M0 in the Counter/Timer Mode register (TMOD). Both timers can be configured independently. 24.1.1. Mode 0: 13-bit Counter/Timer Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration and operation of Timer 0. However, both timers oper ate identically, and Timer 1 is configured in the same manner as described for Timer 0. The TH0 register holds the eight MSBs of the 13-bit c ounter/timer. TL0 holds the five LSBs in bit positions ignored when reading the TL0 register. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 inter- rupts are enabled. Timer 0 and Timer 1 Modes: Timer 2, 3, and 4 Modes: 13-bit counter/timer 16-bit counter/timer with auto-reload 16-bit counter/timer 16-bit counter/timer with capture 8-bit counter/timer with auto-reload Toggle Output Two 8-bit counter/timers (Timer 0 only)

288 Rev. 1.2 The C/T0 bit (TMOD.2) selects the counter/timer's cloc k source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T 0) increment the timer register (Refer to Section “18.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 205 for information on selecting and configuring external I/O pins). Clearing C/T select s the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON (see Figure 24.6). Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal /INT0 is logic-level 1. Setting GATE0 to ‘1’ allows the timer to be controlled by the external input signal / INT0 (see Section “13.3.5. Interrupt Register Descriptions” on page 154), facilitating pulse width measure- ments. Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial value before the timer is enabled. TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The input signal /INT1 is used with Timer 1. TR0 GATE0 /INT0 Counter/Timer

0 X X Disabled

111 E n a b l e d

X = Don't Care Figure 24.1. T0 Mode 0 Block Diagram TCLK TL0 (5 bits) TH0 (8 bits) TCON TF0 TR0 TR1 TF1 IE1 IT1 IE0 IT0 Interrupt TR0 SYSCLK Pre-scaled Clock CKCON S C A S C A T M T M TMOD T M T M C T G A T E G A T E C T T M T M GATE0 /INT0 Crossbar

Rev. 1.2 289 24.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except th at the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0. 24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 or Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from 0xFF to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be cor- rect. When in Mode 2, Timer 1 operates identically to Timer 0. Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is low. Figure 24.2. T0 Mode 2 Block Diagram TCLK TMOD T M T M C T G A T E G A T E C T T M T M TCON TF0 TR0 TR1 TF1 IE1 IT1 IE0 IT0 InterruptTL0 (8 bits) ReloadTH0 (8 bits) 1SYSCLK Pre-scaled Clock CKCON S C A S C A T M T M TR0 GATE0 /INT0 Crossbar

290 Rev. 1.2 24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/ timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use eit her the system clock or an external input si gnal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the Timer 1 run control bit TR1. TH0 sets the Timer 1 over flow flag TF1 on overflow and thus controls the Timer 1 interrupt. Timer 1 is inactive in Mode 3. When Timer 0 is operat ing in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used to generate baud ra tes for the SMBus and/or UART, and/or initiate ADC conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode set- tings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for Mode 3. Figure 24.3. T0 Mode 3 Block Diagram TL0 (8 bits) TMOD TCON TF0 TR0 TR1 TF1 IE1 IT1 IE0 IT0 Interrupt Interrupt SYSCLK Pre-scaled Clock TR1 TH0 (8 bits) CKCON S C A S C A T M T M T M T M C T G A T E G A T E C T T M T M TR0 GATE0 /INT0 Crossbar

Rev. 1.2 291 Figure 24.4. TCON: Timer Control Register Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow detected. 1: Timer 1 has overflowed. Bit6: TR1: Timer 1 Run Control. 0: Timer 1 disabled. 1: Timer 1 enabled. Bit5: TF0: Timer 0 Overflow Flag. Set by hardware when Timer 0 overflows. This flag can be cleared by software but is auto- matically cleared when the CPU vectors to the Timer 0 interrupt service routine. 0: No Timer 0 overflow detected. 1: Timer 0 has overflowed. Bit4: TR0: Timer 0 Run Control. 0: Timer 0 disabled. 1: Timer 0 enabled. Bit3: IE1: External Interrupt 1. This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Inter- rupt 1 service routine if IT1 = 1. This flag is the inverse of the /INT1 signal. Bit2: IT1: Interrupt 1 Type Select. This bit selects whether the configured /INT1 interrupt will be falling-edge sensitive or active-low. 0: /INT1 is level triggered, active-low. 1: /INT1 is edge triggered, falling-edge. Bit1: IE0: External Interrupt 0. This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Inter- rupt 0 service routine if IT0 = 1. This flag is the inverse of the /INT0 signal. Bit0: IT0: Interrupt 0 Type Select. This bit selects whether the configured /INT0 interrupt will be falling-edge sensitive or active-low. 0: /INT0 is level triggered, active logic-low. 1: /INT0 is edge triggered, falling-edge. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: SFR Page: 0x88

292 Rev. 1.2 Figure 24.5. TMOD: Timer Mode Register Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 = logic 1. Bit6: C/T1: Counter/Timer 1 Select. 0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4). 1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin (T1). Bits5-4: T1M1-T1M0: Timer 1 Mode Select. These bits select the Timer 1 operation mode. Bit3: GATE0: Timer 0 Gate Control. 0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level. 1: Timer 0 enabled only when TR0 = 1 AND /INT0 = logic 1. Bit2: C/T0: Counter/Timer Select. 0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3). 1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin (T0). Bits1-0: T0M1-T0M0: Timer 0 Mode Select. These bits select the Timer 0 operation mode. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value GATE1 C/T1 T1M1 T1M0 GATE0 C/T0 T0M1 T0M0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0x89 T1M1 T1M0 Mode 0 0 Mode 0: 13-bit counter/timer 0 1 Mode 1: 16-bit counter/timer

10 Mode 2: 8-bit counter/timer with auto-

1 1 Mode 3: Timer 1 inactive T0M1 T0M0 Mode 0 0 Mode 0: 13-bit counter/timer 0 1 Mode 1: 16-bit counter/timer 1 1 Mode 3: Two 8-bit counter/timers

Rev. 1.2 293 Figure 24.6. CKCON: Clock Control Register Bits7-5: UNUSED. Read = 000b, Write = don’t care. Bit4: T1M: Timer 1 Clock Select. This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1. 0: Timer 1 uses the clock defined by the prescale bits, SCA1-SCA0. 1: Timer 1 uses the system clock. Bit3: T0M: Timer 0 Clock Select. This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to logic 1. 0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0. 1: Counter/Timer 0 uses the system clock. Bit2: UNUSED. Read = 0b, Write = don’t care. Bits1-0: SCA1-SCA0: Ti mer 0/1 Prescale Bits These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured to use prescaled clock inputs. †Note: External clock divided by 8 is synchronized with the system clock, and external clock must be less than or equal to the system clock frequency to operate the timer in this mode. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - T1M T0M - SCA1 SCA0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0x8E SCA1 SCA0 Prescaled Clock 0 0 System clock divided by 12 0 1 System clock divided by 4 1 0 System clock divided by 48 1 1 External clock divided by 8†

Rev. 1.2 295 24.2. Timer 2, Timer 3, and Timer 4 Timers 2, 3, and 4 are 16-bit counter/timers, each formed by two 8-bit SFRs: TMRnL (low byte) and TMRnH (high byte) where n = 2, 3, and 4 for timers 2, 3, and 4 respectively. These timers feature auto- reload, capture, and togg le output modes with the ability to count up or down. Captur e Mode and Auto- reload mode are selected using bits in the Timer 2, 3, and 4 Control registers (TMRnCN). Toggle output mode is selected using the Timer 2, 3, and 4 Configuration registers (TMRnCF). These timers may also be used to generate a square-wave at an external pin. Timers 2, 3, and 4 can use either the system clock (divided by one, two, or twelve), external clock (divi ded by eight) or transitions on an external input pin as its clock source. Timer 2 and 3 can be used to start an ADC Data Conversion and Timers 2, 3, and 4 can schedule DAC outputs. Timers 1, 2, 3, or 4 may be used to generate baud rates for UART 0. Only Timer 1 can be used to generate baud rates for UART 1. The Counter/Timer Select bit C/Tn bit (TMRnCN.1) conf igures the peripheral as a counter or timer. Clear- ing C/Tn configures the Timer to be in a timer mode (i .e., the selected timer clock source as the input for the timer). When C/Tn is set to 1, the timer is configured as a counter (i.e., high-to-low transitions at the Tn input pin increment (or decrement) the counter/timer register. Refer to Section “18.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 205 for information on selecting and configuring external I/O pins for digital peripherals, such as the Tn pin. Timer 2, 3, and 4 can use either SYSCLK, SYSCLK divided by 2, SYSCLK divided by 12, an external clock divided by 8, or high-to-low transitions on the Tn input pin as its clock source when operating in Counter/ Timer with Capture mode. Clearing the C/Tn bit (TnCON.1) selects the system clock/external clock as the input for the timer. The Timer Clock Select bits TnM0 and TnM1 in TMRnCF can be used to select the sys- tem clock undivided, system clock divided by two, syst em clock divided by 12, or an external clock pro- vided at the XTAL1/XTAL2 pins divided by 8 (see Figure 24.14). When C/Tn is set to logic 1, a high-to-low transition at the Tn input pin increments the counter/timer register (i.e., configured as a counter). 24.2.1. Configuring Timer 2, 3, and 4 to Count Down Timers 2, 3, and 4 have the abilit y to count down. When the timer’s respective Decrement Enable Bit (DCENn) in the Timer Configuration Register (See Figure 24.14) is set to ‘1’, the timer can then count up or down. When DCENn = 1, the direction of the timer’s count is controlled by the TnEX pin’s logic level. When TnEX = 1, the counter/timer will count up; when TnEX = 0, the counter/timer will count down. To use this feature, TnEX must be enabled in the digital crossbar and configured as a digital input. Note: When DCENn = 1, other functions of the TnEX input (i.e., capture and auto-reload) are not available. TnEX will only control the direction of the timer when DCENn = 1.

296 Rev. 1.2 24.2.2. Capture Mode In Capture Mode, Timer 2, 3, and 4 will operate as a 16-bit counter/time r with capture facility. When the Timer External Enable bit (found in the TMRnCN register) is set to ‘1’, a high-to-low transition on the TnEX input pin causes the 16-bit value in the associated timer (THn, TLn) to be loaded into the capture registers (RCAPnH, RCAPnL). If a capture is triggered in the counter/timer, the Timer External Flag (TMRnCN.6) will be set to ‘1’ and an interrupt will occur if the interrupt is enabled. See Section “13.3. Interrupt Handler” on page 151 for further information concerning the configuration of interrupt sources. As the 16-bit timer register increments and overfl ows TMRnH:TMRnL, the TFn Timer Overflow/Underflow Flag (TMRnCN.7) is set to ‘1’ and an interrupt will occur if the interrupt is enabled. The timer can be config- ured to count down by setting th e Decrement Enable Bit (TMRnCF.0) to ‘1’. This will cause the timer to decrement with every timer clock/count event and underflow when the timer transitions from 0x0000 to 0xFFFF. Just as in overflows, the Overflow/Underflow Flag (TFn) will be set to ‘1’, and an interrupt will occur if enabled. Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RLn (TMRnCN.0) and the Timer 2, 3, and 4 Run Control bit TRn (TnCON.2) to logic 1. The Timer 2, 3, and 4 respective External Enable EXENn (TnCON.3) must also be set to logic 1 to enable a captures. If EXENn is cleared, transitions on TnEX will be ignored. TMRnL TMRnH TRn TCLK Interrupt TMRnCNEXFn EXENn TRn C/Tn CP/RLn TFn SYSCLK 12 TMRnCF D C E N T n O E T O G n T n M T n M Toggle Logic Tn (Port Pin) EXENn CrossbarTnEX RCAPnL RCAPnH 0xFF 0xFF 8External Clock (XTAL1) Tn Crossbar OVF Capture Figure 24.11. T2, 3, and 4 Capture Mode Block Diagram

Rev. 1.2 297 24.2.3. Auto-Reload Mode In Auto-Reload Mode, the counter/timer can be configured to count up or down and cause an interrupt/flag to occur upon an overflow/underflow event. When counting up, the counter/timer will set its overflow/under- flow flag (TFn) and cause an interrupt (if enabled) upon overflow/underflow, and the values in the Reload/ Capture Registers (RCAPnH and RCAPnL) are loaded into the timer and the timer is restarted. When the Timer External Enable Bit (EXENn) bit is set to ‘1’ and the Decrement Enable Bit (DCENn) is ‘0’, a falling edge (‘1’-to-‘0’ transition) on the TnEX pin (configured as an input in the digital crossbar) will cause a timer reload (in addition to timer overflows causing auto-rel oads). When DCENn is set to ‘1’, the state of the TnEX pin controls whether the counter/timer counts up (increments) or down (decrements), and will not cause an auto-reload or interrupt event. See Section 24.2.1 for information concerning configuration of a timer to count down. When counting down, the counter/timer will set its overflow/underflow flag (TFn) and cause an interrupt (if enabled) when the value in the timer (TMRnH and TM RnL registers) matches the 16-bit value in the Reload/Capture Registers (RCAPnH and RCAPnL). This is considered an underflow event, and will cause the timer to load the value 0xFFFF. The timer is automatically restarted when an underflow occurs. Counter/Timer with Auto-Reload mode is selected by clearing the CP/RLn bit. Setting TRn to logic 1 enables and starts the timer. In Auto-Reload Mode, the External Flag (EXFn) togg les upon every overflow or underflow and does not cause an interrupt. The EXFn flag can be thought of as the most significant bit (MSB) of a 17-bit counter. TMRnL TMRnH TRn TCLK Reload InterruptEXENn CrossbarTnEX TMRnCNEXFn EXENn TRn C/Tn CP/RLn TFn SYSCLK 12 TMRnCF D C E N T n O E T O G n T n M T n M Toggle Logic Tn (Port Pin) RCAPnL RCAPnH 0xFF 0xFF OVF 8External Clock (XTAL1) Tn Crossbar SMBus (Timer 4 Only) Figure 24.12. T2, 3, and 4 Auto-reload Mode Block Diagram

298 Rev. 1.2 24.2.4. Toggle Output Mode Timer 2, 3, and 4 have the capability to toggle the state of their respective output port pins (T2, T3, or T4) to produce a 50% duty cycle wave form output. The port pin state will change upon the overflow or under- flow of the respective timer (depending on whether the timer is counting up or down). The toggle frequency is determined by the clock source of the timer and the values loaded into RCAPnH and RCAPnL. When counting DOWN, the auto-reload value for the timer is 0xFFFF, and underflow will occur when the value in the timer matches the value stored in RCAPnH:RCAPnL. When counting UP , the auto-reload value for the timer is RCAPnH:RCAPnL, and overflow will occur when the value in the timer transitions from 0xFFFF to the reload value. To output a square wave, the timer is placed in reload mode (the Capture/Reload Select Bit in TMRnCN and the Timer/Counter Select Bit in TMRnCN are cleared to ‘0’). The timer output is enabled by setting the Timer Output Enable Bit in TMRnCF to ‘1’. The timer should be configured via the timer clock source and reload/underflow values such that the timer overflow/u nderflows at 1/2 the desire d output frequency. The port pin assigned by the crossbar as the timer’s output pin should be configured as a digital output (see Section “18. Port Input/Output” on page 203). Setting the timer’s Run Bit (TRn) to ‘1’ will start the toggle of the pin. A Read/Write of the Timer’s Toggle Output State Bit (TMRnCF.2) is used to read the state of the toggle output, or to force a value of the output. This is useful when it is desired to start the toggle of a pin in a known state, or to force the pin into a desired state when the toggle mode is halted. Fsq FTCLK Equation 24.1. Toggle Mode Square Wave Frequency

Rev. 1.2 299 Bit7: TFn: Timer 2, 3, and 4 Overflow/Underflow Flag. Set by hardware when either the Timer overflows from 0xFFFF to 0x0000, underflows from the value placed in RCAPnH:RCAPnL to 0XFFFF (in Auto-reload Mode), or underflows from 0x0000 to 0xFFFF (in Capture Mode). When the Timer interrupt is enabled, setting this bit causes the CPU to vector to the Timer interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit6: EXFn: Timer 2, 3, and 4 External Flag. Set by hardware when either a capture or reload is caused by a high-to-low transition on the TnEX input pin and EXENn is logic 1. When the Timer interrupt is enabled, setting this bit causes the CPU to vector to the Timer Interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit5-4: Reserved. Bit3: EXENn: Timer 2, 3, and 4 External Enable. Enables high-to-low transitions on TnEX to trigger captures, reloads, and control the direc- tion of the timer/counter (up or down count). If DCENn = 1, TnEX will determine if the timer counts up or down when in Auto-reload Mode. If EXENn = 1, TnEX should be configured as a digital input. 0: Transitions on the TnEX pin are ignored. 1: Transitions on the TnEX pin cause capture, reload, or control the direction of timer count (up or down) as follows: Capture Mode : ‘1’-to-’0’ Transition on TnEX pin causes RCAPnH:RCAPnL to capture timer value. Auto-Reload Mode DCENn = 0: ‘1’-to-’0’ transition causes reload of timer and sets the EXFn Flag. DCENn = 1: TnEX logic level controls direction of timer (up or down). Bit2: TRn: Timer 2, 3, and 4 Run Control. This bit enables/disables the respective Timer. 0: Timer disabled. 1: Timer enabled and running/counting. Bit1: C/Tn: Counter/Timer Select. 0: Timer Function: Timer incremented by clock defined by TnM1:TnM0 (TMRnCF.4:TMRnCF.3). 1: Counter Function: Timer incremented by high-to-low transitions on external input pin. Bit0: CP/RLn: Capture/Reload Select. This bit selects whether the Timer functions in capture or auto-reload mode. 0: Timer is in Auto-Reload Mode. 1: Timer is in Capture Mode. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value TFn EXFn - - EXENn TRn C/Tn CP/RLn 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: TMR2CN: 0xC8; TMR3CN: 0xC8; TMR4CN: 0xC8 SFR Page: TMR2CN: page 0; TMR3CN: page 1; TMR4CN: page 2 Figure 24.13. TMRnCN: Timer 2, 3, and 4 Control Registers

300 Rev. 1.2 Bit7-5: Reserved. Bit4-3: TnM1 and TnM0: Timer Clock Mode Select Bits. Bits used to select the Timer clock source. The sources can be the System Clock (SYSCLK), SYSCLK divided by 2 or 12, or an external clock signal routed to Tn (port pin) divided by 8. Clock source is selected as follows: 00: SYSCLK/12 01: SYSCLK 10: EXTERNAL CLOCK/8 11: SYSCLK/2 Bit2: TOGn: Toggle output state bit. When timer is used to toggle a port pin, this bit can be used to read the state of the output, or can be written to in order to force the state of the output. Bit1: TnOE: Timer output enable bit. This bit enables the timer to output a 50% duty cycle output to the timer’s assigned external port pin. NOTE : A timer is configured for Square Wave Output as follows: CP/RLn= 0 C/Tn = 0 TnOE = 1 Load RCAPnH:RCAPnL (See “Toggle Mode Square Wave Frequency” on page 298.) Configure Port Pin to output squarewave (See Section “18. Port Input/Output” on page 203) 0: Output of toggle mode not available at Timers’s assigned port pin. 1: Output of toggle mode available at Timers’s assigned port pin. Bit0: DCENn: Decrement Enable Bit. This bit enables the timer to count up or down as determined by the state of TnEX. 0: Timer will count up, regardless of the state of TnEX. 1: Timer will count up or down depending on the state of TnEX as follows: if TnEX = 0, the timer counts DOWN if TnEX = 1, the timer counts UP. R/W R/W R/W R/W R/W Reset Value - - - TnM1 TnM0 TOGn TnOE DCENn 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: TMR2CF: 0xC9; TMR3CF: 0xC9; TMR4CF: 0xC9 SFR Page TMR2CF: page 0; TMR3CF: page 1; TMR4CF: page 2 Figure 24.14. TMRnCF: Timer 2, 3, and 4 Configuration Registers

302 Rev. 1.2 Figure 24.18. TMRnH: Timer 2, 3, and 4 High Byte Bits 7-0: TH2, 3, and 4: Timer 2, 3, and 4 High Byte. The TH2, 3, and 4 register contains the high byte of the 16-bit Timer 2, 3, and 4 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: TMR2H: 0xCD; TMR3H: 0xCD; TMR4H: 0xCD SFR Page: TMR2H: page 0; TMR3H: page 1; TMR4H: page 2

Rev. 1.2 303 25. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. PCA0 consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section “18.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 205 ). The counter/timer is driven by a programmable time- base that can select between six inputs as its sour ce: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an external clock signal on the ECI line. Each capture/compare module may be configured to operate independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each is described in Section 25.2). The PCA is configured and controlled through the system controller's Special Function Registers. The basic PCA block diagram is shown in Figure 25.1. Figure 25.1. PCA Block Diagram Capture/Compare Module 1 Capture/Compare Module 0 Capture/Compare Module 2 Capture/Compare Module 3 CEX1 ECI Crossbar CEX2 CEX3 CEX0 Port I/O 16-Bit Counter/TimerPCA CLOCK MUX SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 Capture/Compare Module 4 CEX4 Capture/Compare Module 5 CEX5

304 Rev. 1.2 25.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bi t SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter. Read- ing PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD regis- ter select the timebase for the counter/timer as shown in Table 25.1. When the counter/timer overflows from 0xFFFF to 0x0 000, the Counter Overflow Flag (CF) in PCA0MD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the CPU vectors to the inte rrupt service routine, and must be cleared by soft- ware (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 inter- rupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the CIDL bit in the PCA0MD register a llows the PCA to continue normal operation while the CPU is in Idle mode. Table 25.1. PCA Timebase Input Options CPS2 CPS1 CPS0 Timebase 0 0 0 System clock divided by 12 0 0 1 System clock divided by 4 0 1 0 Timer 0 overflow

011 High-to-low transitions on ECI (max rate = system clock divided

by 4)

100 S y s t e m c l o c k

101 External oscillator source divided by 8 (synchronized with sys-

tem clock) Figure 25.2. PCA Counter/Timer Block Diagram PCA0MD C I D L W D T E E C F C P S C P S W D L C K C P S IDLE

1 PCA0H PCA0L

Overflow To PCA Interrupt System CF PCA0L read To PCA Modules SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI 000 001 010 011 100 101 SYSCLK External Clock/8 PCA0CN C F C R C C F C C F C C F C C F C C F C C F

Rev. 1.2 305 25.2. Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP- 51 system controller. These registers are used to exchange data with a module and configure the module's mode of operation. Table 25.2 summarizes the bit settings in the PCA0CPMn registers used to select the PCA0 capture/com- pare module’s operating modes. Setting the ECCFn bi t in a PCA0CPMn register enables the module's CCFn interrupt. Note: PCA0 interrupts must be globally enabled before individual CCFn interrupts are rec- ognized. PCA0 interrupts are globally enabled by se tting the EA bit (IE.7) and the EPCA0 bit (EIE1.3) to logic 1. See Figure 25.3 for details on the PCA interrupt configuration. Table 25.2. PCA0CPM Register Settings for PCA Capture/Compare Modules PWM16 ECOM CAPP CAPN MAT TOG PWM ECCF Operation Mode X X 1 0000X Capture triggered by positive edge on CEXn X X 0 1000X Capture triggered by negative edge on CEXn X X 1 1000X Capture triggered by transition on CEXn X 1 0 0 1 0 0 X Software Timer X 1 0 0 1 1 0 X High Speed Output X 1 0 0 0 1 1 X Frequency Output 0 1 0 0 0 0 1 0 8-Bit Pulse Width Modulator 1 1 0 0 0 0 1 0 16-Bit Pulse Width Modulator X = Don’t Care Figure 25.3. PCA Interrupt Block Diagram PCA0CN C F C R C C F C C F C C F C C F C C F C C F PCA0MD C I D L E C F C P S C P S C P S PCA Module 0 PCA Module 1 ECCF1 ECCF0 PCA Module 2 ECCF2 PCA Module 3 ECCF3 ECCF4 PCA Counter/ Timer Overflow Interrupt Priority Decoder EPCA0 (EIE.3) PCA0CPMn (for n = 0 to 5) P W M n E C O M n E C C F n T O G n P W M n C A P P n C A P N n M A T n 1PCA Module 4 PCA Module 5 EA (IE.7) ECCF5

306 Rev. 1.2 25.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin caus es PCA0 to capture the value of the PCA0 counter/ timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (p ositive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when th e CPU vectors to the interrupt serv ice routine, and must be cleared by software. Note: The signal at CEXn must be high or low for at least 2 system clock cycles in order to be valid. Figure 25.4. PCA Capture Mode Diagram PCA0L PCA0CPLn PCA Timebase CEXnCrossbarPort I/O PCA0H Capture PCA0CPHn (to CCFn) PCA Interrupt PCA0CPMn P W M n E C O M n E C C F n T O G n P W M n C A P P n C A P N n M A T n PCA0CN C F C R C C F C C F C C F C C F C C F C C F

Rev. 1.2 307 25.2.2. Software Timer (Compare) Mode In Software Timer mode, the PCA0 counter/timer is compared to the module's 16-bit capture/compare reg- ister (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vect ors to the interrupt service routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode. Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0 Capture/ Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’. Figure 25.5. PCA Software Timer Mode Diagram Match16-bit Comparator PCA0H PCA0CPHn Enable PCA0LPCA Timebase PCA0CPLn 00 00 PCA Interrupt x ENB ENB Write to PCA0CPLn Write to PCA0CPHn Reset PCA0CPMn P W M n E C O M n E C C F n T O G n P W M n C A P P n C A P N n M A T n x PCA0CN C F C R C C F C C F C C F C C F C C F C C F

308 Rev. 1.2 25.2.3. High Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16- bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High- Speed Output mode. Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0 Capture/ Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’. Figure 25.6. PCA High Speed Output Mode Diagram Match16-bit Comparator PCA0H PCA0CPHn Enable PCA0LPCA Timebase PCA0CPLn PCA Interrupt 00 0x ENB ENB Write to PCA0CPLn Write to PCA0CPHn Reset PCA0CPMn P W M n E C O M n E C C F n T O G n P W M n C A P P n C A P N n M A T n x CEXn Crossbar Port I/O Toggle TOGn PCA0CN C F C R C C F C C F C C F C C F C C F C C F

Rev. 1.2 309 25.2.4. Frequency Output Mode Frequency Output Mode produces a programmable-freq uency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of the square wave is then defined by Equation 25.1. Where F PCA is the frequency of the clock selected by the CPS2-0 bits in the PCA mode register, PCA0MD. The lower byte of the capture/compare module is compared to the PCA0 counter low byte; on a match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn. Fre- quency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn register. Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0 Capture/ Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’. Equation 25.1. Square Wave Frequency Output Fsqr FPCA Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation. 8-bit Comparator PCA0L Enable PCA Timebase 000 0 match PCA0CPMn P W M n E C O M n E C C F n T O G n P W M n C A P P n C A P N n M A T n PCA0CPHn8-bit AdderPCA0CPLn Adder Enable CEXn Crossbar Port I/O Toggle TOGn Figure 25.7. PCA Frequency Output Mode

310 Rev. 1.2 25.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate pulse width modulated (PWM) outputs on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA0 counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register. When the value in the low byte of the PCA0 counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be high . When the count value in PCA0L overflows, the CEXn output will be low (see Figure 25.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stor ed in the counter/timer's high byte (PCA0H) with- out software intervention. Setting the ECOMn and PW Mn bits in the PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 25.2. Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0 Capture/ Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’. DutyCycle 256 PCA 0CPHn–() Equation 25.2. 8-Bit PWM Duty Cycle 8-bit Comparator PCA0L PCA0CPLn PCA0CPHn CEXn Crossbar Port I/OEnable Overflow PCA Timebase 0000 0 Q Q SET CLR S R match PCA0CPMn P W M n E C O M n E C C F n T O G n P W M n C A P P n C A P N n M A T n Figure 25.8. PCA 8-Bit PWM Mode Diagram

Rev. 1.2 311 25.2.6. 16-Bit Pulse Width Modulator Mode Each PCA0 module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA0 clocks for the low time of the PWM signal. When the PCA0 counter matches the module contents, the output on CEXn is as serted high; when the counter overflows, CEXn is asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA0 CCFn match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a varying duty cycle, CCFn should also be set to logic 1 to enable match inter- rupts. The duty cycle for 16-Bit PWM Mode is given by Equation 25.3. Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0 Capture/ Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’. Equation 25.3. 16-Bit PWM Duty Cycle DutyCycle 65536 PCA 0CPn–() Figure 25.9. PCA 16-Bit PWM Mode PCA0CPLnPCA0CPHn Enable PCA Timebase 0000 0 PCA0CPMn P W M n E C O M n E C C F n T O G n P W M n C A P P n C A P N n M A T n 16-bit Comparator CEXn Crossbar Port I/O Overflow Q Q SET CLR S R match PCA0H PCA0L

312 Rev. 1.2 25.3. Register Descriptions for PCA0 Following are detailed descriptions of the special function registers related to the operation of PCA0. Bit7: CF: PCA Counter/Timer Overflow Flag. Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vec- tor to the CF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit6: CR: PCA0 Counter /Timer Run Control. This bit enables/disables the PCA0 Counter/Timer. 0: PCA0 Counter/Timer disabled. 1: PCA0 Counter/Timer enabled. Bit5: CCF5: PCA0 Module 5 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit4: CCF4: PCA0 Module 4 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit3: CCF3: PCA0 Module 3 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit2: CCF2: PCA0 Module 2 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit1: CCF1: PCA0 Module 1 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit0: CCF0: PCA0 Module 0 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value CF CR CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xD8 Figure 25.10. PCA0CN: PCA Control Register

Rev. 1.2 313 Figure 25.11. PCA0MD: PCA0 Mode Register Bit7: CIDL: PCA0 Counter/Timer Idle Control. Specifies PCA0 behavior when CPU is in Idle Mode. 0: PCA0 continues to function normally while the system controller is in Idle Mode. 1: PCA0 operation is suspended while the system controller is in Idle Mode. Bits6-4: UNUSED. Read = 000b, Write = don't care. Bits3-1: CPS2-CPS0: PCA0 Co unter/Timer Pulse Select. These bits select the timebase source for the PCA0 counter Bit0: ECF: PCA Counter/Timer Overflow Interrupt Enable. This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt. 0: Disable the CF interrupt. 1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set. †Note: External clock divided by 8 is synchronize d with the system clock, and external clock must be less than or equal to the system clock frequency to operate in this mode. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value CIDL - - - CPS2 CPS1 CPS0 ECF 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xD9 CPS2 CPS1 CPS0 Timebase 0 0 0 System clock divided by 12 0 0 1 System clock divided by 4 0 1 0 Timer 0 overflow

011 High-to-low transitions on ECI (max rate = system clock

divided by 4) 1 0 0 System clock 1 0 1 External clock divided by 8† 1 1 0 Reserved 1 1 1 Reserved

314 Rev. 1.2 Figure 25.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers Bit7: PWM16n: 16-bit Pulse Width Modulation Enable. This bit selects 16-bit mode when Pulse Width Modulation mode is enabled (PWMn = 1). 0: 8-bit PWM selected. 1: 16-bit PWM selected. Bit6: ECOMn: Comparator Function Enable. This bit enables/disables the comparator function for PCA0 module n. 0: Disabled. 1: Enabled. Bit5: CAPPn: Capture Positi ve Function Enable. This bit enables/disables the positive edge capture for PCA0 module n. 0: Disabled. 1: Enabled. Bit4: CAPNn: Capture Negative Function Enable. This bit enables/disables the negative edge capture for PCA0 module n. 0: Disabled. 1: Enabled. Bit3: MATn: Match Function Enable. This bit enables/disables the match function for PCA0 module n. When enabled, matches of the PCA0 counter with a module's capture/compare register cause the CCFn bit in PCA0MD register to be set to logic 1. 0: Disabled. 1: Enabled. Bit2: TOGn: Toggle Function Enable. This bit enables/disables the toggle function for PCA0 module n. When enabled, matches of the PCA0 counter with a module's capture/compare register cause the logic level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module operates in Frequency Output Mode. 0: Disabled. 1: Enabled. Bit1: PWMn: Pulse Width Modulation Mode Enable. This bit enables/disables the PWM function for PCA0 module n. When enabled, a pulse width modulated signal is output on the CEXn pin. 8-bit PWM is used if PWM16n is logic 0; 16-bit mode is used if PWM16n logic 1. If the TOGn bit is also set, the module operates in Frequency Output Mode. 0: Disabled. 1: Enabled. Bit0: ECCFn: Capture/Compare Flag Interrupt Enable. This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt. 0: Disable CCFn interrupts. 1: Enable a Capture/Compare Flag interrupt request when CCFn is set. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: PCA0CPM0: 0xDA, PCA0CPM1: 0xDB, PCA0CPM2: 0xDC, PCA0CPM3: 0xDD, PCA0CPM4: 0xDE, PCA0CPM5: 0xDF SFR Page: PCA0CPM0: page 0, PCA0CPM1: page 0, PCA0CPM2: page 0, PCA0CPM3: 0, PCA0CPM4: page 0, PCA0CPM5: page 0

Rev. 1.2 317 26. JTAG (IEEE 1149.1) Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-sys- tem testing, Flash read/write operations, and non-int rusive in-circuit debug. Th e JTAG interf ace is fully compliant with the IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test Interface and Boundary-Scan Architec ture. Access of the JTAG Instruction Register (IR) and Data Regis- ters (DR) are as described in the Test Access Port and Operation of the IEEE 1149.1 specification. The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO. Through the 16-bit JTAG Instruction Register (IR), any of the eight instructions shown in Figure 26.1 can be commanded. There are three DR’s associated wit h JTAG Boundary-Scan, and four associated with Flash read/write operations on the MCU. Figure 26.1. IR: JTAG Instruction Register Reset Value 0x0000 Bit15 Bit0 IR Value Instruction Description 0x0000 EXTEST Selects the Boundary Data Register for control and observability of all device pins 0x0002 SAMPLE/ PRELOAD Selects the Boundary Data Register for observability and presetting the scan-path latches 0x0004 IDCODE Selects device ID Register 0xFFFF BYPASS Selects Bypass Data Register 0x0082 Flash Control Selects FLASHCON Register to control how the interface logic responds to reads and writes to the FLASHDAT Register 0x0083 Flash Data Selects FLASHDAT Register for reads and writes to the Flash memory 0x0084 Flash Address Selects FLASHADR Register which holds the address of all Flash read, write, and erase operations 0x0085 Flash Scale Selects FLASHSCL Register which controls the Flash one-shot timer and read-always enable

318 Rev. 1.2 26.1. Boundary Scan The DR in the Boundary Scan path is a 126-bit shift register for the C8051F060/2/4/6 and a 118-bit shift register for the C8051F061/3/5/7. The Boundary DR provides control and observability of all the device pins as well as the SFR bus and Weak Pullup feature via the EXTEST and SAMPLE commands. Table 26.1. Boundary Data Register Bit Definitions (C8051F060/2/4/6) EXTEST provides access to both capture and update actions, while Sample only performs a capture. Bit Action Target

0 Capture Reset Enable from MCU

Update Reset Enable to /RST pin

1 Capture Reset Input from /RST pin

2 Capture CAN RX Output Enable to pin

Update CAN RX Output Enable to pin

3 Capture CAN RX Input from pin

Update CAN RX Output to pin

4 Capture CAN TX Output Enable to pin

Update CAN TX Output Enable to pin

5 Capture CAN TX Input from pin

Update CAN TX Output to pin

6 Capture External Clock from XTAL1 pin

7 Capture Weak Pullup Enable from MCU

Update Weak Pullup Enable to Port Pins 8, 10, 12, 14, 16, 18, 20, 22 9, 11, 13, 15, 17, 19, 21, 23 34, 36, 38 Capture P1.n output enable from MCU (follows P0.n numbering scheme) Update P1.n output enable to pin (follows P0.n numbering scheme) 35, 37, 39 Capture P1.n input from pin (follows P0.n numbering scheme) Update P1.n output to pin (fo llows P0.n numbering scheme) 50, 52, 54 Capture P2.n output enable from MCU (follows P0.n numbering scheme) Update P2.n output enable to pin (follows P0.n numbering scheme) 51, 53, 55 Capture P2.n input from pin (follows P0.n numbering scheme) Update P2.n output to pin (fo llows P0.n numbering scheme) 66, 68, 70 Capture P3.n output enable from MCU (follows P0.n numbering scheme) Update P3.n output enable to pin (follows P0.n numbering scheme) 67, 69, 71 Capture P3.n input from pin (follows P0.n numbering scheme) Update P3.n output to pin (fo llows P0.n numbering scheme) 72, 74, 76 Capture P4.5, P4.6, P4.7 (r espectively) output enable from MCU Update P4.5, P4.6, P4.7 (respec tively) output enable to pin 73, 75, 77 Capture P4.5, P4.6, P4.7 (respectively) input from pin Update P4.5, P4.6, P4.7 (res pectively) output to pin 88, 90, 92 Capture P5.n output enable from MCU (follows P0.n numbering scheme) Update P5.n output enable to pin (follows P0.n numbering scheme)

Rev. 1.2 319 89, 91, 93 Capture P5.n input from pin (follows P0.n numbering scheme) Update P5.n output to pin (fo llows P0.n numbering scheme) 94, 96, 98, 100, 102, 104, 106, 108 Capture P6.n output enable from MCU (follows P0.n numbering scheme) Update P6.n output enable to pin (follows P0.n numbering scheme) 95, 97, 99, 101, 103, 105, 107, 109 Capture P6.n input from pin (follows P0.n numbering scheme) Update P6.n output to pin (fo llows P0.n numbering scheme) 110, 112, 114, 116, 118, 120, 122, 124 Capture P7.n output enable from MCU (follows P0.n numbering scheme) Update P7.n output enable to pin (follows P0.n numbering scheme) 111, 113, 115, 117, 119, 121, 123, 125 Capture P7.n input from pin (follows P0.n numbering scheme) Update P7.n output to pin (fo llows P0.n numbering scheme) Table 26.1. Boundary Data Register Bit Definitions (C8051F060/2/4/6) (Continued) EXTEST provides access to both capture and update actions, while Sample only performs a capture. Bit Action Target

320 Rev. 1.2 Table 26.2. Boundary Data Register Bit Definitions (C8051F061/3/5/7) EXTEST provides access to both capture and update actions, while Sample only performs a capture. Bit Action Target

0 Capture Not used

1 Capture Not used

Update CAN RX Output Enable to pin Update CAN RX Output to pin Update CAN TX Output Enable to pin Update CAN TX Output to pin Update Weak Pullup Enable to Port Pins 8, 10, 12, 14, 16, 18, 20, 22 9, 11, 13, 15, 17, 19, 21, 23 34, 36, 38 Capture P1.n output enable from MCU (follows P0.n numbering scheme) Update P1.n output enable to pin (follows P0.n numbering scheme) 35, 37, 39 Capture P1.n input from pin (follows P0.n numbering scheme) Update P1.n output to pin (fo llows P0.n numbering scheme) 50, 52, 54 Capture P2.n output enable from MCU (follows P0.n numbering scheme) Update P2.n output enable to pin (follows P0.n numbering scheme) 51, 53, 55 Capture P2.n input from pin (follows P0.n numbering scheme) Update P2.n output to pin (fo llows P0.n numbering scheme) 66, 68, 70 Capture P3.n output enable from MCU (follows P0.n numbering scheme) Update P3.n output enable to pin (follows P0.n numbering scheme) 67, 69, 71 Capture P3.n input from pin (follows P0.n numbering scheme) Update P3.n output to pin (fo llows P0.n numbering scheme)

72 Capture Reset Enable from MCU

Update Reset Enable to /RST pin

73 Capture Reset Input from /RST pin

MCU† 96, 98, 100 Capture P6.n output enable from MCU (follows P0.n numbering scheme)† Update P6.n output enable to pin (follows P0.n numbering scheme)†

Rev. 1.2 321 26.1.1. EXTEST Instruction The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all the device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1. 26.1.2. SAMPLE Instruction The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of the scan-path latches. 26.1.3. BYPASS Instruction The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data reg- ister. 26.1.4. IDCODE Instruction The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register. 97, 99, 101 Capture P6.n input from pin (follows P0.n numbering scheme)† Update P6.n output to pin (fo llows P0.n numbering scheme)† 102, 104, 106, 108, 110, 112, 114, 116 Capture P7.n output enable from MCU (follows P0.n numbering scheme)† Update P7.n output enable to pin (follows P0.n numbering scheme)† 103, 105, 107, 109, 111, 113, 115, 117 Capture P7.n input from pin (follows P0.n numbering scheme)† Update P7.n output to pin (fo llows P0.n numbering scheme)† † Not connected to pins in this device package. Table 26.2. Boundary Data Register Bit Definitions (C8051F061/3/5/7) (Continued) EXTEST provides access to both capture and update actions, while Sample only performs a capture. Bit Action Target Figure 26.2. DEVICEID: JTAG Device ID Register Version = 0000b Part Number = 0000 0000 0000 0110b (C8051F060/1/2/3/4/5/6/7) Manufacturer ID = 0010 0100 001b (Silicon Labs) Reset Value Version Part Number Manufacturer ID 1 0xn0006243 Bit31 Bit28 Bit27 Bit12 Bit11 Bit1 Bit0

322 Rev. 1.2 26.2. Flash Programming Commands The Flash memory can be programmed directly over the JTAG interface using the Flash Control, Flash Data, Flash Address, and Flash Scale registers. These Indirect Data Registers are accessed via the JTAG Instruction Register. Read and write operations on indirect data registers are performed by first setting the appropriate DR address in the IR register. Each read or write is then initiated by writing the appropriate Indirect Operation Code (IndOpCode) to the selected data register. Incoming commands to this register have the following format: IndOpCode: These bit set the operation to perform according to the following table: The Poll operation is used to check the Busy bit as described below. Although a Capture-DR is performed, no Update-DR is allowed for the Poll operation. Since updates are disabled, polling can be accomplished by shifting in/out a single bit. The Read operation initiates a read from the register addressed by the DRAddress. Reads can be initiated by shifting only 2 bits into the indirect register. Afte r the read operation is initia ted, polling of the Busy bit must be performed to determine when the operation is complete. The write operation initiates a write of WriteData to the register addressed by DRAddress. Registers of any width up to 18 bits can be written. If the register to be written contains fewer than 18 bits, the data in Write- Data should be left-justified, i.e. its MSB should occupy bit 17 above. This allows shorter registers to be written in fewer JTAG clock cycles. For example, an 8-bi t register could be written by shifting only 10 bits. After a Write is initiated, the Busy bit should be polled to determine when the next operation can be initi- ated. The contents of the Instruction Register should not be altered while either a read or write operation is busy. Outgoing data from the indirect Data Register has the following format: The Busy bit indicates that the current operation is not complete. It goes high when an operation is initiated and returns low when complete. Read and Write commands are ignored while Busy is high. In fact, if poll- ing for Busy to be low will be followed by another read or write operation, JTAG writes of the next operation can be made while checking for Busy to be low. They will be ignored unt il Busy is read low, at which time the new operation will initiate. This bit is placed at bit 0 to allow polling by single-bit shifts. When waiting for a Read to complete and Busy is 0, the following 18 bits can be shifted out to obtain the resulting data. ReadData is always right-justified. This allows regi sters shorter than 18 bits to be read using a reduced number of shifts. For example, the results from a byte-read requires 9 bit shifts (Busy + 8 bits). 19:18 17:0 IndOpCode WriteData IndOpCode Operation 0x Poll

10 Read

11 Write

19 18:1 0

0 ReadData Busy

Rev. 1.2 323 Figure 26.3. FLASHCON: JTAG Flash Control Register This register determines how the Flash interface logic will respond to reads and writes to the FLASHDAT Register. Bit7: SFLE: Scratchpad Flash Memory Access Enable When this bit is set, Flash reads and writes through the JTAG port are directed to the 128- byte Scratchpad Flash sector. When SFLE is set to logic 1, Flash accesses out of the address range 0x00-0x7F should not be attempted. Reads/Writes out of this range will yield undefined results. 0: Flash access from JTAG directed to the Program/Data Flash sector. 1: Flash access from JTAG directed to the Scratchpad sector. Bits6-4: WRMD2-0: Write Mode Select Bits. The Write Mode Select Bits control how the interface logic responds to writes to the FLASH- DAT Register per the following values: 000: A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise ignored. 001: A FLASHDAT write initiates a write of FLASHDAT into the memory address by the FLASHADR register. FLASHADR is incremented by one when complete. 010: A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page containing the address in FLASHADR. The data written must be 0xA5 for the erase to occur. FLASHADR is not affected. If FLASHADR = 0x7BFE - 0x7BFF, the entire user space will be erased (i.e. entire Flash memory except for Reserved area 0x7C00 - 0x7FFF). (All other values for WRMD2-0 are reserved.) Bits3-0: RDMD3-0: Read Mode Select Bits. The Read Mode Select Bits control how the interface logic responds to reads to the FLASH- DAT Register per the following values: 0000: A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise ignored. 0001: A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register if no operation is currently active. This mode is used for block reads. 0010: A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no operation is active and any data from a previous read has already been read from FLASH- DAT. This mode allows single bytes to be read (or the last byte of a block) without initiating an extra read. (All other values for RDMD3-0 are reserved.) Reset Value SFLE WRMD2 WRMD1 WRMD0 RDMD3 RDMD2 RDMD1 RDMD0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Rev. 1.2 325 26.3. Debug Support Each MCU has on-chip JTAG and debug logic that provides non-intrusive, full speed, in-circuit debug sup- port using the production part installed in the end application, via the four pin JTAG I/F. Silicon Labs' debug system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, or communi cations channels are required. All the digital and analog peripherals are functional and work correctly (remain synchr onized) while debugging. The Watch- dog Timer (WDT) is disabled when the MCU is halted during single stepping or at a breakpoint. The C8051F060DK is a development kit with all the hardware and software necessary to develop applica- tion code and perform in-circuit debug with each MCU in the C8051F06x family. Each kit includes develop- ment software for the PC, a Serial Adapter (for c onnection to JTAG) and a target application board with a C8051F060 installed. Serial cables and wall-mount power supply are also included.

326 Rev. 1.2

Rev. 1.2 327 Document Change List Revision 1.1 to Revision 1.2

• Added four part numbers: C8051F064, C8051F065, C8051F066, and C8051F067.
• Modified all sections to describe functionality of the four new parts.
• Revised and expanded Flash Chapter with cleare r descriptions of Flash security features.
• UART0 Chapter, Section 22.3: “FE0 in register SCON0” changed to “FE0 in register SSTA0”.
• UART0 Chapter: Updated and clarified baud rate equations.
• Port I/O Chapter, Section 18.2: Added a note in text body that Port 4-7 registers are all on SFR Page F.
• Comparators Chapter: Updated Table 12.1 “Comparator Electrical Characteristics”.
• CIP51 Chapter: Section 13.4.1: Added note regarding IDLE mode operation.
• ADC2 Chapter: AD2LJST bit remove d from ADC2CF register description (AD2LJST is in the ADC2CN register).
• ADC2 Chapter: Updated Table 7.1 “ADC2 Electrical Characteristics” and Figure 7.2 “Temperature Sen- sor Transfer Function” with temperature sensor information.
• ADC0/ADC1 Chapter: Tracking/Conversion timing when ADnTM = 1 is shown in Figure 5.4 and Table 5.1. References to “18” or “16” SAR clocks of tracking were removed.
• DACs Chapter, Table 8.1 “DAC Electrical Characteri stics”: Changed “Gain Error” to “Full-Scale Error”.
• SMBus Chapter, Figure 20.9 SMB0CR: Changed “1.125” to “1.125 * 10^6”.
• PCA Chapter, Figure 25.12 PCA0CPMn: Bit 0 name changed to “ECCFn” (from incorrect “EECFn”).
• JTAG Chapter, Figure 26.3 FLASHCON: Bit 7 description corrected. Bit 7 is SFLE, allowing access to the Scratchpad memory area.
• CAN Chapter: Added text “The CAN controller’s clock (f sys, or CAN_CLK in the C_CAN User’s Guide) is equal to the CIP-51 MCU’s clock (SYSCLK).”
• Table 4.1 “Pin Descriptions”, MO NEN: Added text “Recommended configuration is to connect directly to VDD.”
• Timers Chapter: All refere nces to “DCEN” and “DECEN” corrected to “DCENn”.
• Timers Chapter, Equation 24.1: Equation was corrected to “Fsq = Ftclk / (2*(65536-RCAPn))”. This equation is valid for a timer counting up or down.
• Timers Chapter, Figure 24.14 TMRnCF: Corrected Bit 1 description. For square-wave output, CP/RLn = 0, C/Tn = 0, TnOE = 1.
• VREF Chapters: Added VREF Powe r Supply Current to VREF Electrical Characteristics Tables.
• PCA Chapter: Added Note about writing PCA0CPLn and PCA0CPHn to sections for SW Timer Mode, High-Speed Output Mode, Frequency Output Mode, 8-bit PWM Mode, and 16-bit PWM Mode.
• Oscillators Chapter, Table 15 .1 “Internal Oscillator Electrical Characteristics”: Updated typical supply current.
• Table 3.1 “Global DC Electrical Characteristics”, Updated supply current numbers with additional char- acterization data.
• ADC0/ADC1 Chapter: Table 5.2 “ADC0 and ADC1 Elec trical Characteristics”, Updated supply current numbers with additional characterization data.
• ADC0/ADC1 Chapter: Table 5.3 “Voltage Reference 0 and 1 Electrical Characteristics”, Updated Out- put Voltage numbers with characterization data.
• Figure 4.3 “TQFP-100 Package Drawing”, Added “L” Dimension.
• Figure 4.6 “TQFP-64 Package Drawing”, Added “L” Dimension.

328 Rev. 1.2 Contact Information Silicon Laboratories Inc.

4635 Boston Lane

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