C8051F060 SILABS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 2

Technical content

CAN 2.0B Copyright © 2004 by S ilicon Laboratories 6.15.2004 P0, P1, P2, P3 Latches JTAG Logic UART1 SMBus SPI Bus PCA 64 kB FLASH 256 byte RAM VDD Monitor SFR Bus C o r e Timers 0, 1, 2,3,4 Drv C R O S S B A R Reset External Oscillator Circuit System Clock

25 MHz 2%

P2.0 P2.7 P1.0/AIN2.0 P1.7/AIN2.7 P0.0 P0.7 Drv Drv Data Bus Address Bus Bus Control DAC0 (12-Bit) VREF UART0 P3.0 P3.7 Drv ADC 200 ksps (10-Bit) A M U X 8:1 WDT VREF2 P4 Latch P7 Latch P5 Latch P6 Latch P7.0 P7.7 DRV P5.0 P5.7 DRV P6.0 P6.7 DRV DRV P4.5 P4.6 P4.7 External Data Memory Bus CP0 + P2.6 Addr7-0 Addr15-8 Ctrl Latch Data Latch CP1 + CP2 + CTX CRX CAN 2.0B (32 Message Objects) ADC0

1 Msps

(16-Bit) R E S U L T R E S U L T Σ + D I F F DMA Temp Sensor EMIF Cntrl ADGND AVDD ADC1 1Msps (16-Bit) P2.7 P2.2 P2.3 P2.4 P2.5 TCK TMS TDI TDO RST XTAL1 XTAL2 DAC0 VREF MONEN VREFD VRGND0 DAC1 VDDVDD VDD DGND DGNDDGND AV+ AGND VREF0AGND AV+ VRGND1 VREF1 ADGND AVDD AIN0 AIN0G VBGAP0 CNVSTR0 AGNDAV+ AIN1 AIN1G VBGAP1 CNVSTR1 C8051F060

25 MIPS, 64 kB Flash, 16-Bit ADC, 100-Pin Mixed-Signal MCU

  • ±0.75 LSB INL; guaranteed no missing codes - Programmable throughput up to 1 Msps (each ADC) - Configurable as two single-ended or one differential ADC - DMA to XRAM or external memory interface - Data-dependent windowed interrupt generator 10-Bit ADC - Programmable throughput up to 200 ksps - 8 external inputs - Built-in temperature sensor (±3 °C) Two 12-Bit DACs - Can synchronize outputs to timers for jitter-free waveform generation Three Comparators Internal Voltage Reference Precision VDD Monitor/Brown-out Detector On-Chip JTAG Debug & Boundary Scan - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) - Provides breakpoints, single stepping, watchpoints, stack monitor - Inspect/modify memory and registers - Superior performance to emulation systems using ICE-chips, target pods, and sockets - IEEE1149.1 compliant boundary scan Supply Voltage: 2.7 to 3.6 V - Typical operating current: 10 mA at 25 MHz - Multiple power saving sleep and shutdown modes High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - Up to 25 MIPS throughput with 25 MHz system clock - Expanded interrupt handler Memory - 4352 bytes data RAM - 64 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes are reserved) - External parallel data memory interface CAN Bus 2.0B - 32 message objects - ”Mailbox" implementation only interrupts CPU when needed Digital Peripherals - 59 port I/O; all are 5 V tolerant - Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial ports available concurrently - Programmable 16-bit counter array with 6 capture/compare modules - 5 general-purpose 16-bit counter/timers - Dedicated watchdog timer; bidirectional reset - Real-time clock mode using timers or PCA Clock Sources - Internal programmable 2% oscillator: up to 24.5 MHz - External oscillator: Crystal, RC, C, or Clock 100-Pin TQFP - Temperature Range: –40 to +85 °C

CAN 2.0B Copyright © 2004 by S ilicon Laboratories 6.15.2004 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders C8051F060 Selected Electrical Specifications (TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified) PARAMETER CONDITIONS MIN TYP MAX UNITS GLOBAL CHARACTERISTICS Supply Voltage 2.7 3.6 V Supply Current (CPU active) Clock = 25 MHz Clock = 1 MHz Clock = 32 kHz; V DD Monitor Enabled 0.7 mA mA µA Supply Current (shutdown) Oscillator not running; VDD Monitor Disabled 0.1 µA Clock Frequency Range DC 25 MHz 16-BIT A/D CONVERTERS Resolution 16 bits Integral Nonlinearity Single-ended Mode Differential Mode ±0.75 ±0.50 LSB LSB Differential Nonlinearity Guaranteed Monotonic ±0.5 ±1 LSB Signal-to-Noise Plus Distortion Fin = 10 kHz, Single-ended Fin = 10 kHz, Differential dB dB Total Harmonic Distortion Fin = 10 kHz, Single-ended Fin = 10 kHz, Differential 103 dB dB Spurious-Free Dynamic Range Fin = 10 kHz, Single-ended Fin = 10 kHz, Differential 104 dB dB Throughput Rate 1 Msps Input Voltage Range Single-ended (AINn–AINnG) Differential (AIN0–AIN1) –VREF V REF VREF V V Power Supply Current (each ADC) Operating Mode, 1 Msps (AVDD + AV+) Shutdown Mode 5.5 mA µA D/A CONVERTERS Resolution 12 LSB Differential Nonlinearity ±1 LSB Output Settling Time 10 µs

Package Information

A b D e E 0.05 0.95 0.17 1.00 0.22 16.00 14.00 0.50 16.00 14.00 1.20 0.15 1.05 0.27 MIN (mm) NOM (mm) MAX (mm) 100 e A1b A PIN 1 DESIGNATOR E1 E D C8051F060DK Development Kit