C3014 IMP | Alldatasheet
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Technical content
87© IMP, Inc. Process C3014 CMOS 3µ m
5 Volt Single Metal Analog
Electrical Characteristics
T=25oC Unless otherwise noted ISO 9001 Registered N-Channel Transistor Symbol Minimum Typical Maximum Unit Comments Threshold Voltage VT N 0.5 0.65 0.8 V 100x3 µm Body Factor γN 0.6 V 1/2 100x3µm Conduction Factor βN 42 47 52 µA/V2 100x100µm Effective Channel Length LeffN 2.0 2.3 2.6 µm 100x3 µm Width Encroachment ΔW N 0.7 µm Per side Punch Through Voltage BVDSS N 12 V Poly Field Threshold VoltageVTF P(N) 12 V P-Channel Transistor Symbol Minimum Typical Maximum Unit Comments Threshold Voltage VT P –0.5 0.65 –0.8 V 100x3 µm Body Factor γP 0.55 V 1/2 100x3µm Conduction Factor βP 13 15 19 µA/V2 100x100µm Effective Channel Length LeffP 2.85 3.2 3.55 µm 100x3 µm Width Encroachment ΔW P 0.9 µm Per side Punch Through Voltage BVDSS P –12 V Poly Field Threshold VoltageVTF P(P) –12 V Diffusion & Thin Films Symbol Minimum Typical Maximum Unit Comments Well (field) Sheet ResistanceρP-well(f) 3.2 4.8 6.5 K Ω /o P-well N+ Sheet Resistance ρN+ 16 21 27 Ω /o N+ Junction Depth x jN+ 0.8 µm P+ Sheet Resistance ρP+ 50 80 100 Ω /o P+ Junction Depth x jP+ 0.7 µm Gate Oxide Thickness T GOX 44 48 52 nm Interpoly Oxide Thickness TP1P2 60 nm Gate Poly Sheet ResistanceρPOLY1 15 22 30 Ω /o Bottom Poly Sheet Res. ρPOLY2 20 30 40 Ω /o Metal-1 Sheet Resistance ρM1 30 60 m Ω /o Passivation Thickness T PASS 200+900 nm oxide+nit. Capacitance Symbol Minimum Typical Maximum Unit Comments Gate Oxide C OX 0.66 0.72 0.78 fF/ µm 2 Metal-1 to Poly-1 C M1P 0.0523 fF/ µm 2 Metal-1 to Silicon C M1S 0.026 0.030 0.034 fF/ µm 2 Poly-1 to Poly-2 C P1P2 0.51 0.57 0.63 fF/ µm 2
88 C3014-4-98
Starting Material N <100> N+/P+ Width/Space 3.0 / 3.0 µm Starting Mat. Resistivity 15 - 25 Ω -cm N+ To P+ Space 12 µm Typ. Operating Voltage 5V Contact To Poly Space 2.5 µm Well Type P-well Contact Overlap Of Diffusion 1.5 µm Metal Layers 1 Contact Overlap Of Poly 1.0 µm Poly Layers 2 Metal-1 Overlap Of Contact 1.0 µm Contact Size 2.0x2.0 µm Minimum Pad Opening 100x100 µm Metal-1 Width/Space 3.5 / 2.5µm Minimum Pad-to-Pad Spacing 55 µm Gate Poly Width/Space 4.0 / 2.5µm Minimum Pad Pitch 80.0 µm Special Feature of C3014 Process: P-well analog low threshold process with single metal CMOS 3.0 µm technology for 5 Volt applications.