C1004 IMP | Alldatasheet
Document overview
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Technical content
© IMP, Inc. ISO 9001 Registered Process C1004 CMOS 1.0µ m
5 Volt Digital
N-Channel Transistor Symbol Minimum Typical Maximum Unit Comments Threshold Voltage VT N 0.55 0.75 0.95 V 100x1.0 µm Body Factor γN 0.60 V 1/2 100x1.0µm Conduction Factor βN 74 87 100 µA/V2 100x100µm Effective Channel Length LeffN 0.60 0.75 0.90 µm 100x1.0 µm Width Encroachment ΔW N 0.8 µm Per side Punch Through Voltage BVDSS N 7V Poly Field Threshold VTF P(N) 10 V P-Channel Transistor Symbol Minimum Typical Maximum Unit Comments Threshold Voltage VT P –0.85 –1.0 –1.15 V 100x1.0 µm Body Factor γP 0.4 V 1/2 100x1.0µm Conduction Factor βP 24 28 32 µA/V2 100x100µm Effective Channel Length LeffP 0.83 0.98 1.13 µm 100x1.0 µm Width Encroachment ΔW P 0.85 µm Per side Punch Through Voltage BVDSS P –7 V Poly Field Threshold VoltageVTF P(P) –10 V Diffusion & Thin Films Symbol Minimum Typical Maximum Unit Comments Well (field) Sheet ResistanceρN-well(f) 0.8 1.0 1.22 K Ω /o n-well N+ Sheet Resistance ρN+ 20 35 50 Ω /o N+ Junction Depth x jN+ 0.45 µm P+ Sheet Resistance ρP+ 60 80 100 Ω /o P+ Junction Depth x jP+ 0.5 µm Gate Oxide Thickness T GOX 20 nm Field Oxide Thickness T FIELD 700 nm Poly Sheet Resistance ρPOL Y 15 22 30 Ω /o Metal-1 Sheet Resistance ρM1 50 m Ω /o Metal-2 Sheet Resistance ρM2 30 m Ω /o Passivation Thickness T PASS 200+900 nm oxide+nit. Capacitance Symbol Minimum Typical Maximum Unit Comments Gate Oxide C ox 1.52 1.64 1.82 fF/ µm 2 Metal-1 to Poly1 C M1P 0.046 fF/ µm 2 Metal-1 to SIlicon C MIS 0.028 fF/ µm 2 Metal-2 to Metal-1 C MM 0.038 fF/ µm 2
Electrical Characteristics
T=25oC Unless otherwise noted
18 C1004-4-98
VGS = 5.0V VGS = 4.0V VGS = 3.0V VGS = 2.0V VGS = 1.0V 0 5.0 35.0 28.0 21.0 14.0 1.0 2.0 3.0 4.0 ID vs VD, W/L = 20/1.2 N-ch Transistor IV Characteristics of a 20/1.2 device 7.0 Drain Current (mA) IDS Drain Voltage (V) VDS VGS = –5.0V VGS = –4.0V VGS = –3.0V VGS = –2.0V 0 –5.0 –15.0 –12.0 –9.0 –6.0 ID vs VD, W/L = 20/1.2 P-ch Transistor IV Characteristics of a 20/1.2 device –3.0 Drain Current (mA) IDS Drain Voltage (V) VDS Starting Material P <100> N+/P+ Width/Space 2.0 / 1.2 µm Starting Mat. Resistivity 7-8.5 Ω -cm N+ To P+ Space 7.0 µm Typ. Operating Voltage 5V Contact To Poly Space 0.8 µm Well Type N-well Contact Overlap Of Diffusion 0.7 µm Metal Layers 2 Contact Overlap Of Poly 0.7 µm Poly Layers 1 Metal-1 Overlap Of Contact 0.7 µm Contact Size 1.2x1.2 µm Metal-1 Overlap Of Via 0.7 µm Via Size 1.2x1.2 µm Metal-2 Overlap Of Via 0.7 µm Metal-1 Width/Space 1.4 / 1.2µm Minimum Pad Opening 65x65 µm Metal-2 Width/Space 2.0 / 1.4µm Minimum Pad-to-Pad Spacing 5.0 µm Gate Poly Width/Space 1.0 / 1.4µm Minimum Pad Pitch 80.0 µm Metal 2 Metal 1 SIO2 LTO n+ n+ p n+ p+ p Field Oxide N-well contact Source Poly gate N-well Drain Contact Drain LDD Poly gate Sidewall spacer Source p– substrate contact Channel stop p+ substrate p–epi p+ p+ LTO Process C1004