BTD21520X BASICSEMI | Alldatasheet
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Technical content
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x
- Isolation voltage up to 5000Vrms(SOW-14)@UL1577； 3000Vrms(SOP-16)@UL1577
- Secondary-side drive voltage range up to 33V
- 4-A peak source, 6-A peak sink at output
- Integrated disable function
- Integrated dead time setting
- Typical propagation delay 45ns
- Operating temperature -40~125℃ 1.Features 2.Applications BTD21520 is an isolated dual-channel gate driver with peak 4-A source current and peak 6-A sink current.It isolates primary-side from secondary-side by a 5k Vrms reinforced isolation barrier. Internal functional isolation between the two second- ary-side output channels allows a operating voltage of up to 1850 VDC. The driver can be configured as two low- side drivers, two high-side drivers, or a half-bridge driver with programmable dead time (DT). Certain models include disable (DIS) pin. When the DIS pin is set high, it shuts down both outputs simultaneously. When the DIS pin is left open or grounded, it allows the device to oper- ate normally.Industrial:
- Power distribution
- Motor drives
- Isolated switched-mode power supplies
- Lighting systems
- Plasma displays
- PV and industrial inverters 3.Description Dual-Channel Isolated Gate Driver BTD21520x 4.Functional Block Diagram Automotive:
- On-board chargers
- Battery management systems
- Charging stations
- Traction inverters
- Hybrid electric vehicles
- Battery electric vehicles SOW-14 SOP-16 BTD21520M ISOLATION ISOLATION UVLO Level Shift and Ctrl Logic UVLO Level Shift and Ctrl Logic UVLO and input Logic VCC VCC IN1 IN2 DIS NC NC GND VDD1 OUT1 VEE1 VDD2 OUT2 VEE2 ISOLATION UVLO Level Shift and Ctrl Logic UVLO Level Shift and Ctrl Logic UVLO and input Logic VCC VCC IN1 IN2 DIS DT NC GND VDD1 OUT1 VEE1 VDD2 OUT2 VEE2
16 UVLO
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x INDEX
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x Part No. Pin Configuration Secondary Side UVLO Threshold Operating Temperature Package Package Material Quantity Marking BTD21520MAWR Dual-channel non-inverting input, dead time configuration and disable function -40-125℃ SOW-14 Tape & Reel 1500pcs /Reel BTD21520MA BTD21520MBWR 8V BTD21520MB BTD21520SAWR Dual-channel non-inverting input, disable function 6V BTD21520SA BTD21520SBWR 8V BTD21520SB BTD21520EAWR Single PWM input, dead time configuration and disable function 6V BTD21520EA BTD21520EBWR 8V BTD21520EB BTD21520MAPR Dual-channel non-inverting input, dead time configu- rtion and disable function -40-125℃ SOP-16 Tape & Reel 2500pcs /Reel BTD21520MA BTD21520MBPR 8V BTD21520MB BTD21520SAPR Dual-channel non-inverting input, disable function 6V BTD21520SA BTD21520SBPR 8V BTD21520SB BTD21520EAPR Single PWM input, dead time configuration and disable function 6V BTD21520EA BTD21520EBPR 8V BTD21520EB 5.Product Information
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x 6.Pin Configuration and Functions NO. NAME TYPE (1) DESCRIPTION PACKAGE
1 IN1 I Input signal for channel 1
2 IN2 I Input signal for channel 2
3 VCC P Primary-side supply voltage
4 GND G Primary-side ground reference
5 DIS I Disables both driver outputs if asserted high,
enables if set low or left open
6 DT I Programmable dead time function
7 NC - No Internal connection
8 VCC P Primary-side supply voltage
9 VEE2 P Ground for secondary-side driver 2
10 OUT2 O Output of driver 2
11 VDD2 P Secondary-side power for driver 2
14 VEE1 P Ground for secondary-side driver 1
15 OUT1 O Output of driver 1
16 VDD1 P Secondary-side power for driver 1
(1) P=Power, G=Ground, I=Input, O=Output
6.1 BTD21520Mx
NO. NAME TYPE (1) DESCRIPTION PACKAGE enables if set low or left open
6 NC - No Internal connection
(1) P=Power, G=Ground, I=Input, O=Output
6.2 BTD21520Sx
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x NO. NAME TYPE (1) DESCRIPTION PACKAGE
1 PWM I PWM control signal input
2 NC - No Internal connection
enables if set low or left open (1) P=Power, G=Ground, I=Input, O=Output
6.3 BTD21520Ex
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x 7.Specification Parameters
7.1 Absolute Maximum Ratings
SYMBOL PARAMETER MIN MAX UNIT VCC Input bias pin supply voltage (pin 3/pin 8) GND-0.3 GND+6.5 V VDDx Driver bias supply (to VEEx) VEEx-0.3 VEEx+35 VO Output signal voltage VEEx-0.3 VDDx+0.3 VIN Input signal voltage (INx, PWM, DIS, DT to GND) GND-0.3 VCC+0.3 - Channel to channel voltage - 1850 TJ Operating Junction Temperature -40 150 ℃TS Storage Temperature -65 150 TL Soldering Temperature (10s) - 300 ESD Human-body model (HBM) ±4000 V Charge-device model (CDM) ±1500 - Input signal voltage(IN1,IN2 Transient for 50ns) -5 VCC+0.3 Note: The above are stress levels only.Devices are not recommended to operate under these or any other conditions beyond these values.Prolonged operation under the absolute maximum rating may affect the reliability of the device, and in severe cases it may cause permanent damage to the devices.
7.2 Thermal Information
SYMBOL DESCRIPTION SOW-14 SOP-16 UNIT RθJA Junction-to-ambient thermal resistance 46.6 41.2 ℃ /W RθJC(top) Junction-to-case (top) thermal resistance 10.5 7.3 RθJB Junction-to-board thermal resistance 31.5 24.9 ψJT Junction-to-top characterization parameter 31.5 10.9 ψJB Junction-to-board characterization parameter 41.7 29.2
7.3 Power Ratings
SYMBOL PARAMETER TEST CONDITIONS SOW-14 SOP-16 UNIT PD Power dissipation by BTD21520x VCC=5V, VDD1/2=12V, IN1/2=3.3V, 3MHz, 50% duty cycle square wave, 1nF load 1.103 1.102 W PD1 Power dissipation by each driver side of BTD21520x 0.531 0.533 PD2 0.561 0.558 PDI Power dissipation by transmitter side of BTD21520x 0.011 0.011
7.4 Recommended Operation Conditions
SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT VCC Input supply voltage - 3 5 VVDDx Driver output bias supply - - 33 VIN Input voltage range IN1, IN2, PWM - 0 VCC TA Operating ambient temperature - -40 125 ℃
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x SYMBOL PARAMETER TEST CONDITIONS SIDE MIN MAX UNIT IS Safety output supply current TA=25℃ , TJ= 150℃ VDD1/2=12V OUT1, OUT2 - 75 mA VDD1/2=25V OUT1, OUT2 - 36 PS Safety supply power VDD1/2=25V, TA=25℃ , TJ=150℃ INPUT - 50 mW OUT1 - 900 OUT2 - 900 TOTAL - 1850 TS Safety temperature (1) - 150 ℃ (1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be exceeded. These limits vary with the ambient temperature, TA.
7.5 Safety-Limiting Values
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Characteristics VIH Input logic 1 (INx, DIS, PWM) VCC=5V 2.1 2.4 2.7 VVIL Input logic 0 (INx, DIS, PWM) - 1.1 1.4 1.7 VIN_HYS Input Hysteresis - - 1 - IVCC VCC quiescent current - - 1.5 2 mA IVDDx VDDx quiescent current - - 1 1.8 Primary side UVLO Thresholds (VCC) VON1 Rising threshold - - 2.6 - VVOFF1 Falling threshold - - 2.5 - VUV, HYS1 Threshold hysteresis - - 0.1 - Secondary side UVLO Thresholds (VDDx) VON2 Rising threshold BTD21520xAx - - 6 6.3 V VOFF2 Falling threshold - 5.4 5.7 - VUV, HYS2 Threshold hysteresis - - 0.3 - VON2 Rising threshold BTD21520xBx - - 8.7 9.2 VOFF2 Falling threshold - 7.8 8.2 - VUV, HYS2 Threshold hysteresis - - 0.5 - Output Characteristics IOH Peak output source current CVDD=10μF, CLOAD=0.18μF, f=1kHz - 4 - AIOL Peak output sink current - 6 - IVTS OUTx pin reverse sinking tolerance 1us pulse - 5 - VDD-VO Output voltage at high state IOUT=10mA - 60 - mV VO-VEE Output voltage at low state IOUT=-10mA - 5.5 - ROHx Output resistance at high state IOUT=10mA, TA=25℃ - 6.5 - Ω ROLx Output resistance at low state IOUT=-10mA, TA=25℃ - 0.5 - Active Pull-Down Function VOUTSD Active pull-down function, the voltage value of OUTx pin to VEEx pin in event of loss of power on VDDx IOUT=-1A, VDDx=floating - 2.5 - V
7.6 Electrical Characteristics
TA=-40~125℃ , VCC=3.3 or 5V, VDD1=VDD2=12V, CL(1) =100pF.Output pin: current towards outside of the chip is positive direction; Input pin: current towards inside of the chip is positive direction.
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x Switching Parameters tPLH Propagation delay from INx to OUTx rising edges - - 40 - ns tPHL Propagation delay from INx to OUTx falling edges - - 45 - tr Output rise time CL=1nF, 20% to 80% - 10 26 ns tf Output fall time CL=1nF, 90% to 10% - 10 26 tPWD Pulse width distortion |tPHL-tPLH| - - - 10 tDM Propagation delays matching between VOUT1, VOUT2 f=100kHz, IN1=IN2 - - 5 DT Dead time DT pull up to VCC Two output channels are completely independent - DT pin open (not recommended) - 8 15 ns RDT=20kΩ 160 200 250 tsk Delay variation between samples Under the same supply voltage, operating temperature, input and load conditions, CL=100pF - 1 25 - Undervoltage lockout recovery time tVCC+ to OUT - - 40 - µs tVDD+ to OUT - - 50 - CMTI Common-mode transient immunity INx tied to GND or VCC, VCM=1500V 100 - - kV/µs (1) CL： Load capacitance from output pin OUTx to VEEx. (Continued)
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x
7.7.1 WIDE-BODY PACKAGE (SOW-14)
Symbol PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CLR External clearance Shortest pin-to-pin distance through air 8.5 - - mm CPG External creepage Shortest pin-to-pin distance across the package surface 8.5 - - DTI Distance through insulation Minimum internal gap (internal clearance) of the double insulation (2×8.5 µm) 17 - - µm CTI Comparative tracking index DIN EN 60112 600 - - V - Overvoltage category Voltage rating ＜ 600Vrms I-III - - Voltage rating ＜ 1000Vrms I-II - - VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 - - VPK VIOWM Maximum working isolation voltage AC voltage (sine wave); time dependent dielectric breakdown 1500 - - Vrms VIOTM Maximum transient isolation voltage 100% VIOTM, 60s, 120% VIOTM, 1s 7000 - - VPK VIOSM Maximum surge isolation voltage IEC 62368-1, 1.2/50us waveform, 1.6 x VIOSM 8000 - - Qpd Apparent charge Method a, After Input/Output safety test subgroup 2/3.VIN= VIOTM, 60s, Vpd=1.2 VIOTM, 10s - - 5 pC Method a, After environmental tests subgroup 1. VIN=VIOTM, 60s, Vpd=1.6VIOTM, 10s - - 5 Method b1; At routine test (100% production) and preconditioning (type test) VIN=1.2VIOTM, 1s, Vpd=1.875VIOTM, 1s - - 5 CIO Barrier capacitance, input to output VIO=0.4Vpeak, f=1MHz, sine wave - 1.2 - pF RIO Isolation resistance, input to output Test voltage of 500V, TA=25℃ 1012 - - ΩTest voltage of 500V, 100℃＜ TA ＜ 125℃ 1011 - - Test voltage of 500V, TA=150℃ 109 - - - Pollution degree - - 2 - - VISO Withstand isolation voltage VTEST=VISO=5000Vrms, t=60 sec(qualification), VTEST=1.2×VISO=6000Vrms, t=1 sec(100% production) 5000 - - Vrms
7.7 SAFETY PARAMETERS
7.7.2 Safety-Related Certifications (SOW-14)
Component Recognition Program Plan to certify according to DIN V VDE V0884-11:2017-01 and DIN EN 61010-1 Plan to certify according to GB 4943.1-2011 Single protection, 5000 VRMS Reinforced Insulation Maximum Transient isolation Overvoltage, 7000 VPK; Maximum Repetitive Peak Isolation Voltage, 2121 VPK; Maximum Surge Isolation Voltage, 8000 VPK Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate
8.1 Propagation Delay and Pulse Width Distortion
both inputs are in phase, the dead time function is disabled by shorting the DT Pin to VCC. Figure 1. Dead Time Disabled, IN1 and IN2 with synchronized signal
8.2 Rise Time and Fall Time
Figure 2. Definition of Rise Time and Fall Time
8.3 Input and Disable Response Time
of about 1nF with low stray inductance close to the DIS pin. Figure 3. Disable Pin Timing
8.4 Programmable Dead Time
DT pin left open or connected to GND via resistor RDT sets dead time between two channels. Figure 4. Dead Time Setting
8.5 CMTI Testing
Figure 5. Simplified CMTI Test Setup
8.6 UVLO Delay During IC Power-On
ed that after powering on the driver IC, adequate time margin is reserved before sending PWM signal to IC. blocked within 1us. This asymmetric design is to ensure safe operation of a VCC or VDDx in the event of a power failure. Figure 6. UVLO delay when the VCC is powered on Figure 7. UVLO delay when the VDDx is powered on
Figure 8. Secondary side per channel current
8.7 Typical Characteristics
Figure 9. Secondary side per channel current Figure 10. Secondary side per channel current Figure 11. Secondary side per channel supply current Figure 12. Secondary side per channel quiescent Figure 13. Primary side quiescent supply current vs
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x 9.Function Description
9.1 Block Diagram
Figure 30. Functional Block Diagram (BTD21520Mx)
9.2 Input and Output Logic Table
DESCRIPTION
L L L or left open L L If dead time function is used, output switching occurs after the dead time ended.See Programmable Dead Time (DT) pinL H L or left open L H H L L or left open H L DT is left open or programmed with RDT H H L or left open H H DT pin pulled to VCC Left open Left open L or left open L L - X X H L L - Reinforced Isolation Functional IsolationDeadtime Control VCC 200k 200k 200k IN1 VCC GND DT DIS IN2 NC
10 OUT2
11 VDD2
9 VEE2
15 OUT1
3,8
14 VEE1
16 VDD1
No internal dead time setting, two output channels are inde- pendent L H L or left open L H H L L or left open H L H H L or left open H H Left open Left open L or left open L L - X X H L L - PWM INPUT DIS OUTPUT H L H L If dead time function is used, output jumps after dead time ended. See Programmable Dead Time (DT) pinL/Left open L L H X H L L Device disabled (1) "X" means L, H or left open.
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x
9.3 Input Stage Characteristics
With input pins and secondary side completely isolated, BTD21520 is designed to be compatible with CMOS levels, and supports 3.3V, 5V and 15V level input, making the chip easy to accept control of multiple logic levels.Inputs with Schmitt stage for improved anti-interference performance.INx, PWM, and DIS have a built-in 200kΩ resistor pulled down to the ground, ensuring that the output of the device is low when the input is left open However, in order to ensure the initial power-on state of the device, it is recommended to add an appropriate pull-up or pull-down resistor to the input.
9.4 Output Booster Characteristic
The BTD21520 has a rail-to-rail booster stage output. The pull-up structure of the output stage consists of a P-chan- nel MOSFET and an N-channel MOSFET connected in parallel. At turn-on, N-channel MOSFET provides high current driv- ing capability. P-channel MOSFET provides a small steady-state conduction voltage drop. The PMOS on-resistance (ROH) is 6.5Ω, and the NMOS on-resistance (RNMOS_ON) is 0.5Ω. The pull-down structure is implemented using an N-channel MOSFET. A 1MΩ resistor is connected in parallel be- tween the drain and gate of the MOSFET to effectively clamp the gate voltage of the power device in the event of a loss of pow-er to prevent the occurrence of partial turn-on.However, in order to ensure reliable shutdown of the power de- vice, it is recommended that appropriate pull-down resistor be added to the gate. Figure 31.Output Characteristics Diagram
9.5 Device Function
9.5.1 Disable
When the DIS pin is set high, both outputs can be shut down at the same time. The device operates normally when the DIS pin is grounded or left open. The response time of the disable function is within 20ns. The disable function is activated or deactivated according to the input only when the VCC is kept above the undervoltage turn-on threshold. If the DIS pin is not used, it is recommended to connect it to the ground. If connecting DIS pin to a microcontroller with distance, it is recommended to bypass the DIS pin with a low ESR/ESL capacitor of approximately 1nF for better noise immunity.
9.5.2 Pulling DT Pin Up to VCC
The two channels are independent, with output exactly matching input, and no dead time is inserted, allowing the out- put signals to be both high.
9.5.3 Dead Time Setting
DT pin sets the dead time.It is used to set the dead time between channel 1 and channel 2 to prevent them from shoot- through. The steady-state voltage of DT pin is 0.8V, and the current value of the pin is measured for corresponding dead time. The dead time is calculated as tDT=10×RDT. The unit of tDT is ns and the unit of RDT is kΩ. To ensure that the pin signal is not interfered, it is recommended to place a 2.2nF capacitor near the IC between DT pin and GND, and it is not recommended to leave DT pin open. VEE VDD Level Shifting and Control Logic ROH RNMOS_ON ROL OUT
9.5.4 BTD21520E Dead Time
A dead time elapses before OUT1 or OUT2 goes high, so as to prevent the high and low side MOSFET shoot-through. Figure 34. Logic relationship between input and output signals of BTD21520E
9.6 Protection Function
9.6.1 UVLO
low the undervoltage protection threshold after starting, the output will remain low regardless of the input state. Figure 35. Simplified Representation of Active Pulldown Feature age when the device starts to turn on/off and the operating current consumption increases abruptly. also has hysteresis feature.
Figure 36. Timing Diagram of Undervoltage Lockout Figure 37. Timing Diagram of Undervoltage Lockout Figure 38. Timing Diagram of Undervoltage Lockout
9.7 ESD Structure
The figure below shows the ESD-protected diode configuration of the input and output pins. Figure 39. ESD Structure Diagram
10.1 Typical Applications
interference and delay needs to be taken into account. CVCC, and the secondary side supply VDDx-VEEx be connected with 10μF+ 0.22μF capacitors CVDD1 and CVDD2. tion losses and reverse recovery losses contribute to the total losses in the gate driver circuit. The recommended value for RBOOT is between 1 Ω and 20 Ω depending on the diode used. Figure 40. BTD21520M Application Diagram Figure 41. BTD21520E Application Diagram
10.2 Recommended Designs
10.2.1 Recommended Design of Secondary Side Supply
ate the negative supply: Use a regulator to generate stable negative voltage, or use both positive and negative supplies. Figure 42. Voltage Regulator Design Figure 43. Dual-Supply Design
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x 1)Legend unit: mm.Note: 11.Packaging and Packing Information
11.1 Package Identifier
11.1.1 SOW-14 Package Identifier
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x
11.1.2 SOP-16 Package Identifier
This integrated circuit can be damaged by ESD. It is recommended that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution 1) Legend unit: mm.Note: °-°
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x Reel Width(W1) REEL DIMENSIONS Reel Diameter
11.2 Packing Information
11.2.1 SOW-14 Packing Information
Reel Width(W1) 12.4mm Note: 1) Legend unit: mm.
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x
11.2.2 SOP-16 Packing Information
Reel Width(W1) REEL DIMENSIONS Reel Diameter Note: 1) Legend unit: mm. ITEM FOOTPRINT Reel Diameter 13 inches Reel Width(W1) 16mm
www.basicsemi.com Rev.0.2 Dual-Channel Isolated Gate Driver BTD21520x 12.Version Description REVISION NOTES DATE Rev.0.0 Released datasheet 12-Jan-2023 Rev.0.1 Parameters extended and SOP-16 package information added 15-Dec-2023 Rev.0.2 Safety certification added 28-Mar-2024 BASiC Semiconductor Ltd. Shenzhen, China © 2023 BASiC Semiconductor Ltd. All Rights Reserved. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest BASiC Semiconductor Office Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, BASiC semiconductor Ltd. hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.