BTD21520 BASICSEMI | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 19
Technical content
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x
- Isolation voltage up to 5000Vrms
- Dual-channel isolated driver
- Primary-side supply supporting 3-18V
- Secondary-side supply supporting up to 25V
- 4-A peak source, 6-A peak sink at output
- Integrated disable function
- Integrated dead time setting function
- Propagation delay 45ns (typical)
- Operating temperature -40~125℃
- SOW-14 wide body package 1.Features 2.Applications BTD21520 is an isolated dual-channel gate driver with peak 4-A source current and peak 6-A sink current.It isolates primary-side from secondary-side by a 5k Vrms reinforced isolation barrier, and its propagation delay for turn-on/turn-off is 45ns. The wide input voltage ranged from 3V to 18V for the primary side power supply makes the driver suitable for interfacing with both digital and analog controllers. Internal functional isolation between the two second- ary-side drivers allows a operating voltage of up to 1500 VDC. The driver can be configured as two low-side driv- ers, two high-side drivers, or a half-bridge driver with programmable dead time (DT).It can also be equipped with disable (DIS) pin. When the DIS pin is set high, it shuts down both outputs simultaneously. When the DIS pin is left open or grounded, it allows the device to oper- ate normally. Industrial:
- Power distribution
- Motor control systems
- Isolated switched-mode power supplies
- Lighting systems
- Plasma displays
- PV and industrial inverters 3.Description Dual-Channel Isolated Gate Driver BTD21520x BTD21520M ISOLATION UVLO Level Shift and Ctrl Logic UVLO Level Shift and Ctrl Logic UVLO and input Iogic VCC VCC IN1 IN2 DIS NC NC GND VDD1 OUT1 VEE1 VDD2 OUT2 VEE2 ISOLATION UVLO Level Shift and Ctrl Logic UVLO Level Shift and Ctrl Logic UVLO and input Iogic VCC VCC IN1 IN2 DIS DT NC GND VDD1 OUT1 VEE1 VDD2 OUT2 VEE2 ISOLATION UVLO Level Shift and Ctrl Logic UVLO Level Shift and Ctrl Logic UVLO and input Iogic VCC VCC PWM NC DIS DT NC GND VDD1 OUT1 VEE1 VDD2 OUT2 VEE2 4.Functional Block Diagram BTD21520S ISOLATION UVLO Level Shift and Ctrl Logic UVLO Level Shift and Ctrl Logic UVLO and input Iogic VCC VCC IN1 IN2 DIS NC NC GND VDD1 OUT1 VEE1 VDD2 OUT2 VEE2 ISOLATION UVLO Level Shift and Ctrl Logic UVLO Level Shift and Ctrl Logic UVLO and input Iogic VCC VCC IN1 IN2 DIS DT NC GND VDD1 OUT1 VEE1 VDD2 OUT2 VEE2 ISOLATION UVLO Level Shift and Ctrl Logic UVLO Level Shift and Ctrl Logic UVLO and input Iogic VCC VCC PWM NC DIS DT NC GND VDD1 OUT1 VEE1 VDD2 OUT2 VEE2
16 BTD21520E
Automotive:
- On-board chargers
- Battery management systems
- Charging stations
- Traction inverters
- Hybrid Vehicles
- Battery electric vehicles
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x INDEX
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x Part No. Pin Configuration Undervoltage Threshold Temperature Package Package Material Quantity Marking BTD21520MAWR Dual-channel non-inverting input, dead time configu- rtion and disable function -40-125℃ SOW-14 Tape & Reel 1500pcs /Reel BTD21520MA BTD21520MBWR 8V BTD21520MB BTD21520SAWR Dual-channel non-inverting input, disable function 1500pcs /Reel BTD21520SA BTD21520SBWR 8V BTD21520SB BTD21520EAWR Single PWM input, dead time configuration and disable function 1500pcs /Reel BTD21520EA BTD21520EBWR 8V BTD21520EB 5.Product Information
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x 6.Pin Configuration and Functions NO. NAME TYPE (1) DESCRIPTION PACKAGE
1 IN1 I Input signal for channel 1
2 IN2 I Input signal for channel 2
3 VCC P Primary-side supply voltage
4 GND G Primary-side ground reference
5 DIS I Disables both driver outputs if asserted high,
enables if set low or left open
6 DT I Programmable dead time function
7 NC - No Internal connection
8 VCC P Primary-side supply voltage
9 VEE2 P Ground for secondary-side driver 2
10 OUT2 O Output of driver 2
11 VDD2 P Secondary-side power for driver 2
14 VEE1 P Ground for secondary-side driver 1
15 OUT1 O Output of driver 1
16 VDD1 P Secondary-side power for driver 1
(1) P=Power, G=Ground, I=Input, O=Output
6.1 BTD21520Mx
NO. NAME TYPE (1) DESCRIPTION PACKAGE enables if set low or left open
6 NC - No Internal connection
(1) P=Power, G=Ground, I=Input, O=Output
6.2 BTD21520Sx
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x NO. NAME TYPE (1) DESCRIPTION PACKAGE
1 PWM I PWM control signal input
2 NC - No Internal connection
enables if set low or left open (1) P=Power, G=Ground, I=Input, O=Output
6.3 BTD21520Ex
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x 7.Specification Parameters
7.1 Absolute Maximum Ratings
SYMBOL PARAMETER MIN MAX UNIT VCC Input bias pin supply voltage (pin 3/pin 8) GND-0.3 GND+20 V VDDx Driver bias supply (to VEEx) VEEx-0.3 VEEx+35 VO Output signal voltage VEEx-0.3 VDDx+0.3 VIN Input signal voltage (INx, PWM, DIS, DT to GND) GND-0.3 VCC+0.3 - Channel to channel voltage - 1850 TJ Operating Junction Temperature -40 150 °CTS Storage Temperature -65 150 TL Soldering Temperature (10s) - 300 ESD Human-body model (HBM) ±4000 V Charge-device model (CDM) ±1500 - Input signal voltage(IN1,IN2 Transient for 50ns) -5 VCC+0.3 Note: The above are stress levels only.Devices are not recommended to operate under these or any other conditions beyond these values.Prolonged operation under the absolute maximum rating may affect the reliability of the device, and in severe cases it may cause permanent damage to the devices.
7.2 Thermal Resistance Information
SYMBOL DESCRIPTION SOW-14 UNIT RθJA Junction-to-ambient thermal resistance 67.3 ℃ /W RθJC(top) Junction-to-case (top) thermal resistance 34.4 RθJB Junction-to-board thermal resistance 32.1 ψJT Junction-to-top characterization parameter 18.0 ψJB Junction-to-board characterization parameter 31.6
7.3 Dissipated Power
SYMBOL PARAMETER TEST CONDITIONS RATING UNIT PD Power dissipation by BTD21520x VCC=18V, VDD1/2=12V, IN1/2=3.3V, 3MHz, 50% duty cycle square wave, 1nF load 1.05 WPDI Power dissipation by transmitter side of BTD21520x 0.05 PD1, PD2 Power dissipation by each driver side of BTD21520x 0.5
7.4 Recommended Operation Conditions
SYMBOL PARAMETER MIN MAX UNIT VCC Input supply voltage 3 18 V VDDx Driver output bias supply BTD21520xAx 6.5 25 BTD21520xBx 9.2 25 VIN Input Voltage Range IN1, IN2, PWM 0 VCC V TA Operating ambient temperature -40 125 ℃
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Characteristics VIH Input logic 1 (IN1, IN2, DIS, PWM) - 2.1 2.4 2.7 VVIL Input logic 0 (IN1, IN2, DIS, PWM) - 1.1 1.4 1.7 VIN_HYS Input Hysteresis - - 1 - IIH High-level input leakage at INx or PWM Input voltage is VCC - 650 - uA IIL Low-level input leakage at INx or PWM Input voltage is GND - - 5 Input voltage is GND-5V -310 -80 - IVCC VCC quiescent current - - 2 2 mA IVDDx VDDx quiescent current - - 1 1.8 Primary side undervoltage lockout (VCC) VON1 Rising threshold voltage - - 2.6 - VVOFF1 Falling threshold voltage - - 2.5 - VUV, HYS1 Threshold hysteresis - - 0.1 - Secondary side undervoltage lockout (VDDx) VON2 Rising threshold voltage BTD21520xAx - - 6 6.3 V VOFF2 Falling threshold voltage - 5.4 5.7 - VUV, HYS2 Threshold hysteresis - - 0.3 - VON2 Rising threshold voltage BTD21520xBx - - 8.7 9.2 VOFF2 Falling threshold voltage - 7.8 8.2 - VUV, HYS2 Threshold hysteresis - - 0.5 - Output Characteristics IO+ Peak output source current CVDD=10μF, CLOAD=0.18μF, f=1kHz - 4 - AIO- Peak output sink current - 6 - IVTS OUTx pin reverse sinking tolerance 1us pulse - 5 - VDD-VO Output voltage at high state IOUT=10mA - 60 - mV VO-VEE Output voltage at low state IOUT=-10mA - 5.5 - ROHx Output resistance at high state IOUT=10mA, TA=25℃ - 6.5 - Ω ROLx Output resistance at low state IOUT=-10mA, TA=25℃ - 0.5 - Active Pull-Down Function VOUTSD Active pull-down function, the voltage value of OUTx pin to VEEx pin in event of loss of power on VDDx IOUT=-1A (current sinking into OUTx pin), VDDx=floating - 1.8 2.5 V
7.6 Electrical Characteristics
TA=-40~125℃ , VCC=3.3 or 5V, VDD1=VDD2=12V, CL(1) =100pF.Output pin: current towards outside of the chip is positive direction; Input pin: current towards inside of the chip is positive direction. SYMBOL PARAMETER TEST CONDITIONS CORRESPONDING FUNCTIONS MIN MAX UNIT IS Safety output supply current RθJA=67.3° C/W, TA=25° C, TJ= 150° C VDD1/2=12V OUT1, OUT2 - 75 mA VDD1/2=25V OUT1, OUT2 - 36 PS Safety supply power RθJA=67.3° C/W, VDD1/2=25V, TA=25° C, TJ=150° C INPUT - 50 mW OUT1 - 900 OUT2 - 900 TOTAL - 1850 TS Safety temperature (1) - 150 ℃ (1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device.The IS and PS parameters represent the safety current and safety power respectively.The maximum limits of IS and PS should not beexceed- ed.These limits vary with the ambient temperature, TA.
7.5 Safety-Limiting Values
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x (Continued) Switching Parameters tPLH Propagation delay from INx to OUTx rising edges - - 40 - ns tPHL Propagation delay from INx to OUTx falling edges - - 45 - tr Output rise time CL=1nF, 20% to 80% - 10 26 ns tf Output fall time CL=1nF, 90% to 10% - 10 26 tPWD Pulse width distortion (tPHL-tPLH) - - - 5 tDM Propagation delays matching between VOUT1, VOUT2 f=100kHz, IN1=IN2 - - 5 DT Dead time DT pull up to VCC Two output channels are completely independent - DT pin open (not recommended) - 8 15 ns RDT=20kΩ 160 200 240 - Undervoltage lockout recovery time tVCC+ to OUT - - 40 - us tVDD+ to OUT - - 50 - CMTI Common-mode transient immunity INx fixed to GND or VCC, VCM=1500V 100 - - kV/us (1) CL： Load capacitance from output pin OUT to VEE.
7.7 WIDE-BODY PACKAGE (SOW-16) SAFETY PARAMETERS
Symbol PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CLR External clearance Shortest pin-to-pin distance through air 8.5 - - mm CPG External creepage Shortest pin-to-pin distance across the package surface 8.5 - - DTI Distance through insulation Minimum internal gap (internal clearance) of the double insulation (2×10.5 µm) 17 - - um CTI Comparative tracking index DIN EN 60112 600 - - V - Overvoltage category Voltage rating ＜ 600Vrms I-III - - Voltage rating ＜ 1000Vrms I-II - - VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 - - VPK VIOWM Maximum working isolation voltage AC voltage (sine wave); time dependent dielectric breakdown 1500 - - Vrms VIOTM Maximum transient isolation voltage 100% VIOTM, 60s, 120% VIOTM, 1s 7000 - - VPK VIOSM Maximum surge isolation voltage IEC 62368-1, 1.2/50us waveform, 1.6 x VIOSM 8000 - - Qpd Apparent charge Method a, After Input/Output safety test subgroup 2/3.VIN= VIOTM, 60s, Vpd=1.2 VIOTM, 10s - - 5 pC Method a, After environmental tests subgroup 1. VIN=VIOTM, 60s, Vpd=1.6VIOTM, 10s - - 5 Method b1; At routine test (100% production) and preconditioning (type test) VIN=1.2VIOTM, 1s, Vpd=1.875VIOTM, 1s - - 5 CIO Barrier capacitance, input to output VIO=0.4Vpeak, f=1MHz, sine wave - 1.2 - pF RIO Isolation resistance, input to output Test voltage of 500V, TA=25℃ 1012 - - ΩTest voltage of 500V, 100℃＜ TA ＜ 125℃ 1011 - - Test voltage of 500V, TA=150℃ 109 - - VISO Pollution degree - - 2 - - Withstand isolation voltage VTEST=VISO=5000Vrms, t=60 sec(qualification), VTEST=1.2×VISO=6000Vrms, t=1 sec(100% production) 5000 - - Vrms
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x 8.Parameter Testing
8.1 Propagation Delay and Pulse Width Distortion
The figure below shows the characterization of pulse width distortion (tPWD) and delay matching (tDM).During the test, the two inputs are synchronized while the DT pin is connected to the VCC to disable the dead time. Figure 1.Dead Time Disabled, IN1 and IN2 with synchronized signal
8.2 Rise Time and Fall Time
Figure 2.Definition of Rise Time and Fall Time
8.3 Input and Disable Response Time
When the DIS pin is connected to the controller at a certain distance, it is recommended to configure a bypass capacitor of about 1nF with low stray inductance close to the DIS pin. Figure 3.Disable Pin Timing
8.4 Programmable Dead Time
DT pin left open or connected to GND via resistor RDT sets dead time between two channels. Figure 4.Dead Time Setting tPLH1 tPLH2 tDM tPWD2= tPLH2-tPHL2 tPHL2 tPHL1 IN1/IN2 OUT1 OUT2 tf 90% 10% tr 20% 80% DIS High Response Time DIS Low Response Time tPHL tPLH IN1 DIS OUT1 OUT2 OUT1 IN2 IN1 t tPHL tPHL tPLH Dead Time (set by RDT) Dead Time (Determined by Input signals if longer than DT set by RDT) 90% 10% 90% tON1 tON2 tDM tPWD2= tON2-tOFF2 tOFF2 tOFF1 IN1/IN2 OUT1 OUT2 tf 90% 10% tr 20% 80% DIS High Response Time DIS Low Response Time tOFF tON IN1 DIS OUT1 V t OUT2 OUT1 IN2 IN1 V t tOFF tOFF tON Dead Time (set by RDT) Dead Time (Determined by Input signals if longer than DT set by RDT) tPLH1 tPLH2 tDM tPWD2= tPLH2-tPHL2 tPHL2 tPHL1 IN1/IN2 OUT1 OUT2 tf 90% 10% tr 20% 80% DIS High Response Time DIS Low Response Time tPHL tPLH IN1 DIS OUT1 OUT2 OUT1 IN2 IN1 t tPHL tPHL tPLH Dead Time (set by RDT) Dead Time (Determined by Input signals if longer than DT set by RDT) 90% 10% 90% 50% 50% 90% 10%10% 90% 50% 50% 50% 50% 10% tPLH1 tPLH2 tDM tPWD2= tPLH2-tPHL2 tPHL2 tPHL1 IN1/IN2 OUT1 OUT2 tf 90% 10% tr 20% 80% DIS High Response Time DIS Low Response Time tPHL tPLH IN1 DIS OUT1 OUT2 OUT1 IN2 IN1 t tPHL tPHL tPLH Dead Time (set by RDT) Dead Time (Determined by Input signals if longer than DT set by RDT) 90% 10% 90% 50% 50% 90% 10%10% 90% 50% 50% 50% 50% 10%
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x
8.5 CMTI Testing
Figure 5.Simplified CMTI Test Setup
8.6 UVLO Delay During IC Power-On
At the process of device power-on, there is a time delay from the start of the supply voltage rise to the UVLO recovery threshold, and then to the device output response, as shown in the figures below.tVCC+ to OUT is primary side power-on UVLO delay (typical value 40us), and tVDD + to OUT is secondary side power-on UVLO delay (typical value 50us).It is suggest- ed that after powering on the driver IC, adequate time margin is reserved before sending PWM signal to IC.If IN1 or IN2 is already at high level before VCC or VDDx reaches the recovery threshold, after tVCC+ to OUT or tVDD+ to OUT counting from the time point when VCC or VDDx reaches the recovery threshold, the corresponding output will jump to a high level.How- ever, when the VCC or VDDx voltage drops to the UVLO lockout threshold, the output will be completely blocked within 1us.This asymmetric design is to ensure safe operation of a VCC or VDDx in the event of a power failure. Figure 6-1.UVLO delay when the VCC is powered on Figure 6-2.UVLO delay when the VDDx is powered on Functional Isolation Isolation barrier VCC VDD VCC Input Logic Common Mode Surge Generator IN1 1 2IN2 GND DIS DT VCC 3VCC VDD1 OUT1 VDD2 OUT2 VEE2 VEE1 VEE OUT1 OUT2 VCC,INx OUT VDD tVCC+ to OUT VVCC-ON VVCC-OFF VCC,INx OUTx VDDx tVDD+ to OUT VVDD-ON VVDD-OFF
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x 9.Function Description
9.1 Block Diagram
Figure 7.Block Diagram
9.2 Input and Output Logic Table
When VCC and VDD are powered on, the relevant input and output logic information is as follows: BTD21520M BTD21520S BTD21520E INPUT DIS OUTPUT
DESCRIPTION
L L L or left open L L If dead time function is used, output switching occurs after the dead time ended.See Programmable Dead Time (DT) pinL H L or left open L H H L L or left open H L Dead time stay open or programmed with RDT H H L or left open H H Dead time pin pulled to VCC Left open Left open L or left open L L - X X H L L - Reinforced Isolation Functional Isolation MOD De adti me Control MOD VCC 20 0k 20 0k 20 0k IN1 VCC GND DT DIS IN2 NC
10 OUT2
11 VDD2
9 VEE2
15 OUT1
3,8
14 VEE1
16 VDD1
No internal dead time setting, two output channels are inde- pendent L H L or left open L H H L L or left open H L H H L or left open H H Left open Left open L or left open L L - X X H L L - PWM INPUT DIS OUTPUT H L H L If dead time function is used, output jumps after dead time ended. See Programmable Dead Time (DT) pinL/Left open L L H X H L L Device disabled (1) "X" means L, H or left open.
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x
9.3 Input Stage Characteristics
With input pins and secondary side completely isolated, BTD21520 is designed to be compatible with CMOS levels, and supports 3.3V, 5V and 15V level input, making the chip easy to accept control of multiple logic levels.Inputs with Schmitt stage for improved anti-interference performance.INx, PWM, and DIS have a built-in 200kΩ resistor pulled down to the ground, ensuring that the output of the device is low when input left open. However, in order to ensure the initial pow- er-on state of the device, BASiC recommends adding an appropriate pull-up or pull-down resistor to the input.
9.4 Output Booster Characteristic
The BTD21520 has a rail-to-rail booster stage output. The pull-up structure of the output stage consists of a P-channel MOSFET and an N-channel MOSFET connected in parallel. At turn-on, N-channel MOSFET provides high current driving capability. P-channel MOSFET provides a small steady-state conduction voltage drop during steady conduction. The PMOS on-resistance (RPMOS_ON ) is 6.5Ω, and the NMOS on-resistance (RNMOS_ON ) is 0.5Ω. The pull-down structure is implemented using an N-channel MOSFET. A 1MΩ resistor is connected in parallel between the drain and gate of the MOSFET to effectively clamp the gate voltage of the power device in the event of a loss of pow- er on the chip to prevent the occurrence of partial turn-on.However, in order to ensure reliable shutdown of the power device, BASiC recommends that appropriate pull-down resistor be added to the gate. Figure 8.Output Characteristics Diagram
9.5 Device Function
9.5.1 Disable
When the DIS pin is set to a high level, both outputs can be shut down at the same time. The device operates normally when the DIS pin is grounded or left open. The response time of the disable function is within 20ns. The disable function is activated or deactivated according to the setting only when the VCC is kept above the undervoltage turn-on threshold. If the DIS pin is not used, it is recommended to connect it to the ground. If connecting DIS pin to a microcontroller with distance, it is recommended to bypass the DIS pin with a low ESR/ESL capacitor of approximately 1nF for better noise immunity.
9.5.2 Pulling DT Pin Up to VCC
The two channels are independent, with output exactly matching input, and no dead time is inserted, allowing the out- put signals to be both high.
9.5.3 Dead Time Setting
DT pin sets the dead time.It is used to set the dead time between channel 1 and channel 2 to prevent them from shoot- through. The steady-state voltage of DT pin is 0.8V, and the current value of the pin is measured for corresponding dead time. The dead time is calculated as TDT=10×RDT. The unit of tDT is ns and the unit of RDT is kΩ. To ensure that the pin signal is not interfered, it is recommended to place a 2.2nF capacitor near the IC between DT pin and GND, and it is not recommended to left DT pin open. VEE VDD Level Shifting and Control Logic RPMOS_ON RNMOS_ON ROL OUT
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x
9.5.4 BTD21520E Dead Time
A dead time elapses before OUT1 or OUT2 goes high, so as to prevent the high and low side MOSFET shoot-through. Figure 10.Logic relationship between input and output signals of BTD21520E
9.6 Protection Function
9.6.1 UVLO
There is an internal undervoltage lock-out (UVLO) on the power circuit function area between VDDx and VEE pins of two out-puts.When the voltage of VDD is below the undervoltage recovery threshold before starting, or be- low the undervoltage protection threshold after starting, the output will remain low regardless of the input state. When the output of the driver is in powered-off or undervoltage state, its output is clamped to the low level by the ac- tive clamping circuit, as shown in the figure below.At this time, the PMOS of the high side is blocked and high imped- ance, and the NMOS gate of the low side is connected to the output of the driver by the resistor RCLAMP.In the absence of bias voltage, the output is effectively clamped to the threshold voltage of the low-side NMOS device, typically around 1.5V (see Figure 11-1). Figure 11-1 Simplified Representation of Active Pulldown Feature The VDDx undervoltage protection has a VVDD_HYS feature that prevents vibration in the presence of noise from the power supply to ground. This also allows the device to accept a small decrease in bias volt - age when the device starts to turn on/off and the operating current consumption increases abruptly. Like the VDDx, there is also an undervoltage lock-out (UVLO) integrated on the primary side of the VCC.When the bias voltage is applied to the VCC terminal and the voltage is lower than the undervoltage turn-on threshold, the device will not be activated.After the activation of the device, if the VCC voltage continuously decreases to the undervoltage turn- off threshold, the signal will stop transmission.Like the undervoltage lockout of VDD, the undervoltage lockout of VCC also has hysteresis feature. DT OUT2 OUT1 PWM VEE VDD Output Control RCLAMP OUT RCL AMP is activated During UVLO
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x Figure 11-2-1. Timing Diagram of Undervoltage Lockout Figure 11-2-2. Timing Diagram of Undervoltage Lockout Figure 11-2-3. Timing Diagram of Undervoltage Lockout
9.7 ESD Structure
The figure below shows the ESD-protected diode configuration of the input and output pins. Figure 12.ESD Structure Diagram IN2 VCC-GND OUT1 VON1 VOFF1 IN1 OUT2 IN2 VDD1-VEE1 OUT1 VON2 VOFF2 IN1 OUT2 IN2 VDD2-VEE2 OUT2 VON2 VOFF2 OUT1 IN1 tVCC+ to OUT tVCC+ to OUT tVDD1+ to OUT tVDD2+ to OUT IN2 VCC-GND OUT1 VON1 VOFF1 IN1 OUT2 IN2 VDD1-VEE1 OUT1 VON2 VOFF2 IN1 OUT2 IN2 VDD2-VEE2 OUT2 VON2 VOFF2 OUT1 IN1 tVCC+ to OUT tVCC+ to OUT tVDD1+ to OUT tVDD2+ to OUT IN2 VCC-GND OUT1 VON1 VOFF1 IN1 OUT2 IN2 VDD1-VEE1 OUT1 VON2 VOFF2 IN1 OUT2 IN2 VDD2-VEE2 OUT2 VON2 VOFF2 OUT1 IN1 tVCC+ to OUT tVCC+ to OUT tVDD1+ to OUT tVDD2+ to OUT 3,8 IN1 IN2 GND VCC DIS DT VEE2 VDD2 OUT2 VDD1 VEE1 OUT1
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x 10.Applications The following sections introduce the basic typical application of BASiC driver ICs, which is for reference only. In practi- cal application, users need to verify and test its applicability according to their own design requirements to confirm the system function.
10.1 Typical Applications
BASiC recommends that customers add a RC filter with a small time constant at the input port to filter out high-frequen- cy interference without adding a large delay. It is recommended that the resistance value should be between 0 and 100Ω and the capacitance should be less than 1000pF. When setting this parameter, the influence between high frequency interference and delay needs to be taken into account. To ensure the supply stability, BASiC recommends adding an appropriate capacitor between the power supply and ground. It is recommended that the primary side supply VCC-GND be connected in parallel with 1uF+ 0.1uF capacitor CVCC, and the secondary side supply VDD-VEE be connected with 10uF+ 0.22uF capacitors CVDD1 and CVDD2. The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation in the bootstrap diode may be significant. Conduction loss also depends on the diode’ s forward voltage drop. Both the diode conduc- tion losses and reverse recovery losses contribute to the total losses in the gate driver circuit. The recommended value for RBOOT is between 1 Ω and 20 Ω depending on the diode used. Figure 13-1.BTD21520M Application Diagram Figure 13-2.BTD21520E Application Diagram Reinforced Isolation RBOOT RGS RON ROFF DGATE CVDD1 SW VDD VDD1 OUT1 VEE1 HV DC-Link CIN Input Logic Functional Isolation RGS RON ROFF DGATE CVDD2 VDD VDD2 OUT2 VEE2 PWM VCC RIN VCC VCC PWM GND DIS DT VCC Analog or Digital Disable RDIS CDIS RT CDT 2.2nF CIN CVCC Reinforced Isolation RGS RON ROFF DGATE CVDD1 SW VDD VDD1 OUT1 VEE1 HV DC-Link CIN Input Logic Functional Isolation RGS RON ROFF DGATE CVDD2 VDD VDD2 OUT2 VEE2 VEE IN1 VCC RIN VCC GND DIS DT VCC Disable RDIS CDIS RT CDT 2.2nF CIN CVCC IN2 2 VCC PWM1 PWM2 Analog or Digital RBOOT VEE VEE VEE Reinforced Isolation RBOOT RGS RON ROFF DGATE CVDD1 SW VDD VDD1 OUT1 VEE1 HV DC-Link CIN Input Logic Functional Isolation RGS RON ROFF DGATE CVDD2 VDD VDD2 OUT2 VEE2 PWM VCC RIN VCC VCC PWM GND DIS DT VCC Analog or Digital Disable RDIS CDIS RT CDT 2.2nF CIN CVCC Reinforced Isolation RGS RON ROFF DGATE CVDD1 SW VDD VDD1 OUT1 VEE1 HV DC-Link CIN Input Logic Functional Isolation RGS RON ROFF DGATE CVDD2 VDD VDD2 OUT2 VEE2 VEE IN1 VCC RIN VCC GND DIS DT VCC Disable RDIS CDIS RT CDT 2.2nF CIN CVCC IN2 2 VCC PWM1 PWM2 Analog or Digital RBOOT VEE VEE VEE
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x
10.2 Recommended Designs
10.2.1 Recommended Design of Secondary Side Supply
In order to avoid partial turn-on of the gate of the power device due to interference, it is recommended that customers add a negative supply when designing the driving output.It is recommended to use the following two methods to gener- ate the negative supply: use a regulator to generate stable negative voltage, or use both positive and negative supplies. Figure 14-1 Voltage Regulator Design Figure 14-2.Dual-Supply Design VDDx OUTx VEEx CA2 CA1 RZ RGON 20V VDDx OUTx VEEx CA1 RGON VEE VEE VEE VDDx OUTx VEEx CA2 CA1 RZ RGON 20V VDDx OUTx VEEx CA1 RGON VEE VEE VEE
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x 11.Package Identifier
11.1 SOW-14 Package Identifier
°° This integrated circuit can be damaged by ESD.BASiC recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution 1)Legend unit: mm.Note:
www.basicsemi.com Rev.0.0 Dual-Channel Isolated Gate Driver BTD21520x 12.Version Description Document Version Date of Release Description of Changes Rev.0.0 2023-01-12 Draft datasheet created. BASiC Semiconductor Ltd. Shenzhen, China © 2023 BASiC Semiconductor Ltd. All Rights Reserved. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest BASiC Semiconductor Office Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, BASiC semiconductor Ltd. hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.