BLV7002 BELLING | Alldatasheet
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Logic level translator. Size structure Planar type Electrodes: Aluminum alloy Backside metal: Au alloy Chip size: 495 µm ×490 µm Chip thickness: 220±20 µm. Scribe street width: 50 µm Pad size: 90 µm x90 µm Die per wafer: 25800 ABSOLUTE MAXIMUM RATING Symbol Parame ter Min. Max. Unit VDS Drain – source voltage (DC) - 60 V VGS Gate – source voltage (DC) - ±20 V ID Drain current (DC) - 115 mA ID M Peak drain current - 0.46 A Ptot Total p ower dissipation - 0.2 W TSTG Storage temperature -55 +150 oC Tj Junction tem perature - 150 oC
http://www.belling.com.cn - 2 - 8/18/2006 Total 2 Pages CHARACTERISTICS Tj = 25 oC unless otherwise specified Symbol Parameter Test conditions Min. Typ. Max. Unit BV DSS Drain -source breakdown voltage VGS =0V,I D =250 µ A 60 73 - V IDSS Drain -source leakage current VDS =6 0V, V GS =0V - 1 500 nA I GSS Gate -source leakage current VGS =+20 V, VDS =0V - 1 ±100 nA VGSth Gate -source threshold voltage VDS =2. 5V , ID =250u A 1 - 2.5 V R DS on Drain -source on -state resistance VGS =10V ,I D =100mA - 1.3 5 Ω C iss Input capacitance - - 50 pF C os s Output capacitance - - 25 pF C rss Reverse transfer capacitance VDS =25V ，VGS =0V f =1MHz - - 5 pF ton Turn-On time - - 30 ns toff Turn-Off time VDD =30V, I D =200mA VGS =0-10V - - 30 ns PATTERN DRAWING