BL6523B

BL6523B BELLING | Alldatasheet

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BL6523B Single Phase, Multifunction Energy meter IC 1/30 v1.0  FEATURES  High accuracy, less than 0.1% error over a dynamic range of 3000:1  High stability, less than 0.1% error in the output frequency fluctuation  Measure the active power in the positive orientation and negative orientation, transform to fast pulse output(CF）  Provide two current input for line and neutral current measurement  Mesure instantaneous IRMS and VRMS over a dynamic range of 1500:1  Provide SAG detection and Phase failure detection  On-chip power supply detector  On-chip anti -creep protection with the programmable threshold set  Provide the pulse output with programmable frequency adjustment  Provide the programmable gain adjustment and phase compensation  Measure the power factor (PF）  Provide a programmable interrupt request signal （/IRQ）  Provide a SPI communication interface  On-chip voltage reference of 2.5V  Single 5V supply, 25mW（typical） Interralated patents are pending  DESCRIPTION The BL6523B is a low cost, high accuracy , high stability, electrical energy measurement IC intended to single phase, multifucion applications. The BL6523B incorporates three high accuracy Sigma-Delta ADC , voltage reference, power management and digital signal process ing circuit using to calculates active energy, apparent energy, IRMS, VRMS etc. The BL6523B have two current input for line and neutral current measurement, when these currents differ by more than the programmable Fault threshold value (RMS or WA TT), the BL6523B give the tamper indicator and can enable neutral current billing, The BL6523B measures line voltage, current and calculates active, apparent energy, power factor, line frequency, detect sag, overvoltage, overcurrent, peak, reverse power, zero-crossing voltage. The BL6523B provides access to on -chip meter registers via SPI communication interface. The BL6523B provide all -digital domain offset compensation, gain adjustment, phase compensation (maximum ±2.54° adjustable）.  BLOCK DIAGRAM AVDD IAP IAN IBP IBN VP VN VREF AGND DGND DVDD /RST CF DIN DOUT SCLK /CS CLKOUT CLKIN /IRQ BL6523B PGA ADC DSP SPI Irms,VrmsIAP IAN IBP VP VN SCLK /CS CLKOUT CLKIN ClockVoltage Ref VREF ADC Logic output DOUT DINPGA BL6523B AGNDSSOP24 AT0 AT1 AT3 AT2 IBN PF A_WATT,B_WATT,VA WattHR/VAHR Fault detector Peak detector Sag detector Interrupt detector AT1 AT0 AT2 AT3 AVDD DVDD Power detector /RST DGND CF interrupt /IRQ PGA ADC PIN DESCRIPTIONS（SSOP24）

BL6523B Single Phase, Multifunction Energy meter IC 2/30 v1.0 Pin Symbol DESCRIPTIONS 1 A VDD Power Supply (+5V). Provides the supply voltage for the circuitry. It should be maintained at 5 V±5% for specified operation. 2，3， 4，5 IAP，IAN， IBP，IBN Analog input for current channel , These inputs are fully differential voltage inputs with a maximum signal level of ±660 mV, Adjustable Gain. 6，7 VP，VN Negative and Positive Inputs for V oltage Channel. These inputs provide a fully differential input pair. The maximum differential input voltage is ± 750 mV for specified operation.Adjustable Gain. 8 VREF On-Chip V oltage Reference. The on-chip reference has a nominal value of 2.5V ± 8% and a typical temperature coefficient of 30ppm/℃. An external reference source may also be connected at this pin. 9 AGND Ground Reference. Provides the ground reference for the circuitry.

10 DGND Digital Ground

11，12， 13，14 AT0，A T1， AT2，A T3 Programmable digital output. See A T_SEL register section. Default output:AT0=FAULT、AT1=REVP、A T2=ZX、A T3=nSAG。 15 /IRQ Interrupt output. 16 CLKIN Clock In. An external clock can be provided at this logic input, Alterrnatively, a crystal (3.58MHz) can be connected across this pin and pin17 to provide a clock source. 17 CLKOUT Clock out. A crystal can be connected across this pin and Pin16 as described above to provide a clock source. 18 /CS Chip select for SPI interface. This pin must be pulled low if using the SPIinterface. 19 SCLK Serial clock input for the synchronous serial interface. All serial communication data are synchronized to the clock. 20 DOUT Data output for SPI interface. Data is shifted out at this pin on the rising edge of SCLK. This output is normally in a high impedance state, unless it is driving data out to the serial data bus. 21 DIN Data input for SPI interface. Data is shifted in at this pin on the rising edge of SCLK 22 CF Calibration Frequency. The CF logic output gives instantaneous real power information. This output is intended to use for calibration purposes. The full-scale output frequency can be scaled by the value of WA_CFDIV register. When the power is low, the pulse width is equal to 90ms. When the power is high and the outpu t period less than 180ms, the pulse width equals to half of the output period. 23 /RST Reset Pin. Logic low on this pin will hold the ADCS and digital circuitry in a reset condition and clear internal registers.

24 DVDD DiDigital Power Supply （+5V）,provides the supply voltage for the digital

circuitry. It should be maintained at +4.75V~+5.25V for specified operation

BL6523B Single Phase, Multifunction Energy meter IC 3/30 v1.0  Package Dimensions  ABSOLUTE MAXIMUM RATIONS （T = 25 ℃） Parameter Symbol Value 单位 Power V oltage AVDD、DVDD AVDD、DVDD -0.3 ~ +7 V Analog Input V oltage to AGND IAP、IBP、VP -6 ~ +6 V Digital Input V oltage to DGND DIN、SCLK、/CS -0.3 ~ VDD+0.3 V Digital Output V oltage to DGND CF、AT0、AT1、AT2、A T3 /IRQ、DOUT -0.3 ~ VDD+0.3 V Operating Temperature Range Topr -40 ~ +85 ℃ Storage Temperature Range Tstr -55 ~ +150 ℃ Power Dissipation（SSOP24） P 80 mW  Electronic Characteristic Patameter （AVDD = DVDD = 5V, AGND＝DGND＝0V, CLKIN=3.58MHz, T=25℃） Parameter Symbol Test Condition Measure Pin Min Value Typical Value Max Value Unit Measure Error on Active Power WATTerr Over a dynamic range 3000:1 CF 0.1 0.3 % Phase error when PF=0.8 Capacitive PF08err Current lead 37° （PF=0.8） 0.5 % Phase error when PF=0.5Inductive PF05err Current lags 60° （PF=0.5） 0.5 % AC PSRR ACPSRR IP/N=100mV 0.01 %

BL6523B Single Phase, Multifunction Energy meter IC 4/30 v1.0 DC PSRR DCPSRR VP/N=100mV 0.1 % Vrms measurement Error VRMSerr 1500:1 input DR 0.3 % Irms measurement Error IRMSerr 1500:1 input DR 0.3 % Maximum Input voltage ± 1200 mV DC Input V oltage 370 kΩ Input Signal Bandwidth （-3dB） 14 kHz Gain Error External 2.5V reference -4 +4 % Gain Error match External 2.5V reference -1.5 +1.5 % On-chip reference Vref VREF 2.5 V Reference Error Vreferr ± 200 mV Temperature Coefficient TempCoef 30 ppm/℃ Input High V oltage DVDD=5V± 5% 2.6 V Input Low V oltage DVDD=5V± 5% 0.8 V Output High V oltage DVDD=5V± 5% 4 V Output Low V oltage DVDD=5V± 5% 1 V Analog Power A VDD V A VDD 4.75 5.25 V Digital Power DVDD VDVDD 4.75 5.25 V AIDD IA VDD A VDD=5.25V 3 mA DIDD IDVDD DVDD=5.25 2 mA

BL6523B Single Phase, Multifunction Energy meter IC 5/30 v1.0  THEORY OF OPERATION HPF × LPF × + x² LPF root+ A_WATT IA_RMS ʃP PWAHR IA_WAVE V_WAVE SINC4ADCLNAIAP IAN Phase + ʃN NWAHR ANTI- CREEP WA_CREEP × × VAGN + ʃ VAHR VA IA_RMSGN RMS_CREEP WA_LOS_L ANTI- CREEP IA_RMSOS VAOS GAIN[3:0] IA_PHCAL IA_CHOSIA_CHGN V_CHGN A_WATTOS A_WATTGN BL6523B System Block GAIN[7:4] GAIN[11:8] IB_PHCAL V_PHCAL HPFSINC4ADCLNAVP VN Phase +× V_CHOS HPFSINC4ADCLNAIBP IBN Phase +× IB_CHOSIB_CHGN IB_WAVE IA_WAVE x² LPF root+ IB_RMS× IB_RMSGN RMS_CREEP ANTI- CREEP IB_RMSOS IB_WAVE x² LPF root+ V_RMS× V_RMSGN RMS_CREEP ANTI- CREEP V_RMSOS V_WAVE WA_REVP × LPF × +ANTI- CREEP WA_LOS_H B_WATTGN B_WATTOS IA_WAVE V_WAVE IB_WAVE ʃ(P+N WATTHR ʃT(P+N ) LINE_WATTHR B_WATT WA_CFDIV ÷ CF IA_RMS IB_RMS V_RMS ÷ PF PEAK IA_PEAK PEAK V_PEAK PEAK IB_PEAK LINECYC FAULT IA_RMS IB_RMS COMP A_WATT B_WATT COMP  Principle of Energy Measure

BL6523B Single Phase, Multifunction Energy meter IC 6/30 v1.0 In energy measure, the power information varying with time is calculated by a direct multiplication of the voltage signal and the current signal. Assume that the current signal and the voltage signal are cosine functions, V ,I are the peak values of the voltage signal and the current signal; the phase difference between the current signal and the voltage signal is expressed as Ф,Then the power is given as follows: )cos()cos()(  wtIwtVtp If  =0 时： )2cos(1(2)( wtVItp  If  0 时：   )sin()2sin(2)cos())2cos(1(2 )sin()sin()cos()cos())2cos(1(2 )sin()sin()cos()cos()cos( )cos()cos()(  wtVIwtVI wtwtVIwtVI wtwtIwtV wtIwtVtp p(t) is called as the instantaneous power signal. The ideal p(t) consists of the DC component and AC component whose frequency is 2ω. The DC component is called as the average active power. The current signal and voltage signal is converted to digital signals by high-precsion ADCS, then through the drop sampling filter (SINC4), high-pass filter (HPF) filter out the high frequency noise and DC gain, get the required current and voltage sampling data. Current sampling data multiplied by voltage sampling data gets instantaneous active power, then through the low pass filter (LPF), output average active power. Current sampling data and voltage sampling data processed by square circuit, low -pass filter( LPF1), square root circuit, get the current RMS and voltage RMS. Active power through a certain time integral, get active energy.  Front-end gain adjustment Every analog channel has a programmable gain amplifier (PGA), gain selection is achieved by the gain register (GAIN), the default value of the gain register (GAIN) is 000H. Every 4-bit of the gain register used to select the current channel or voltage channel PGA. Gain[3:0] used to select Current A channel PGA,Gain[7:4] used to select Current B channel PGA, Gain[11:8] used to select V oltage channel PGA. For example Gain [3:0]: x000=1x x001=2x x010=4x x011=8x x100=16x x101=24x x110=32x x111=32x

BL6523B Single Phase, Multifunction Energy meter IC 7/30 v1.0  Phase compensation BL6523B provides the method of small phase error digital calibration. It will be a small time delay or advance into signal processing circuit in order to compensate for small phase error . Because this compensation should be promptly, so this method applies only to 0.1~0.5 range of small phase error. Phase calibration register (IA_PHCAL、IB_PHCAL、V_PHCAL) is a binary 8 -bit register, corresponding to the compensation current A channel, current B channel and voltage channel phase. The default value is 00H. Bit[7] is enable bit, when Bit [7]＝0,disable compensation;Bit[7] ＝1,enable compensation. Bit[6:0] used to adjust the delay time ，1.1us/1LSB. With a line frequency of 50Hz, t he resolution is 360（1/900KHz）50Hz=0.02, The adjustable range is 0~2.54.  Input channel offset calibration BL6523B contains the input channel offset calibration registers (IA_CHOS, IB_CHOS, V_CHOS), these registers are in 12 -bit sign magnitude format, the default value is 0 00H. The offset may result from the analog input and the analog-digital conversion circuit itself.  Active power offset calibration BL6523B contains the active power offset calibration ( A_WA TTOS,B_W ATTOS). Both registers are in 12-bit sign magnitude format, the default value is 000H. The offset can exist in the power calculations due to crosstalk between channels on the PCB and in the BL6523B. The active power offset calibration allows these offsets to be removed to increase the accuracy of the measurement at low input power levels. WATTOS_0 XrActivePowerActivePowe   Active power gain adjustment The gain registers (A_W A TTGN, B_WA TTGN) are used t o adjust the active power measurement range. Both registers are in 12-bit sign magnitude format, the default value is 000H. The following formula shows how to adjust the output active power: _1( 12 WATTWGXPowerActiverActivePoweOutput  The minimum value that can be write to the X_WA TTGN register is 801H(HEX), which represents a gain adjustmen of -50%. The maximum value that can be write to the X_W ATTGN register is 7FFH (HEX), which represents a gain adjustmen of +50%. Similar gain calibration regisets are available for current channel A, current channel B and voltage channel (IA_CHGN, IB_CHGN, V_CHGN).  No-load threshold of active power BL6523B contains two no-load detection feature that eliminates meter creep. BL6523B can set the no -load threshold on the active power (W A_CREEP), this register is in 24-bit unsign magnitude format. The low 12-bit(WA_CREEP_L) is used to set the active power threshold value, When the absolute value of the input power signal is less than this threshold, the output active power is set to zero . This can make the active power register to 0 in no-load conditions, even a small noise signal input .

BL6523B Single Phase, Multifunction Energy meter IC 8/30 v1.0 LCREEPWAWATT LCREEPWAWATT WATTWATT __||, __||,0 The high 12-bit of WA_CREEP register(WA_CREEP_H) is used to set the active power timer threshold value. The default value is 0xFFF. There have a internal TIME_CREEP register in BL6523B, when detect the CF pulse output , the TIME_CREEP register is set to the value of WA_CREEP_H. If not detected the CF pulse output , the TIME_CREEP register value decrease. If the TIME_CREEP register decrease to 0, there is still no CF signal output, the BL6523B produce a reset signal used to reset the internal energy accumulated register of CF pulse and reload the value of W A_CREEP_H to the TOME_CREEP register. The resolution of the WA_CREEP_H is 4.6s / LSB, so the maxium timing anti-creep time is about 5h13m. MODE[6]=1 enable timing anti-creep function. MODE[6]=0 disable timing anti-creep function.  Active power compensation of small signal BL6523B contains a small active power signal compensation register ( W A_LOS), this register is in 12-bit sign magnitude format. The default value is 000H。  Reverse indicator threshold BL6523B contains a reverse indicator threshold register(WA_REVP), this register is in 12-bit unsigned magnitude format, When the input power s ignal is negative and the absolute value is greater than the power threshold，the BL6523B output the REVP indicator.  Active energy calculation The relationship between power and energy can be expressed as： dt dEnergyPower  Conversely, energy is given as the integral of power.  dtPowerEnergy In BL6523B, the active power signals are accumulated in a 53 internal registers continuously to get active energy, Active energy register WATTHR [23:0] take out this internal register[52:29] as active energy output. This discrete time accumulation is equivalent to integration in continuous time. })({)( 0    n T TnTPLimdttpE Where: n is the discrete time -sample number ; T is the sampling period ; the sampling period of BL6523B is 1.1us. The BL6523B include a interrupt ( APEHF) that is triggered When the active energy register(WATTHR) is half full. If the enable APEHF bit in the interrupt mask register set to logic high, the / IRQ output Pin goes logic low. The BL6523B include line cycle energy regis ter(LINE_WATTHR). The number of cycles is

BL6523B Single Phase, Multifunction Energy meter IC 9/30 v1.0 writen to the LINECYC register, the LSB of the LINECYC register is 0.1S. At the end of a line cycle accumulation cycle, the LINE_WATTHR regiseter is updated. The LINE_WATTHR register hold its current value until the end of the next line cycle period, when the content is replaced with the new reading. If a new value is written to the LINECYC register midway through a line cycle accumulation, the new value is not internally loaded until the end of a line cycle period.  Frequency output The BL6523B provides a energy -to-frequency conversion for calibration purpose. After initial calibration at manufacturing, the manufacturer or end customer is often required to verify the meter accuracy. One convenient way to do this is to provide an output frequency that is proportional to the active power. This output frequency provides a simple sigle-wire interface that can be optically isolated to interface to external calibration equipment. BL6523B includes a programmable calibration frequency output PIN ( CF). The digital-to-frequency converter is used to generate the pulse output. The pulse output (CF) stay high for 90ms if the pulse period is longer than 180ms. If the pulse period is shorter than 180ms, the duty cycle of de pulse o utput is 50%. The maximum output frequency with ac inputs at full scale and with WA_CFDIV=100H is approximately 0.5 kHz. The BL6523B can set the CF frequency through the WA_CF_DIV register . The default value of the W A_CFDIV register is 001H (HEX). When set W A_CFDIV[x]=1, the CF frequency is 2(x－ 4)*CFWA_CFDIV=010H.  Root mean square measurement The rms is expressed mathematically as: T rms dttVTV 2 )(1 For time-sampled signals: N i rms iVNV )(1  rms offset calibration BL6523B contains the rms offset calibration (IA_RMSOS, IB_RMSOS, V_RMSOS). These registers are in 12-bit sign magnitude format, the default value is 000H. The offset can exist in the rms calculations due to input noise that is intergrated in the dc component of square calculation. The rms offset calibration allows these offsets to be removed to increase the accuracy of the measurement at low input power levels. 172 0 2_  RMSOSIXII ARMSARMS  rms gain calibration The gain registers (IA_RMSGN, IB_RMSGN, V_RMSGN) are used to adjust the rms measurement range. Both registers are in 12-bit sign magnitude format, the default value is 000H. The following formula shows how to adjust the rms: _1( 12 RMSGNXrmsrmsOutput 

BL6523B Single Phase, Multifunction Energy meter IC 10/30 v1.0 The minimum value that can be write to the X_RMSGN register is 801H(HEX), which represents a gain adjustment of -50%. The maximum value that can be write to the X_RMSGN register is 7FFH (HEX), which represents a gain adjustment of +50%.  No-load threshold of RMS BL6523B can set the no -load threshold on the RMS_CREEP register, this register is in 12-bit unsigned magnitude format. When the value of the RMS register is less than this threshold, the RMS register is set to zero . This can make the RMS register to 0 in no-load conditions, even a small noise signal input . 3655.12_||, 3655.12_|| RMS 0RMS   CREEPRMSRMS CREEPRMSRMS  Apparent Power and Apparent Energy Calculation In BL6523B, the apparent power is defined as the product of V_RMS and IX_RMS. VA＝IX_RMS×V_RMS The apparent energy is given as the intergral of the apparent power. The apparent power signals are accumulated in an internal 49 -bit register, apparent energy register VAHR [23:0] take out this internal register [48:25] as apparent energy output . The BL6523B include a interrupt (V APEHF) that is triggered When the apparent energy register(V AHR) is half full. If the enable VAPEHF bit in the interrupt mask register set to logic high, the / IRQ output Pin goes logic low.  Power Factor PF＝ (WATT/V A) PF register is in 24-bit sign magnitude format. Power factor =(sign bit)*((PF[22]× 2^－1）＋ （PF[21]× 2^－2）＋。 。 。), the register value of 0x7FFFFF(HEX) corresponds to a power factor value of 1, the register value of 0x800000(HEX) corresponds to a power factor of -1, the register value of 0x400000(HEX) corresponds to a power factor of 0.5.  Operation Mode Select  Metering channel selection The default metering channel of BL6523B is channel A. the MODE[0] of MODE register is used to select the metering channel. MODE[0]=0, the metering channel is channel A; MODE[0]=1, the metering channel is channel B; MODE[1]=0; disable auto channel select; MODE[1]=1; enable auto channel select; when the chip detect the imbalance of two current channel, the chip select the bigger current channel as the metering channel.  High-pass filter selection In the analog -digital conversion circuit, the current and vol tage channels have high-pass filters to eliminate the DC offset. The MODE[4:2] of MODE register is used to select high -pass filter. MODE[2]=0, enable the high-pass filter of current channel A; MODE[2]=1,disable the high-pass filter of current channel A;

BL6523B Single Phase, Multifunction Energy meter IC 11/30 v1.0 MODE[3]=0, enable the high-pass filter of current channel B; MODE[3]=1,disable the high-pass filter of current channel B; MODE[4]=0, enable the high-pass filter of voltage channel; MODE[4]=1,disable the high-pass filter of voltage channel;  MODE[7]=1 When BL6523B measure AC signal, MODE[7] must be set to 1.  Energy accumulation mode selection The MODE[9:8] of the MODE regiset is used to select energy accumulation mode. MODE[9:8]=00, absolute energy accumulation; MODE[9:8]=01, positive-only energy accumulation; MODE[9:8]=10, arithmetical energy accumulation; MODE[9:8]=11, negative-only energy accumulation;;  The current imbalance judgment The BL6523B contains the detection of current imbalance. MODE[11:10] of the MODE register is used to set the current rms imbalance threshold. When the Line current rms and neutral current rms difference exceeds the threshold, the BL6523B give the FAULT indicator. MODE[11] MODE[10] Threshold 0 0 12.5%(default) 0 1 6.25% 1 0 3.125% 1 1 10.1%  Electric parameters monitor  Power Supply Monitor The BL6523B contains an on -chip power supply monitor. The analog supply (A VDD) is continuously monitored by the BL6523B. if the supply is less than 4V±5%, the BL6523B will be reset. This is useful to ensure correct device startup at power -up and power -down. The power supply monitor has built in hysteresis and filtering. This gives a high degree of immunity to false triggering due to noisy supplies. The power supply and decoupling for the part should be such that the ripple at A VDD does not exceed 5V5% as specified for normal operation.  Zero-Crossing Detection The BL6523B includes a zero -crossing detection on voltage channel. The ZX output pin

BL6523B Single Phase, Multifunction Energy meter IC 12/30 v1.0 goeshigh on positive-going edge of the voltage channel zero crossing.  Zero-Crossing Timeout The BL6523B includes a zero -crossing timeout feature that is designed to detect when no zero crossings are obtained over a programmable time period. The duration of the z ero-crossing timeout is programmed in the 16 -bit ZXTOUT register. The value in the ZXTOUT register is decremented by 1LSB e very 70.5us. if a zero -crossing is obtained, the ZXTOUT register is reloaded. If the ZXTOUT register reaches 0, a zero -crossing timeout event is issued. The maximum programmable timeout period is 4.369 secs. A interrupt is associated with the zero-crossing timeout feature. If enabled, a zero -crossing timeout event causes the external IRQ pin to go low.  Voltage Sag Detection The BL6523B includes a sag detection features that warns the user when the absolute value of the line voltage falls below the programmable threshold for a programmable number of half line cycles. The voltage sag feature is controlled by two registers: SAGLVL and SAGCYC. These registers control the sag voltage threshold and the sag period, respectively. The 12-bit SAGLVL register contains the amplitude that the voltage channel m ust fall below before sag event occurs.The sag threshold is the number of half line cycles below which the voltage channel must remain before a sag condition occurs. Each LSB of the SAGCYC register corresponds to one half line cycle period. The default value is 0xFF(HEX). At 50Hz, the maximum sag cycle time is 2.55 seconds.  Peak Detection The BL6523B continuously records the maximum value of the current and voltage channels. The three registers that record the peak values on current channel A , current channel B, and the

BL6523B Single Phase, Multifunction Energy meter IC 13/30 v1.0 voltage channel, respectively, are IAPEAK, IBPEAK, VPEAK.  Peak monitor The BL6523B include an overcurrent and overvoltage feature that detects whether the absolute value of the current or voltage waveform exceeds a programmable threshold. Three peak threshold register (IA_PKLVL, IB_PKLVL, V_PKLVL ) are used to set the current or voltage channel peak threshold, respectively. If the BL6523B detects an overvoltage condition, the PKV bit of the interrupt status register is set to 1. If the PKV bit of the interrupt mask register is enable, the IRQ output go low. The overcurrent detection feature works in the similar manner. Interrupt The BL6523B uses interrupt status register and interrupt mask register to manage interrupts. When an interrupt event occurs, the corresponding bit in the STATUS register is set to 1. If the enable bit for this interrupt, located in the MAK registe r is set to 0, the external IRQ pin is pulled to logic 0. The status bit located in the STA TUS register is set when an interrupt event occurs, regardless of whether the external interrupt is enabled. All interrupts are latched and require servicing to clear. To service the interrupt and return the IRQ pin to logic 1, the status bits mu st be cleared using the STA TUS register. After completion of a read from the STA TUS register, the IRQ pin returns to logic 1.the status bit can’t be cleared after a read operation of STAUTS register, but can be writen 0 to the corresponding bit in the status register through the SPI interface clearing the status bit.  SPI interface The SPI communication packet consists of an initial byte, The Bit [7:6] of this byte dictates whether a read or a write is being issued. The Bit [7:6] of this byte should be set to 00 for a read operation and to 01 for a write operation. The Bit [5:0] of this byte is the address of the register that is to be read from or written to. This byte should be transmitted MSB first. When this initial byte transmission is complete, the register data is either sent from the BL6523B on the DOUT pin (in the case of a read) or is written to the BL6523B DIN Pin by the external microcontroller (in the case of a write). All data is sent or received MSB first. The lenth of the data transfer is 24 bits long. The serial peripheral interface of BL6523B uses four communication pins : SCLK, DIN , DOUT and /CS. The SPI communication operates in slave mode, a clock must be provided on the SCLK pin. This clock synchronizs all communication. The DIN pin is an input to the BL6523B; data is sampled by BL6523B on the rising edge of SCLK. The DOUT pin is an output from t he BL6523B; data is shifted out on the rising edge of SCLK. The /CS ( chip select) input must be driven low to initialize the communication and driven high at the end of the communication. Driving the /CS input high before the completion of a data transfer ends the communication.  SPI Write operation Serial write sequence is shown in the figure. The Bit[7:6] of the first bytes in DIN is 01, indicate a write operation. The Bit[5:0] of this byte indicate the address of register. The last three bytes is the d ata that will be writed to the register. The data written to the BL6523B should be

BL6523B Single Phase, Multifunction Energy meter IC 14/30 v1.0 ready before the rising edge of SLCK. The SPI interface will shift the data in the BL6523B on the rising edge of SCLK. t8t7t7t3t3t2t2t1 A5 A2A4 A1A3 A0 D7 D6 D5 D4 D0D0 D7 D6 D5 /CS SCLK DIN 命令字节 数据高字节 数据低字节 min type max unit t1 /CS to the rising edge of SCLK 5000 ns t2 The high pulse width of SCLK 5000 ns t3 The low pulse width of SCLK 5000 ns t4 Data setup time before the rising edge of SCLK 3000 ns t5 Data hold time after the rising edge of SCLK 2000 ns t6 Transmission time between two bytes 80 us t7 The minimum time interval between two bytes of data 5000 ns t8 The minimu hold time of /CS after the falling edge of SCLK 5000 ns  SPI read operation Serial read sequence is shown in the figure. T he Bit[7:6] of the first bytes in DIN is 00, indicate a read operation. The Bit[5:0] of this byte indicate the address of register. The data written to the BL6523B should be ready on DIN before the rising edge of SLCK. After the BL6523B receive the address of register, the BL6523B will shift out the data of the register on DOUT pin on the rising edge of SCLK. 命令字节 t12 t11 t10t10t9t9t3t3t2t2t1 A5 A2A4 A1 A0A3 D7 D6 D5 D4 D0 D7 D6 D5 D0 /CS SCLK DIN DOUT 数据高字节 数据低字节

BL6523B Single Phase, Multifunction Energy meter IC 15/30 v1.0 min type max unit t9 The shortest interval from the End of the read command to the start of read data read 5000 ns t10 The shortest interval between two bytes of data 5000 ns t11 Data setup time after the rising edge of SCLK 10000 ns t12 Data hold time after the falling edge of SCLK 5000 ns

BL6523B Single Phase, Multifunction Energy meter IC 16/30 v1.0  Register  Register list AD DR ESS REGISTER NAME EXT ERN AL R/W INT ERN AL R/W BI T DEFA ULT DESCRIPTION ELECTRIC PARAMETERS REGISTER（INTERNAL WRITE） 01H IA_WA VE R W 24 0 Wave register of channel A 02H IB_WA VE R W 24 0 Wave register of channel B 03H V_W A VE R W 24 0 Wave register of V oltage 04H LINE_ WATTHR R W 24 0 Line cycle energy register 05H IA_RMS R W 24 0 Irms register(channel A) 06H IB_RMS R W 24 0 Irms register(channel B) 07H V_RMS R W 24 0 Vrms 08H PF R W 24 0 Power Factor 09H FREQ R W 24 0 Frequency register 0AH A_W ATT R W 24 0 Average active power of channel A 0BH VA R W 24 0 Average apparent power 0CH WATTHR R W 24 0 Active energy 0DH V AHR R W 24 0 Apparent energy 0EH PW AHR R W 24 0 Positive active energy 0FH NW AHR R W 24 0 Negative active energy 10H IA_PEAK R W 24 0 Current A Peak register 11H IB_PEAK R W 24 0 Current B Peak register 12H V_PEAK R W 24 0 V oltage Peak register 13H B_WA TT R W 24 0 Average active power of channel B Calibration registers ( External write，Except 3AH） 14H MODE R/W R 12 000H Mode regiser, 15H GAIN R/W R 12 000H Channel Gain register 16H FAULTLVL R/W R 12 044H Current imbalance shielding threshold register 17H WA_CREEP R/W R 24 FFF02 BH Active power no-load threshold register 18H WA_REVP R/W R 12 087H Reverse threshold register 19H WA_CFDIV R/W R 12 001H Active power CF frequency divider 1AH A_W ATTOS R/W R 12 0 Active power offset correction(current channel A) 1BH B_WA TTOS R/W R 12 0 Active power offset correction(current 1CH A_W ATTGN R/W R 12 0 Active power gain(current channel A)

BL6523B Single Phase, Multifunction Energy meter IC 17/30 v1.0 1DH B_WA TTGN R/W R 12 0 Active power gain(current channel B) 1EH IA_PHCAL R/W R 8 0 Phase calibration register(current channel A)(bit[7]is enable bit,2.2us/1LSB） 1FH IB_PHCAL R/W R 8 0 Phase calibration register(current channel B) 20H V_PHCAL R/W R 8 0 Phase calibration register(voltage channel) 21H V AOS R/W R 12 0 Apparent Power Offset Calibration Register 22H V AGN R/W R 12 0 Apparent power gain adjust register 23H IA_RMSGN R/W R 12 0 Current A RMS gain adjust register 24H IB_RMSGN R/W R 12 0 Current B RMS gain adjust register 25H V_RMSGN R/W R 12 0 V oltage RMS gain adjust register 26H IA_RMSOS R/W R 12 0 Current A RMS Offset Calibration register 27H IB_RMSOS R/W R 12 0 Current B RMS Offset Calibration register 28H V_RMSOS R/W R 12 0 V oltage RMS Offset Calibration register 29H RMS_CREEP R/W R 12 0 RMS small signal threshold register 2AH WA_LOS R/W R 24 0 Active-power offset Calibration register Bit[23:12] B channel; Bit[11:0] A channel; 2BH IA_CHOS R/W R 12 0 Current A channel offset adjustment register， 2CH IB_CHOS R/W R 12 0 Current B channel offset adjustment register 2DH V_CHOS R/W R 12 0 V oltage channel offset adjustment register 2EH IA_CHGN R/W R 12 0 Current A channel gain adjustment register 2FH IB_CHGN R/W R 12 0 Current B channel gain adjustment register 30H V_CHGN R/W R 12 0 V oltage channel gain adjustment register 31H LINECYC R/W R 12 000H Line energy accumulation cycles register 32H ZXTOUT R/W R 16 FFFFH Zero-crossing timeout 33H SAGCYC R/W R 8 FFH Sag period 34H SAGLVL R/W R 12 0 Sag voltage level 35H IA_PKLVL R/W R 12 FFFH Current peak threshold (current channel

BL6523B Single Phase, Multifunction Energy meter IC 18/30 v1.0 36H IB_PKLVL R/W R 12 FFFH Current peak threshold (current channel 37H V_PKLVL R/W R 12 FFFH Voltage peak threshold 38H AT_SEL R/W R 16 0 Logic output selection 39H MASK R/W R 12 0 Interrupt mask register, 3AH STA TUS R W 12 0 Interrupt state register Special register 3BH READ R R 24 0 Contains the data from the last read operation of SPI 3CH WRITE R R 24 0 Contains the data from the last write operation of SPI 3DH CHKSUM R R 24 0x0121 F2H Checksum。The sum of register 14H~39H 3EH WRPROT R/W R 8 0 Write protection register. Write 55H, it means that allows write to writable register。 Electric Parameters Registers Waveform Register (IA_WAVE,IB_WAVE,V_WAVE) Waveform Register of Current(IA_WA VE) Addr：01H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 Sign bit I_WA VE22 I_WA VE21 I_WA VE20…3 I_WA VE2 I_WA VE1 I_WA VE0 Waveform Register of Current(IB_WA VE) Addr：02H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 Sign bit I_WA VE22 I_WA VE21 I_WA VE20…3 I_WA VE2 I_WA VE1 I_WA VE0 Waveform Register of voltage(V_W A VE) Addr：03H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 Sign bit V_WA VE22 V_WA VE21 V_WA VE20…3 V_WA VE2 V_WA VE1 V_WA VE0 Note: These registers have 24 -bit complement registers, bit 23 is sign bit. The update speed of waveform register is 14 KHz. Line Cycle Energy Register (LINE_WATTHR) Line Cycle Active Energy Register of (LINE_WA TTHR) Addr：04H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 L_AHR23 L_AHR22 L_AHR21 L_AHR20…3 L_AHR2 L_AHR1 L_AHR0

BL6523B Single Phase, Multifunction Energy meter IC 19/30 v1.0 Note: Th is registers accumulate energy over (LINECYC+1)*0. 1 second. The update speed of these registers is (LINECYC+1)*0. 1 second. By using the line cycle energy accumulation mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. The accumulation time is specified in the LINECYC register. RMS Register (IA_RMS, IB_RMS and V_RMS) Irms register of Current(IA_RMS) Addr ：05H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 RMS23 RMS22 RMS21 RMS20…3 RMS2 RMS1 RMS0 Irms register of Current(IB_RMS) Addr ：06H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 RMS23 RMS22 RMS21 RMS20…3 RMS2 RMS1 RMS0 Vrms register (V_RMS) Addr ：07H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 RMS23 RMS22 RMS21 RMS20…3 RMS2 RMS1 RMS0 Note: RMS value is 24-bit unsigned data. The registers updating frequency is 10Hz. Power Factor Register (PF) Power Factor Register(PF) Addr ：08H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 PF23 PF22 PF21 PF20…3 PF2 PF1 PF0 Note: PF23 is the sign bit. 24 bit complement register. If PF23=0 then If PF23=1 then Frequency Register (FREQ) Frequency Register(FREQ) Addr ：09H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 FREQ23 FREQ22 FREQ21 FREQ20…3 FREQ2 FREQ1 FREQ0 Note: this register is the period value of the line in voltage channel. If an 3.579545MHz crystal is used, the voltage frequency= Active Power Register (A_WATT and B_WATT) Average active power (A_WATT) Addr ： 0AH Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 Sign bit WATT22 WATT21 WATT20…3 WATT2 WATT1 WATT0 Average active power (B_WATT) Addr ： Type: Read Default: 000000H

BL6523B Single Phase, Multifunction Energy meter IC 20/30 v1.0 13H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 Sign bit WATT22 WATT21 WATT20…3 WATT2 WATT1 WATT0 Note: these registers are set as binary complement. The MSB is sign bit. Register updated frequency is 2.5Hz. Assume the data in register is WATT0, then the AP for calculation is: If WATT0<2^23, AP=WA TT0; If WATT0>=2^23, AP=WA TT0-2^24; Assume the displayed active power is P, and conversion coefficiency is Kp, then P=AP/Kp; Where Kp is calculated at PF=1.0, Un, Ib. Apparent Power Register (VA) Average apparent power register(V A) Addr：0BH Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 V A23 V A22 V A21 V A20…3 V A2 V A1 V A0 Note: The coefficient of apparent power is equal to active power coefficient. Energy Registers（WATTHR,PWAHR,NWAHR,VAHR） Active Energy Register(WATTHR) Addr ： 0CH Type: Read Default：000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 WTTHR23 WATTHR22 WATTHR21 WATTHR20…3 WATTHR2 WATTHR1 WATTHR0 Apparent Energy Register(V AHR) Addr： 0DH Type: Read Default：000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 V AHR23 V AHR 22 V AHR21 VAHR20…3 V AHR2 V AHR1 V AHR0 Positive Active Energy Register(PW AHR) Addr：0EH Type: Read Default：000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 PWAHR23 PWAHR22 PWAHR21 PWAHR20…3 PWAHR2 PWAHR1 PWAHR0 Negative Active Energy Register(NWAHR) Addr：0FH Type: Read Default：000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 NWAHR23 NWAHR22 NWAHR21 NWAHR20…3 NWAHR2 NWAHR1 NWAHR0 Note: these registers cannot be clear after read.

BL6523B Single Phase, Multifunction Energy meter IC 21/30 v1.0 Peak Register (IA_PEAK, IB_PEAK and V_PEAK) Current A peak register(IA_PEAK) Addr ： 10H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 PEAK23 PEAK22 PEAK21 PEAK20…3 PEAK2 PEAK1 PEAK0 Current A peak register(IB_PEAK) Addr ： 11H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 PEAK23 PEAK22 PEAK21 PEAK20…3 PEAK2 PEAK1 PEAK0 Voltage peak register(V_PEAK) Addr ：12H Type: Read Default: 000000H Bit23 Bit22 Bit21 20…3 Bit2 Bit1 Bit0 PEAK23 PEAK22 PEAK21 PEAK20…3 PEAK2 PEAK1 PEAK0 Note: the register updating frequency is 50Hz. Calibration Registers MODE Register (MODE) MODE Register(MODE) Addr ：14H Type：R/W Default： 000H Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit location Bit mnemonic Default value

Description

0 WATT_SEL 0 The channel selection of Energy accumulation and CF output. MODE [0] =0, Current A channel. MODE [0] =1, Current B channel.

1 AUTO_SEL 0 Enable/disable Anti-tampering Mode

MODE [1] =0, disable auto-switch channel. MODE [1] =1, enable auto -switch channel. When the Line and Neutral Current differ by more than the Fault_SEL threshold, the IC will auto-switch to the channel of the larger power.

2 A_HPF_SEL 0 Enable/disable the high-pass filter of current channel A

MODE [2] =0, When measure AC signal input. MODE [2] =1, When measure DC signal input.

3 B_HPF_SEL 0 Enable/disable the high-pass filter of current channel B

4 V_HPF_SEL 0 Enable/disable the high-pass filter of voltage channel.

5 COMP_SEL 0 Anti-tampering MODE

=0, anti-tampering mode of RMS, =1, anti-tampering mode of active power.

6 ANTICREEP 0 Anti-Creep Mode

BL6523B Single Phase, Multifunction Energy meter IC 22/30 v1.0 _SEL =0, anti-creep mode of active power threshold, =1, anti -creep mode of active power threshold and time-creep.

7 This bit must be set to 1

8,9 CF_ADD_SE L

00 CF output mode for active power

MODE[9:8]=00, absolute energy pulse output; MODE[9:8]=01, positive-only energy pulse output; MODE[9:8]=10, arithmetical energy pulse output; MODE[9:8]=11, negative-only energy pulse output; 10, FAULT_SEL 00 These bits configure the L and N Line power difference threshold in anti-tampering mode Mode[11] Mode[10] Threshold 0 0 12.5% 0 1 6.25% 1 0 3.125% 1 1 10.16% Channel Gain Register (GAIN) Channel Gain Register(Gain) Addr ：15H Type：R/W Default：000H Bit[11]~Bit[8] Bit[7]~Bit[4] Bit[3]~Bit[0] V oltage channel PGA Gain Current channel B PGA Gain Current channel B PGA Gain Bit Description 11~8 V oltage PGA Gain, default value is ‘0’ Bit[11] Bit[10] Bit[9] Bit[8] PGA Gain × 0 0 0 1 × 0 0 1 2 × 0 1 0 4 × 0 1 1 8 × 1 0 0 16 × 1 0 1 24 × 1 1 0 32 7~4 Current channel B PGA Gain, default value is ‘0’ Bit[7] Bit[6] Bit[5] Bit[4] PGA Gain × 0 0 0 1 × 0 0 1 2 × 0 1 0 4 × 0 1 1 8 × 1 0 0 16 × 1 0 1 24 × 1 1 0 32 3~0 Current channel A PGA Gain, default value is ‘0’

BL6523B Single Phase, Multifunction Energy meter IC 23/30 v1.0 Bit[3] Bit[2] Bit[1] Bit[0] PGA Gain × 0 0 0 1 × 0 0 1 2 × 0 1 0 4 × 0 1 1 8 × 1 0 0 16 × 1 0 1 24 × 1 1 0 32 Imbalance Threshold Register (FAUL TLVL) Active Power Noload threshold(FAULTLVL) Addr：16H Type：R/W Default：044H Bit11 Bit10 Bit9 … Bit2 Bit1 Bit0 When the value of the RMS/WATT is less than this threshold, the fault detection can’t work. FAULTLVL=RMS_reg/256 or FAULTLVL=WATT_reg/256. Noload Threshold Register (WA_CREEP) Active Power Noload threshold(WA_CREEP) Addr：17H Type：R/W Default：FFF02BH Bit23 Bit22 Bit21 … Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 … Bit2 Bit1 Bit0 Bit[23:12] is used to set time-creep threshold. 1LSB=4.6 second. Bit[11:0] is used to set active power noload threshold. When the absolute value of the input power signal is less than this threshold, the output active power is set to zero. This can make in no -load conditions, even a small noise signal output to the active register is 0. One LSB in the W A_CREEP [11:0] register is equivalent to 0.366 LSBs in the WA TT register. Example: the value of WA TT register is 249F0H (150000) (100%Un, 100%Ib), the starting current of the meter is 0.4%Ib. the No -Load threshold value of active power can be set to 0.2%Ib*Un. (150000*0.2%=300), the value of WA_CREEP[11:0] is 300*0.366≈110(6EH) Reverse Noload Threshold Register (WA_REVP) Reverse Noload threshold(W A_REVP) Addr：18H Type：R/W Default：087H Bit11 Bit10 Bit9 … Bit2 Bit1 Bit0 WA_REVP=W ATT_reg/(32*1.3655) When the value of X_W ATT register is less than this threshold, the REVP bit of the Status register don’t update and set to 0. Note: this register only affects the status register. CF Frequency Divider Register (WA_CFDIV) CF output divider(WA_CFDIV) Addr ：19H Type：R/W Default：001H Bit11 Bit10 Bit9 … Bit2 Bit1 Bit0

BL6523B Single Phase, Multifunction Energy meter IC 24/30 v1.0 At maximum signal level ± 660mV（467mV rms） Typical value CFDIV register(30H) The frequency of CF（Hz） WATT register IA_RMS register V_RMS register 1(001H) 1.95 6500000 5650000 5650000 2(002H) 3.91 4(004H) 7.81 8(008H) 15.63 16(010H) 31.25 32(020H) 62.50 64(040H) 125.00 128(080H) 250.00 256(0100H) 500.00 Active Power Offset Register (A_WATTOS, B_WATTOS) Active power offset of channel A (A_W ATTOS) Addr：1AH Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 Active power offset of channel B (B_WA TTOS) Addr：1BH Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 Complement, Bit [11] is the sign bit. Power offset compensation in small power. Assume in small power condition (5%In, PF=1.0), error of the energy meter is Err, the data of x_WA TT register is WATT_Data. If Err<0, then x_W ATTOS=int ((WATT_Data*(-Err)/1.3655)); If Err<0, then x_W ATTOS=int((WATT_Data*(-Err)/1.3655))+4096; Active Power Gain Register (A_WATTGN, B_WATTGN) Active power gain of channel A(A_W A TTGN) Addr：1CH Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 Active power gain of channel B(B_W ATTGN) Addr：1DH Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 Complement, Bit [11] is the sign bit. Output WA TT_Reg=

BL6523B Single Phase, Multifunction Energy meter IC 25/30 v1.0 Phase Calibration Registers (IA_PHCAL,IB_PHCAL,V_ PHCAL) PHCAL Register(IA_PHCAL) Addr ：1EH Type：R/W Default：00H Enable bit Phase compensaton of current channel A D7 D6 D5 D4 D3 D2 D1 D0 PHCAL Register(IB_PHCAL) Addr ：1FH Type：R/W Default：00H Enable bit Phase compensaton of current channel B D7 D6 D5 D4 D3 D2 D1 D0 PHCAL Register(V_PHCAL) Addr ：20H Type：R/W Default：00H Enable bit Phase compensaton of voltage channel D7 D6 D5 D4 D3 D2 D1 D0 Bit[7] is enable bit, when Bit[7]＝0,disable compensation; Bit[7]＝1,enable compensation. Bit[6:0] used to adjust the delay time，1.1us/1LSB. With a line frequency of 50Hz, the resolution is 360 （1/900KHz）50Hz=0.02, The adjustable range is 0~2.54. 1LSB of register may cause the accuracy Error change 0.0605%. If Error>=0, write the adjust value to Phase compensation of current channel. If Error<0, write the adjust Value to Phase compensation of voltage channel. The value=int (|Err|/0.0605) +127. Apparent power offset Register (VA_OS) Apperant power offset (V AOS) Addr：21H Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 Complement, Bit [11] is the sign bit. V A=V A0+V AOS. Apparent Power Gain Register (VAGN) Apparent power gain (V AGN) Addr：22H Type：R/W Default： 000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 Complement, Bit [11] is the sign bit. Output V A_reg= RMS Gain Register (IA_RMSGN, IB_RMSGN and V_RMSGN) RMS gain of current A(IA_RMSGN) Addr ： 23H Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 RMS gain of current B(IB_RMSGN) Addr ： 24H Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0

BL6523B Single Phase, Multifunction Energy meter IC 26/30 v1.0 RMS gain of voltage(V_RMSGN) Addr ： 25H Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 Complement, Bit [11] is the sign bit. Output x_RMS_reg= RMS Offset Registers (IA_RMSOS, IB_RMSOS, V_RMSOS) RMS offset of current A(IA_RMSOS) Addr ： 26H Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 RMS offset of current B(IB_RMSOS) Addr ： 27H Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 RMS offset of voltage(V_RMSOS) Addr ： 28H Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 Complement, Bit [11] is the sign bit. IX_RMS= RMS Noload Threshold Register (RMS_CREEP) RMS Noload threshold(RMS_CREEP) Addr：29H Type：R/W Default：000H Bit11 Bit10～8 Bit7～4 Bit3～0 3655.12_, 3655.12_ RMS 0RMS   CREEPRMSRMS CREEPRMSRMS Please refer to chapter “No-load threshold of RMS” Small signal compensation of Active power (WA_LOS) These two registers do not need change. Keep the default value. Channel Offset Registers (IA_CHOS, IB_CHOS, V_CHOS) These two registers do not need change. Keep the default value. Calibration Gain Register (IA_CHGN, IB_CHGN, V_CHGN) Calibration gain of current A (IA_CHGN) Addr：2EH Type：R/W Default：000H

BL6523B Single Phase, Multifunction Energy meter IC 27/30 v1.0 Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 Calibration gain of current B (IB_CHGN) Addr：2FH Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 Calibration gain of V oltage (V_CHGN) Addr：30H Type：R/W Default：000H Bit11(sign bit) Bit10～8 Bit7～4 Bit3～0 Complement, Bit [11] is the sign bit. L line gain calibration is performed when PF=1.0 and the current is In. Assume the error output of the calibration bench is Err. If Err <0, then GN=int ( If Err>=0, then GN=int The Err can be calibrated when the Err range is -33.3%~+99.9% The GN value can be set to 2EH or 30H register. Line Energy Accumulation Cycle Register (LINECYC) Line Energy Cycle(LINECY) Addr ：31H Type：R/W Default：000H Bit11 Bit10 Bit9 … Bit2 Bit1 Bit0 Note: set the LINE_WATTHR, LINE_V ARHR.LINE_V AHR update period. The LSB of the LINECYC register is 0. 1S. At the end of a line cycle accumulation cycle, the LINE_WA TTHR register is updated. The LINE_WA TTHR register hold its current value until the end of the next line cycle period, when the content is replaced with the new reading. If a new value is written to the LINECYC register midway through a line cycle accumulation, the new value is not internally loaded until the end of a line cycle period. Zero-Crossing TimeOut Register (ZXTOUT) Zero-Crossing TimeOut(ZXTOUT) Addr ： 32H Type：R/W Default：FFFFH Bit15～12 Bit11～8 Bit7～4 Bit3～0 70.5uS/LSB. Please refer to chapter “Electric parameters monitor” SAG Detection Register (SAGCYC, SAGLVL) (SAGCYC) Addr ：33H Type：R/W Default：FFH D7 D6 D5 D4 D3 D2 D1 D0 10mS/LSB. (SAGLVL) Addr ：34H Type：R/W Default：FFH

BL6523B Single Phase, Multifunction Energy meter IC 28/30 v1.0 Bit11 Bit10～8 Bit7～4 Bit3～0 The value compare with V_RMS [23:12]. Please refer to chapter “Electric parameters monitor” Peak Detection Register (IA_PKLVL, IB_PKLVL,V_PKLVL) Current A peak level(IA_PKLVL) Addr ：35H Type：R/W Default：000H Bit11 Bit10～8 Bit7～4 Bit3～0 Current B peak level(V_PKLVL) Addr ：36H Type：R/W Default：000H Bit11 Bit10～8 Bit7～4 Bit3～0 Voltage peak level(V_PKLVL) Addr ：37H Type：R/W Default：000H Bit11 Bit10～8 Bit7～4 Bit3～0 Please refer to chapter “Electric parameters monitor” Logic output control register(ATT_SEL) (ATT_SEL) Addr ：38H Type：R/W Default：0000H Bit15~12 Bit11～8 Bit7～4 Bit3～0 AT3 AT2 AT1 AT0 The BL6523B contains four logic output pin(A T0~A T3) that can output some measurement states. The A T_SEL register is used to set the AT0~AT3 pin output, AT_SEL [3：0] corresponds to AT0; A T_SEL[7：4] corresponds to AT1; A T_SEL[11：8] corresponds to AT2; A T_SEL[15：12] corresponds to A T3. The default value of AT_SEL register is 0x0000, the default output is AT0=FAULT, AT1=REVP, A T2=ZX, A T3=nSAG. BIT[3:0] ATX OUTPUT DEFAULT DESCRIPTION

0000 AT0=FAULT、AT1=REVP、A T2=ZX、AT3=nSAG

0001 nSAG 0 Sag event has occurred

0010 ZXTO 0 Indicates that zero crossing has been missing on the

voltage channel for the length of time specified in the ZXTOUT register

0011 ZX 0 Voltage channel zero crossing

0100 PKIA 0 Current channel A peak has exceeded IAPKLVL

0101 PKIB 0 Current channel B peak has exceeded IBPKLVL

0110 PKV 0 Voltage peak has exceeded VPKLVL

0111 REVP 0 Sign of active power has changed to negative

1000 APEHF 0 Active energy register(WATTR) is half full

1001 V APEHF 0 Apparent energy register(V AHR) is half full

1010 FAULT 0 Fault=1 indicates the imbalance in two channels rms, the

difference is greater than the FAULTLVL

1011 CHSEL 0 0 indicates measureing power with channel A;

1 indicates measureing power with channel B;

BL6523B Single Phase, Multifunction Energy meter IC 29/30 v1.0 其余 Reversed 0 Reserved Interrupt Mask Register(MASK) Interrupt Mask Register(MASK) Addr ：39H Type:R/W Default:000H D11 D10 D9 D8…D2 D1 D0 BITS INTERRUP NAME DEFAULT DESCRIPTION

0 SAG 0 Enable the interrupt that sag event has occurred

1 ZXTO 0 Enable the interrupt of ZXTO

2 ZX 0 Enable the interrupt of ZX

3 PKIA 0 Enable the interrupt of PAIA

4 PKIB 0 Enable the interrupt of PKIB

5 PKV 0 Enable the interrupt of PKV

6 REVP 0 Enable the interrupt of REVP

7 APEHF 0 Enable the interrupt of APEHF

8 V APEHF 0 Enable the interrupt of V APEHF

9 FAULT 0 Enable the interrupt of FAULT

10 CHSEL 0 Enable the interrupt of CHSEL

Others Reversed 0 Reversed Interrupt Status Register Interrupt Status Register(STATUS) Addr ： 3AH Type:Read Default:000H D11 D10 D9 D8…D2 D1 D0 BIT LOCATION INTERRUPT FLAG DEFAULT DESCRIPTION

0 SAG 0 Indicates that an interrupt was caused by a Sag

1 ZXTO 0 Indicates that zero crossing has been missing on

the voltage channel for the length of time specified in the ZXTOUT register

2 ZX 0 Voltage channel zero crossing

3 PKIA 0 Current channel A peak has exceeded I_PKLVL

4 PKIB 0 Current channel B peak has exceeded I_PKLVL

5 PKV 0 Voltage peak has exceeded V_PKILVL

6 REVP 0 Indicates the active power has gone from positive

to negative(instantaneous power)

7 APEHF 0 Indicates that an interrupt was caused because

BL6523B Single Phase, Multifunction Energy meter IC 30/30 v1.0 WATTHR register is more than half full

8 V APEHF 0 Indicates that an interrupt was caused because

WAHR register is more than half full

9 FAULT 0 Indicates the Line and Neutral signal imbalance

10 CHSEL 0 Indicates the channel of CF output

11 VREF_LOW 0 Indicates that the reference voltage is lower than

Read/Write Register (Read/Write) Read Register(READ) Addr ：3BH Type：R 默认值：000000H Bit23 Bit22 Bit21 … Bit2 Bit1 Bit0 Write Register(WRITE) Addr ：3CH Type：R 默认值：000000H Bit23 Bit22 Bit21 … Bit2 Bit1 Bit0 Note: these register store the data that is just read or written through the UART interface. Checksum Register (CHKSUM) Checksum Register(CHKSUM) Addr ：3DH Type：R 默认值：0121F2H Bit23 Bit22 Bit21 … Bit2 Bit1 Bit0 Note: this register is the sum of register 14H~39H V alue. If the value of these register changed, the CHKSUM will be written the new value automatically. Write Protection Register (WRPROT) Write Protection Register(WRPROT) Addr ： 3EH Type：R 默认值：00H Bit7 Bit6 Bit5 … Bit2 Bit1 Bit0 Note: when the calibration registers of BL6523GX can be written after only the 55H is written to this register.