BL24C512

BL24C512 BELLING | Alldatasheet

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Shanghai Belling Corp., Ltd BL24C512 /square6 Features

• Two-Wire Serial Interface, I 2C TM Compatible – Bi-directional data transfer protocol
• Wide-voltage Operation – VCC = 1.7V to 5.5V
• Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V)
• Standby current (max.): 1 µA, 1.7V
• Operating current (max.): 2 mA, 1.7V
• Hardware Data Protection – Write Protect Pin
• Sequential & Random Read Features
• Memory organization: 65,536 x 8 bits
• Page Size: 128 bytes
• Page write mode – Up to 128 bytes per page write
• Self timed write cycle with auto clear: 5ms (max.)
• Filtered inputs for noise suppression
• High-reliability – Endurance: 1 million cycles – Data retention: 100 years
• Industrial temperature grades
• Packages: SOIC/SOP , TSSOP, DFN and CSP
• Lead-free, RoHS, Halogen free, Green /square6 Description The BL24C512 are EEPROM devices that use the industrial standard 2-wire interface for communications. The BL24C512 contains a memory array of 512K-bits (65,536x8), which is organized in 128-byte per page. The EEPROM can operate in a wide voltage range from 1.7V to 5.5V which fits most application. This product can provide a low-power 2-wire EEPROM solution. The device is offered in Lead-free, RoHS, halogen free or Green. The available package types are 8-pin SOIC/SOP , TSSOP , DFN and CSP . The BL24C512 is compatible with the industrial standard 2-wire bus protocol. If in case the bus is not responded, a new sent Op-code command will reset the bus and the device will respond correctly. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Utilizing such bus protocol, a Master device, such as a microcontroller, can usually control one or more Slave devices, alike this BL24C512. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The BL24C512 also has a Write Protect pin (WP) to allow blocking any write operations over specified memory area. Under no circumstance, the device will be hung up. In order to refrain the state machine entering into a wrong state during power-up sequence or a power toggle off-on condition, a power on reset circuit is embedded. During power-up, the device does not respond to any instructions until the supply voltage (V CC ) has reached an acceptable stable level above the reset threshold voltage. Once VCC passes the power on reset threshold, the device is reset and enters into the Standby mode. This would also avoid any inadvertent Write operations during power-up stage. During power-down process, the device will enter into standby mode, once VCC drops below the power on reset threshold voltage. In addition, the device will be in standby mode after receiving the Stop command, provided that no internal write operation is in progress. Nevertheless, it is illegal to send a command unless the VCC is within its operating level.

Shanghai Belling Corp., Ltd BL24C512 /square6 Functional Block Diagram HIGHKVOLTAGEK GENERATORK TIMINGK&K CONTROL EEPROMKARRAY YKDECODER XKDECODER DATAKREGISTER CONTROLKLOGIC WORDKADDRESSK COUNTER SLAVEKADDRESSK REGISTERK&K COMPARATOR GND WP SCL SDA VCC ACK nMOS DI/O CLOCK

Shanghai Belling Corp., Ltd BL24C512 /square6 Pin Configuration 8-Pin SOIC/SOP and TSSOP Top View 8-Lead DFN Top View VCC SCL SDA GND WP Pin Definition Pin No. Pin Name I/O Definition

1 A0 I Device Address Input

2 A1 I Device Address Input

3 A2 I Device Address Input

4 GND - Ground

5 SDA I/O Serial Address and Data input and Data out put

6 SCL I Serial Clock Input

7 WP I Write Protect Input

8 V CC - Power Supply

This input clock pin is used to synchronize the data transfer to and from the device. SDA The SDA is a bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wired with other open drain or open collector outputs. However, the SDA pin requires a pull-up resistor connected to the power supply. A0, A1, A2 The A0, A1 and A2 are the device address inputs. Typically, the A0, A1, and A2 pins are for hardware addressing and a total of 8 devices can be connected on a single bus system. When A0, A1, and A2 are left floating, the inputs are defaulted to zero. WP WP is the Write Protect pin. While the WP pin is connected to the power supply of BL24C512, the entire array becomes Write Protected (i.e. the device becomes Read only). When WP is tied to Ground or left floating, the normal write operations are allowed. V CC Supply voltage GND Ground of supply voltage

Shanghai Belling Corp., Ltd BL24C512 /square6 Device Operation The BL24C512 serial interface supports communications using industrial standard 2-wire bus protocol, such as I 2C. 2-WIRE Bus The two-wire bus is defined as Serial Data (SDA), and Serial Clock (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as receivers. The bus is controlled by Master device that generates the SCL, controls the bus access, and generates the Start and Stop conditions. The BL24C512 is the Slave device. The Bus Protocol Data transfer may be initiated only when the bus is not busy. During a data transfer, the SDA line must remain stable whenever the SCL line is high. Any changes in the SDA line while the SCL line is high will be interpreted as a Start or Stop condition. The state of the SDA line represents valid data after a Start condition. The SDA line must be stable for the duration of the High period of the clock signal. The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated by a Stop condition. Start Condition The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The EEPROM monitors the SDA and SCL lines and will not respond until the Start condition is met. Stop Condition The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must end with a Stop condition. Acknowledge After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line. Reset The BL24C512 contains a reset function in case the 2-wire bus transmission on is accidentally interrupted (e.g. a power loss), or needs to be terminated mid-stream. The reset is initiated when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.) Standby Mode While in standby mode, the power consumption is minimal. The BL24C512 enters into standby mode during one of the following conditions: a) After Power-up, while no Op-code is sent; b) After the completion of an operation and followed by the Stop signal, provided that the previous operation is not Write related; or c) After the completion of any internal write operations. Device Addressing The Master begins a transmission on by sending a Start condition, then sends the address of the particular Slave devices to be communicated. The Slave device address is 8 bits format as shown in Figure. 1-5. The four most significant bits of the Slave address are fixed (1010) for BL24C512. The next three bits, A0, A1 and A2, of the Slave address are specifically related to EEPROM. Up to eight BL24C512 units can be connected to the 2-wire bus. The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, Read operation is selected. While it is set to 0, Write operation is selected. After the Master transmits the Start condition and Slave address byte appropriately, the associated 2-wire Slave device, BL24C512, will respond with ACK on the SDA line. Then BL24C512 will pull down the SDA on the ninth clock cycle, signaling that it received the eight bits of data. The BL24C512 then prepares for a Read or Write operation by monitoring the bus. Write Operation Byte Write In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the byte address that is to be written into the address pointer of the BL24C512. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address

Shanghai Belling Corp., Ltd BL24C512 memory location. The BL24C512 acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write The BL24C512 is capable of 128-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 127 more bytes. After the receipt of each data word, the EEPROM responds immediately with an ACK on SDA line, and the seven lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 128 bytes prior to issuing the Stop condition, the address counter will “roll over,” and the previously written data will be overwritten. Once all 128 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the BL24C512 in a single Write cycle. All inputs are disabled until completion of the internal Write cycle. Acknowledge (ACK) Polling The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host's Write operation, the BL24C512 initiates the internal Write cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave address for a Write operation. If the EEPROM is still busy with the Write operation, no ACK will be returned. If the BL24C512 has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation. Read Operation Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to “1”. There are three Read operation options: current address read, random address read and sequential read. Current Address Read The BL24C512 contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the EEPROM receives the Slave Addressing Byte with a Read operation (R/W bit set to “1”), it will respond an ACK and transmit the 8-bit data byte stored at address location n+1. The Master should not acknowledge the transfer but should generate a Stop condition so the BL24C512 discontinues transmission. If 'n' is the last byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 1-8. Current Address Read Diagram.) Random Address Read Selective Read operations allow the Master device to select at random any memory location for a Read operation. The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave address and byte address of the location it wishes to read. After the BL24C512 acknowledges the byte address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one. The EEPROM then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition. (Refer to Figure 1-9. Random Address Read Diagram.) Sequential Read Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the BL24C512 sends the initial byte sequence, the Master device now responds with an ACK indicating it requires additional data from the BL24C512. The EEPROM continues to output data for each ACK received. The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data word to be read, followed by a Stop condition. The data output is sequential, with the data from address n followed by the data from address n+1,n+2 ... etc. The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operation. When the memory address boundary of the array is reached, the

Shanghai Belling Corp., Ltd BL24C512 /square6 Electrical Characteristics Absolute Maximum Ratings Symbol Parameter Value Unit VS Supply Voltage -0.5 to + 6.5 V VP Voltage on Any Pin –0.5 to V CC + 0.5 V TBIAS Temperature Under Bias –55 to +125 ° C TSTG Storage Temperature –65 to +150 ° C IOUT Output Current 5 mA Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Range Range Ambient Temperature (T A) VCC Industrial –40° C to +85° C 1.7V to 5.5V Note: Industrial grade for Commercial applications (0 °C to +70 °C). Capacitance Symbol Parameter [1, 2] Conditions Max. Unit C IN Input Capacitance VIN = 0V 6 pF C I/O Input / Output Capacitance VI/O = 0V 8 pF Notes: [1] Tested initially and after any design or process changes that may affect these parameters and not 100% tested. [2] Test conditions: T A = 25° C, f = 1 MHz, V CC = 5.0V.

Shanghai Belling Corp., Ltd BL24C512 Industrial: T A = –40°C to +85°C, VCC = 1.7V ~ 5.5V Symbol Parameter [1] VCC Test Conditions Min. Max. Unit VCC Supply Voltage 1.7 5.5 V VIH Input High Voltage 0.7*V CC V CC +1 V VIL Input Low Voltage -1 0.3* V CC V ILI Input Leakage Current 5 V V IN = VCC max -- 2 µA ILO Output Leakage Current 5V -- 2 µA VOL1 Output Low Voltage 1.7V IOL = 0.15 mA — 0.2 V VOL2 Output Low Voltage 3V IOL = 2.1 mA — 0.4 V ISB1 Standby Current 1.7V V IN = VCC or GND — 1 µA ISB2 Standby Current 2.5V V IN = VCC or GND — 2 µA ISB3 Standby Current 5V V IN = VCC or GND — 3 µA ICC1 Read Current 1.7V Read at 400 KHz — 0.5 mA 2.5V Read at 1 MHz 1 mA 5.5V Read at 1 MHz 1 mA ICC2 Write Current 1.7V Write at 400 KHz — 2 mA 2.5V Write at 1 MHz 3 mA 5.5V Write at 1 MHz 3 mA Note: The parameters are characterized but not 100% tested.

Shanghai Belling Corp., Ltd BL24C512 Industrial: T A = –40°C to +85°C, Supply voltage = 1.7V to 5.5V Symbol Parameter [1] [2] Unit FSCL SCK Clock Frequency 400 1000 1000 KHz TLOW Clock Low Period 1200 — 400 — 400 — ns THIGH Clock High Period 600 — 400 — 400 — ns TR Rise Time (SCL and SDA) — 300 — 300 — 300 ns TF Fall Time (SCL and SDA) — 300 — 100 — 100 ns TSU:STA Start Condition Setup Time 600 — 200 — 200 — ns TSU:STO Stop Condition Setup Time 600 — 200 — 200 — ns THD:STA Start Condition Hold Time 600 — 200 — 200 — ns TSU:DAT Data In Setup Time 100 — 40 — 40 — ns THD:DAT Data In Hold Time 0 — 0 — 0 — ns TAA Clock to Output Access time (SCL Low to SDA Data Out Valid) 100 900 50 400 50 400 ns TDH Data Out Hold Time (SCL Low to SDA Data Out Change) 100 — 50 — 50 — ns TWR Write Cycle Time — 5 — 5 — 5 ms TBUF Bus Free Time Before New Transmission 1000 — 400 — 400 — ns TSU:WP WP pin Setup Time 600 — 400 — 400 ns THD:WP WP pin Hold Time 1200 — 1200 — 1200 — ns T Noise Suppression Time — 100 — 50 — 50 ns Notes: [1] The parameters are characterized but not 100% tested. [2] AC measurement conditions: R L (connects to V CC ): 1.3 k Ω (2.5V, 5.0V), 10 k Ω (1.7V) C L = 100 pF Input pulse voltages: 0.3*V CC to 0.7*V CC Input rise and fall times: ≤ 50 ns Timing reference voltages: half V CC level

Shanghai Belling Corp., Ltd BL24C512 /square6 Package Information SOIC/SOP 8L 150mil SOP Package Outline MIN NOM MAX MIN NOM MAX e L 0.38 -- 1.27 0.015 0.050 ZD 0.545 REF. 0.050 BSC. 0.010 BSC. 0.021 REF. SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES 1.27 BSC. 0.25 BSC.

Shanghai Belling Corp., Ltd BL24C512 TSSOP 8L 3x4.4mm TSSOP Package Outline b MIN NOM MAX MIN NOM MAX e

0.252 BSC

0.026 BSC

SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES

0.65 BSC

6.4 BSC

Θ A 12°(4X) 0.10mm L C E E1 e D Note: 1.KControllingKDimension:MM 2.KDimensionKDKandKE1KdoKnotKincludeKMoldKprotrusion 3.KDimensionKbKdoesKnotKincludeKdambarKprotrusion/intrusion. 4.KReferKtoKJedecKstandardKMO°153KAA 5.KDrawingKisKnotKtoKscale 6.KPackageKmayKhaveKexposedKtieKbar.

Shanghai Belling Corp., Ltd BL24C512 DFN 8L 3x3mm DFN Package Outline MIN NOM MAX MIN NOM MAX D E e SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES 0.50BSC. 3.00 BSC 0.118 BSC 3.00 BSC 0.118 BSC 0.020BSC Note: 1.KControllingKDimension:MM 2.KDrawingKisKnotKtoKscale TOPKVIEW BOTTOMKVIEW SIDEKVIEW D E PIN#1KDOTKBYK MARKING e K L b A PIN#1K IDENTIFICATIONK CHAMFER