BL2046QN

BL2046QN BELLING | Alldatasheet

Document overview

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Technical content

Features

‰ 2.2V to 5.25V operation ‰ 1.5V to 5.25V digital I/O ‰ Internal 2.5V reference ‰ 4-wire I/F ‰ Programmable 8 or 12 bit Resolution ‰ Direct battery measurement(0V to 6V) ‰ Temperature measurement ‰ Touch-pressure measurement ‰ Available in QFN-16 and TSSOP-16 package General Description The BL2046 is a 4-wire touch screen controller which supports a low-voltage I/O interface from 1.5V to 5.25V. The BL2046 has an on-chip 2.5V reference that can be used for the auxiliary input, battery monitor, and temperature measurement modes. The reference can also be powered down when not used to conserve power. The internal reference operates down to 2.7V supply voltage, while monitoring the battery voltage from 0V to 6V. The BL2046 is a highly integrated controller for portable applications with 4-wire resistive touch panel such as, PDA, portable instruments, cellular phone, etc.

Applications

‰ Cellular phones ‰ Personal digital assistants ‰ Touch screen monitors ‰ Portable instruments Order Information Part Number Package Shipping BL2046QN QFN-16 3000pcs / Tape & Reel BL2046TS TSSOP-16 2500pcs / Tape & Reel http://www.belling.com.cn - 1 - Total 1 Pages

SSSS - digits from lot number Pin Description No. Pin Name Description 1 BUSY Busy Output. This output is high impedance when is high. 2 DIN Serial Data Input. If is low, data is latched on rising edge of DCLK. Chip Select Input. Controls conversion timing and enables the serial input/output register. high = power-down mode (ADC only). http://www.belling.com.cn - 2 - Total 2 Pages

4 DCLK External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O. 5 +Vcc Power Supply

6 X+ X+ Position Input

7 Y+ Y+ Position Input

8 X- X– Position Input

9 Y- Y– Position Input

10 GND Ground

11 VBAT Battery Monitor Input

12 AUX Auxiliary Input to ADC

13 VREF Voltage Reference Input/Output

14 IOVDD Digital I/O Power Supply

16 DOUT Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when is high. Typical Application Circuit Figure 1 Typical Application Circuit of the BL2046

Electrical Characteristics

At TA = –40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, digital inputs = GND or IOVDD, and +VCC must be •IOVDD, unless otherwise noted BL2046 PARAMETER CONDITIONS MIN TYP MAX UNITS REFERENCE OUTPUT Internal Reference Voltage 2.46 250 2.54 V http://www.belling.com.cn - 3 - Total 3 Pages

ppm/¥ uA ANALOG INPUT Full-Scale Input Span Absolute Input Range Capacitance Leakage Current Positive Input-Negative Input Positive Input Negative Input -0.2 -0.2 0.1 VREF +VCC+0.2 +0.2 V V V PF uA TEMPERATURE MEASUREMENT Temperature Range Resolution Accuracy Differential Method3 TEMPO:4 Differential Method3 TEMPO4 -40¥ 1.6 0.3 +85 SYSTEM PERFORMANCE Resolution No Missing Codes Integral Linearity Error Offset Error Gain Error Noise Power-Supply Rejection External VREF Including Internal VREF Bits Bits LSB1 LSB LSB uVrms dB SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter Channel-to-Channel Isolation VIN = 2.5Vp-p at 50kHz 500 100 100 125 CLKCycles CLKCycles khz ns ns ps dB BATTERY MONITOR Input Voltage Range Input Impedance Sampling Battery Battery Monitor Off Accuracy VBAT = 0.5V to 5.5V, External VREF =2.5V VBAT = 0.5V to 5.5V, Internal Reference 0.5 6.0 V kΩ G Ω REFERENCE INPUT Range Input Impedance SER%'3= D, PD1 = 0 , Internal Reference Off 1.0 +VCC V GΩ http://www.belling.com.cn - 4 - Total 4 Pages

Ω DIGITAL INPUTfOUTPUT Logic Family VIH VIL VOH VOL Data Format *ɖI)ɖ›+5uA *ɖI-ɖ›+5uA LOH = -250 uA LOL = 250uA IOVD%·0.7 -0.3 IOVDD·0.8 CMOS Straight Binary IOVDD+0.3 0.3 • IOVDD 0.4 V V V V POWER-SUPPLY REQUIREMENTS +VCC IOVDO6 Quiescent Current7 Power Dissipation Specified Performance Operating Range Internal Reference Off Internal Reference On fSAMPLE= 12.5kHz Power-Down Mode with %$-, %*/ *07%% +VCC=+2.7V 2.7 2.2 1.5 280 780 220 3.6 5.25 +VCC 650 1.8 V V V uA uA uA uA mW TEMPERATURE RANGE Specified Performance +85 SWITCH DRIVERS Qn-Resistance Y+, X+ Y-.X- Drive Current2 Duration 100ms Ω Ω mA NOTES: (1) LSB means least significant bit. With VREF = +2.5V, one LSB is 610µV. (2) Assured by design, but not tested. Exceeding 50mA source current may result in device degradation. (3) Difference between TEMP0 and TEMP1 measurement, no calibration necessary. (4) Temperature drift is –2.1mV/°C. (5) BL2046 operates down to 2.2V. (6) IOVDD must be - +VCC. (7) Combined supply current from +VCC and IOVDD. Typical values obtained from conversions on AUX input with PD0 = 0. Analog Input Table 1 and Table 2 show the relationship between the A2, A1, A0, and SER/ control bits and the configuration of the BL2046. The control bits are provided serially via the DIN pin (see the Digital Interface section of this data sheet for more details). When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The input current into the analog inputs depends on the http://www.belling.com.cn - 5 - Total 5 Pages

sampling capacitor . After the capacitor has been fully charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a function of conversion rate. TABLE 1. Input Configuration (DIN), Single-Ended Reference Mode (SER/ TABLE 2. Input Configuration (DIN), Differential Reference Mode (SER/ screen performance is achieved when using the differential mode. inherent in the ADC appears to increase, in terms of LSB size, as the reference voltage is reduced. adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. portion of the BL2046. Therefore, the input current is very low. drivers are ON. For this discussion, it is useful to consider the typical application of the BL2046.

track the resistance of the touch screen, providing an additional source of error. Figure 2. Diagram of Single-Ended Reference (SER/ resistance, regardless of how it changes in relation to the on-resistance of the internal switches. ratiometric mode of operation. current for the external load (such as a resistive touch screen).

Figure 3. Diagram of Differential Reference (SER/ by the processor (see Figure 11).

equivalent temperature measurement resolution of 0.3°C/LSB (in 12-bit mode). Figure 4. Functional Block Diagram of Temperature Measurement Mode. method to eliminate the need for absolute temperature calibration and for achieving 2°C accuracy.

especially if the temperature measurement only occurs occasionally. (VBAT) is divided down by 4 so that a 5.5V battery voltage is represented as 1.375V to the ADC. the relationship between the control bits and configuration of the BL2046). Figure 5. Battery Measurement Functional Block Diagram.

accomplished with three serial communications for a total of 24 clock cycles on the DCLK input. (DOUT will be low), which are ignored by the converter. information regarding the order and description of these control bits within the control byte. TABLE 3. Order of the Control Bits in the Control Byte. clock cycle in 8-bit conversion mode (see Figure 11). the next conversion: 12-bits (low) or 8-bits (high). inputs (see Tables 1 and 2). Power-Down Mode Select bits. Refer to Table V for details. TABLE 4. Descriptions of the Control Bits within the Control Byte. control byte. The BL2046 ignores inputs on the DIN pin until the start bit is detected.

Addressing— The next three bits (A2, A1, and A0) select the active input channel(s) of the input multiplexer (see Tables 1, 2), touch screen drivers, and the reference inputs. MODE— The mode bit sets the resolution of the ADC. With this bit low, the next conversion has 12 bits of resolution, whereas with this bit high, the next conversion has 8 bits of resolution. SER/ — The SER/ bit controls the reference mode, either single-ended (high) or differential (low). The differential mode is also referred to as the ratiometric conversion mode and is preferred for X-Position, Y-Position, and Pressure- Touch measurements for optimum performance. The reference is derived from the voltage at the switch drivers, which is almost the same as the voltage to the touch screen. In this case, a reference voltage is not needed as the reference voltage to the ADC is the voltage across the touch screen. In the single-ended mode, the converter reference voltage is always the difference between the VREF and GND pins. If X-Position, Y-Position, and Pressure-Touch are measured in the single-ended mode, an external reference voltage is needed. The BL2046 must also be powered from the external reference. Caution should be observed when using the single-ended mode such that the input voltage to the ADC does not exceed the internal reference voltage, especially if the supply voltage is greater than 2.7V. NOTE: The differential mode can only be used for X-Position, Y-Position, and Pressure-Touch measurements. All other measurements require the single-ended mode. PD0 and PD1— Table 5 describes the power-down and the internal reference voltage configurations. The internal reference voltage can be turned on or off independently of the ADC. This can allow extra time for the internal reference voltage to settle to the final value prior to making a conversion. Make sure to also allow this extra wake-up time if the internal reference is powered down. The ADC requires no wake-up time and can be instantaneously used. Also note that the status of the internal reference power-down is latched into the part (internally) with BUSY going high. In order to turn the reference off, an additional write to the BL2046 is required after the channel has been converted. http://www.belling.com.cn - 13 - Total 13 Pages

Figure 7. Conversion Timing, 24 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.

DESCRIPTION

Power-Down Between Conversions. When each conversion is finished, the converter enters a low-power mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to ensure full operation, and the very first conversion is valid. The Y– switch is on when in power-down. Reference is off and ADC is on. Reference is on and ADC is off. Device is always powered. Reference is on andADC is ON. TABLE 5. Power-Down and Internal Reference Selection. input is pulled to ground through the touch screen. terminals must be less than 21kΩ.

The -90 version of the BL2046 uses a nominal 90kΩ pullup resistor, which allows the total resistance between the X+ and Y- terminals to be as high as 30kΩ. Note that the higher pullup resistance will cause a slower response time of the to a screen touch, so user software should take this into account. The output goes low due to the current path through the touch screen to ground, which initiates an interrupt to the processor. During the measurement cycle for X-, Y-, and Z-Position, the X+ input is disconnected from the internal pull-up resistor. This is done to eliminate any leakage current from the internal pull-up resistor through the touch screen, thus causing no errors. Figure 8. Functional Block Diagram. Furthermore, the output is disabled and low during the measurement cycle for X-, Y-, and Z-Position. The output is disabled and high during the measurement cycle for battery monitor, auxiliary input, and chip temperature. If the last control byte written to the BL2046 contains PD0 = 1, the pen-interrupt output function is disabled and is not able to detect w hen the screen is touched. In order to re-enable the pen-interrupt output function under these circumstances, a control byte needs to be written to the BL2046 with PD0 = 0. If the last control byte written to the BL2046 contains PD0 = 0, the pen-interrupt output function is enabled at the end of the conversion. The end of the conversion occurs on the falling edge of DCLK after bit 1 of the converted data is clocked out of the BL2046. http://www.belling.com.cn - 15 - Total 15 Pages

output is disabled in the cases discussed in this section. Figure 9. Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.

16 Clocks-per-Conversion

communications are taking place during a conversion.

TABLE 6. Timing Specifications, TA = –40°C to +85°C. Figure 10. Detailed Timing Diagram.

Figure 11. Maximum Conversion Rate, 15 Clocks-per-Conversion. Figures 7 and 10 and Table 6 provide detailed timing for the digital interface of the BL2046.

15 Clocks-per-Conversion

Figure 12. Ideal Input Voltages and Output Codes.

Figure 11 provides the fastest way to clock the BL2046. This method does not work with the serial interface of most microcontrollers and digital signal processors, as they are generally not capable of providing 15 clock cycles per serial transfer. However, this method can be used with field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Note that this effectively increases the maximum conversion rate of the converter beyond the values given in the specification tables, which assume 16 clock cycles per conversion. Data Format The BL2046 output data is in Straight Binary format, as shown in Figure 12. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. 8-Bit Conversion The BL2046 provides an 8-bit conversion mode that can be used when faster throughput is needed and the digital result is not as critical. By switching to the 8-bit mode, a conversion is complete four clock cycles earlier. Not only does this shorten each conversion by four bits (25% faster throughput), but each conversion can actually occur at a faster clock rate. This is because the internal settling time of the BL2046 is not as critical—settling to better than 8 bits is all that is needed. The clock rate can be as much as 50% faster. The faster clock rate and fewer clock cycles combine to provide a 2x increase in conversion rate. Power Dissipation There are two major power modes for the BL2046: full-power (PD0 = 1) and auto power-down (PD0 = 0). When operating at full speed and 16 clocks-per-conversion (see Figure 9), the BL2046 spends most of the time acquiring or converting. There is little time for auto power-down, assuming that this mode is active. Therefore, the difference between full-power mode and auto power-down is negligible. If the conversion rate is decreased by slowing the frequency of the DCLK input, the two modes remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion but conversions are done less often, the difference between the two modes is dramatic. also puts the BL2046 into power-down mode. When goes high, the BL2046 immediately goes into power-down mode and does not complete the current conversion. The internal reference, however, does not turn off with going high. To turn the reference off, an additional write is required before goes high (PD1 = 0). When the BL2046 first powers up, the device draws about 20µA of current until a control byte is written to it with PD0 = 0 to put it into power-down mode. This can be avoided if the BL2046 is powered up with = 0 and DCLK = IOVDD. http://www.belling.com.cn - 19 - Total 19 Pages

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