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Dear customer, As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors, which will be used in future data sheets together with new contact details. In data sheets where the previous Philips references remain, please use the new links as shown below. (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - © Koninklijke Philips Electronics N.V. (year). All rights reserved - is replaced with: - © NXP B.V. (year). All rights reserved. - If you have any questions related to the data sheet, please contact our nearest sales ofﬁce via e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding, NXP Semiconductors BF904; BF904R N-channel dual gate MOS-FETs Rev. 06 — 13 November 2007 Product data sheet

NXP Semiconductors Product speciﬁcation N-channel dual gate MOS-FETs BF904; BF904R FEA TURES

Specially designed for use at 5V supply voltage
Short channel transistor with high transfer admittance to input capacitance ratio
Low noise gain controlled amplifier up to 1GHz
Superior cross-modulation performance during AGC. APPLICA TIONS
VHF and UHF applications with 3 to 7V supply voltage such as television tuners and professional communications equipment.

DESCRIPTION

Enhancement type field-effect transistor in a plastic microminiature SOT143B and SOT143R package. The transistor consists of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. PINNING CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. PIN SYMBOL DESCRIPTION 1 s, b source 2 d drain 3g 2 gate2 4g 1 gate1 Fig.1 Simplified outline (SOT143B) and symbol. BF904 marking code: %MC. handbook, halfpage Top view MAM124 s,b d Fig.2 Simplified outline (SOT143R) and symbol. BF904R marking code: %MD. handbook, halfpage Top view MAM125 - 1 s,b d QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage −− 7V ID drain current −− 30 mA Ptot total power dissipation −− 200 mW Tj operating junction temperature −− 150 °C yfs forward transfer admittance 22 25 30 mS C ig1-s input capacitance at gate 1 − 2.2 2.6 pF C rs reverse transfer capacitance f = 1 MHz − 25 35 fF F noise ﬁgure f = 800 MHz − 2 − dB Rev. 06 - 13 November 2007 2 of 14

NXP Semiconductors Product speciﬁcation N-channel dual gate MOS-FETs BF904; BF904R LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Note 1. Device mounted on a printed-circuit board. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage − 7V ID drain current − 30 mA IG1 gate1 current −± 10 mA IG2 gate2 current −± 10 mA Ptot total power dissipation see Fig.3 BF904 Tamb ≤ 50 °C; note1 − 200 mW BF904R Tamb ≤ 40 °C; note1 − 200 mW Tstg storage temperature −65 +150 °C Tj operating junction temperature − 150 °C Fig.3 Power derating curves. handbook, halfpage 100 150 200 250 0 50 100 150 200 Ptot (mW) MRA770 Tamb ( C)o BF904 BF904R Rev. 06 - 13 November 2007 3 of 14

NXP Semiconductors Product speciﬁcation N-channel dual gate MOS-FETs BF904; BF904R THERMAL CHARACTERISTICS Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj=2 5 °C unless otherwise speciﬁed. Note 1. R G1 connects gate1 to VGG = 5 V; see Fig.20. DYNAMIC CHARACTERISTICS Common source; Tamb =2 5 °C; VDS = 5 V; VG2-S = 4 V; ID = 10 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS VALUE UNIT R th j-a thermal resistance from junction to ambientnote1 BF904 500 K/W BF904R 550 K/W R th j-s thermal resistance from junction to soldering pointnote2 BF904 Ts =9 2 °C 290 K/W BF904R Ts =7 8 °C 360 K/W SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)G1-SS gate1-source breakdown voltage VG2-S =V DS = 0; IG1-S = 10 m A 6 15 V V(BR)G2-SS gate2-source breakdown voltage VG1-S =V DS = 0; IG2-S = 10 m A 6 15 V V(F)S-G1 forward source-gate1 voltage VG2-S =V DS = 0; IS-G1 = 10 m A 0.5 1.5 V V(F)S-G2 forward source-gate2 voltage VG1-S =V DS = 0; IS-G2 = 10 m A 0.5 1.5 V VG1-S(th) gate1-source threshold voltage VG2-S =4V ; VDS =5V ; ID =2 0 µA 0.3 1 V VG2-S(th) gate2-source threshold voltage VG1-S =V DS =5V ; ID =2 0 µA 0.3 1.2 V IDSX drain-source current VG2-S =4V ; VDS =5V ; R G1 = 120 kΩ ; note1 81 3 m A IG1-SS gate1 cut-off current VG2-S =V DS = 0; VG1-S =5V − 50 nA IG2-SS gate2 cut-off current VG1-S =V DS = 0; VG2-S =5V − 50 nA SYMBOL PARAMETER CONDITIONS MIN. TYP . MAX. UNIT yfs forward transfer admittancepulsed; Tj=2 5 °C 222 53 0m S C ig1-s input capacitance at gate1 f= 1 MHz − 2.2 2.6 pF C ig2-s input capacitance at gate2 f= 1 MHz 1 1.5 2 pF C os drain-source capacitance f= 1 MHz 1 1.3 1.6 pF C rs reverse transfer capacitancef= 1 MHz − 25 35 fF F noise ﬁgure f= 200 MHz; GS = 2 mS; BS =B Sopt − 1 1.5 dB f= 800 MHz; GS =G Sopt; BS =B Sopt − 2 2.8 dB Rev. 06 - 13 November 2007 4 of 14

NXP Semiconductors Product speciﬁcation N-channel dual gate MOS-FETs BF904; BF904R Fig.4 Transfer admittance as a function of the junction temperature; typical values. 50 0 50 150 MLD268 100 T ( C)o j Y fs (mS) Fig.5 Typical gain reduction as a function of the AGC voltage. f = 50 MHz. handbook, halfpage0 01234 V (V)AGC gain reduction (dB) MRA769 Fig.6 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.20. VDS = 5 V; VGG = 5 V; fw = 50 MHz. funw = 60 MHz; Tamb =2 5°C; RG1 = 120 kΩ. handbook, halfpage 100 110 120 0 1 02 03 04 05 0 Vunw (dB V) gain reduction (dB) MRA771 µ Fig.7 Transfer characteristics; typical values. VDS =5V . Tj=2 5°C. 0.4 2.0 MLD270 0.8 1.2 1.6 ID (mA) V (V)G1 S 2 V 1.5 V 1 V V = 4 V3 V 2.5 VG2 S Rev. 06 - 13 November 2007 5 of 14

NXP Semiconductors Product speciﬁcation N-channel dual gate MOS-FETs BF904; BF904R Fig.8 Output characteristics; typical values. VG2-S =4V . Tj=2 5°C. handbook, halfpage 21 0 MLD269 468 ID (mA) V (V)DS 1.3 V 1.2 V 1.1 V 1.0 V 0.9 V V = 1.4 VG1 S Fig.9 Gate 1 current as a function of gate 1 voltage; typical values. VDS =5V . Tj=2 5°C. handbook, halfpage 150 100 0.5 2.5 MLD271 1.0 1.5 2.0 IG1 (µA) V (V)G1 S 3.5 V 2.5 V 2 V 3 V V = 4 VG2 S Fig.10 Forward transfer admittance as a function of drain current; typical values. VDS =5V . Tj=2 5°C. handbook, halfpage 4 8 12 16 20 MLD272 yfs (mS) I (mA)D 3 V 2.5 V 2 V V = 4 VG2 S 3.5 V Fig.11 Drain current as a function of gate 1 current; typical values. VDS =5V . VG2-S =4V . Tj=2 5°C. handbook, halfpage 10 50 MLD273 20 30 40 ID (mA) I (µA)G1 Rev. 06 - 13 November 2007 6 of 14

NXP Semiconductors Product speciﬁcation N-channel dual gate MOS-FETs BF904; BF904R Fig.12 Drain current as a function of gate 1 supply voltage (= VGG ); typical values; see Fig.20. VDS = 5 V; VG2-S =4V . R G1 = 120 kΩ (connected to VGG ); Tj=2 5°C. handbook, halfpage MLD275 234 ID (mA) V (V)GG Fig.13 Drain current as a function of gate 1 (= VGG ) and drain supply voltage; typical values; see Fig.20. VG2-S =4V . R G1 connected to VGG ; Tj=2 5°C. handbook, halfpage 24 8 MLD274 V = V (V)GG DS ID (mA) R = 47 kΩG1 68 kΩ 82 kΩ 100 kΩ 120 kΩ 150 kΩ 180 kΩ 220 kΩ VDS = 5 V; Tj=2 5°C. R G1 = 120 kΩ (connected to VGG ). Fig.14 Drain current as a function of gate 2 voltage; typical values; see Fig.20. handbook, halfpage 0246 MLD276 ID (mA) 4.5 V 4 V 3.5 V 3 V V (V)G2 S V = 5 VGG Fig.15 Gate 1 current as a function of gate 2 voltage; typical values; see Fig.20. VDS = 5 V; Tj=2 5°C. R G1 = 120 kΩ (connected to VGG ). handbook, halfpage 0246 MLB945 IG1 (µA) V (V)G2 S 4.5 V 4 V 3.5 V 3 V V = 5 VGG Rev. 06 - 13 November 2007 7 of 14

NXP Semiconductors Product speciﬁcation N-channel dual gate MOS-FETs BF904; BF904R Fig.16 Input admittance as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 15 mA; Tamb =2 5°C. handbook, halfpage 103 MLD277 10210 10 1 10 2 yis (mS) f (MHz) bis gis Fig.17 Reverse transfer admittance and phase as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 15 mA; Tamb =2 5°C. 103 MLD278 10210 10 3 10 2 yrs 10 3 rs (µS) f (MHz) rs yrs (deg) ϕ ϕ Fig.18 Forward transfer admittance and phase as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 15 mA; Tamb =2 5°C. 103 MLD279 10210 10 2 yfs (mS) yfs f (MHz) fs fs (deg) ϕ ϕ Fig.19 Output admittance as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 15 mA; Tamb =2 5°C. handbook, halfpage 103 MLD280 10210 10 1 10 2 yos (mS) f (MHz) bos gos Rev. 06 - 13 November 2007 8 of 14

NXP Semiconductors Product speciﬁcation N-channel dual gate MOS-FETs BF904; BF904R Fig.20 Cross-modulation test set-up. DUT VAGC 4.7 nF 10 kΩ MLD171 4.7 nF 450 nH C3 12 pF R L 50 Ω≈ VGG V DS R GEN V I 4.7 nF R G1Ω Ω Rev. 06 - 13 November 2007 9 of 14

NXP Semiconductors Product speciﬁcation N-channel dual gate MOS-FETs BF904; BF904R Table 1 Scattering parameters:VDS =5 V; VG2-S = 4 V; ID =1 0m A Table 2 Noise data:VDS = 5 V; VG2-S = 4 V; ID =1 0m A f (MHz) S11 S21 S12 S22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) f (MHz) Fmin (dB) Γopt rn (ratio) (deg) 800 2.00 0.686 49.6 50.40 Rev. 06 - 13 November 2007 10 of 14

NXP Semiconductors Product speciﬁcation N-channel dual gate MOS-FETs BF904; BF904R PACKAGE OUTLINES UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 1.1 0.9 A 1 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 H E ywvQ 2.5 2.1 0.45 0.15 0.55 0.45 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143B 97-02-28 0 1 2 mm scale Plastic surface mounted package; 4 leads SOT143B D H E E AB v M A X A Lp Q detail X c y w M e B bp Rev. 06 - 13 November 2007 11 of 14

NXP Semiconductors Product speciﬁcation N-channel dual gate MOS-FETs BF904; BF904R UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 1.1 0.9 A 1 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 H E ywvQ 2.5 2.1 0.55 0.25 0.45 0.25 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143R 97-03-10 0 1 2 mm scale Plastic surface mounted package; reverse pinning; 4 leads SOT143R D H E E AB v M A X A Lp Q detail X c y w M e B bp Rev. 06 - 13 November 2007 12 of 14

NXP Semiconductors BF904; BF904R N-channel dual gate MOS-FETs Legal information Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Deﬁnitions Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail. Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Contact information For additional information, please visit:http://www.nxp.com For sales ofﬁce addresses, send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation. Rev. 06 - 13 November 2007 13 of 14

NXP Semiconductors BF904; BF904R N-channel dual gate MOS-FETs © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 November 2007 Document identifier: BF904_904R_N_6 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

Revision history

Document ID Release date Data sheet status Change notice Supersedes BF904_904R_N_6 20071113 Product data sheet - BF904_904R_5 Modiﬁcations: • Fig. 1 and 2 on page 2; Figure note changed BF904_904R_5 (9397 750 05898)

19990517 Product speciﬁcation - BF904R_4

BF904R_4 (9397 750 02668)

19970905 Product speciﬁcation - BF904R_3

BF904R_3 19950425 Product speciﬁcation - BF904R_2 BF904R_2 - - - BF904R_1 BF904R_1 - - - -

Product Information

BF904 specifications and overview.

Summary

N-channel dual gate MOS-FETs

Description

N-channel dual gate MOS-FETs

Source title BF904_15 Datasheet(PDF) - Quanzhou Jinmei Electronic Co.,Ltd.

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